coreboot-mirror
/
coreboot
mirror of https://review.coreboot.org/coreboot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

soc/intel/meteorlake: Refactor heci finalize functions 

This patch creates a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again FSP config.

Currently, `heci_set_to_d0i3()` function is getting called twice.

BUG=b:260041679
TEST=Able to build google/rex with this patch and observe coreboot log
modification as below:

Without this patch:

[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms

With this patch:

[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-11-24 19:42:55 +05:30
parent a3c0ba12eb
commit fb970a43bd
1 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/intel/meteorlake/finalize.c
View File

@ -64,6 +64,13 @@ static void sa_finalize(void)
sa_lock_pam();
}
static void heci_finalize(void)
{
heci_set_to_d0i3();
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
heci1_disable();
}
static void soc_finalize(void *unused)
{
printk(BIOS_DEBUG, "Finalizing chipset.\n");
@ -72,9 +79,9 @@ static void soc_finalize(void *unused)
apm_control(APM_CNT_FINALIZE);
tbt_finalize();
sa_finalize();
heci_set_to_d0i3();
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
heci1_disable();
if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
heci_finalize();
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);