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New mechanism to define SRAM/memory map with automatic bounds checking 

This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Julius Werner 2014-08-20 15:29:56 -07:00 committed by Patrick Georgi
parent 06ef046045
commit ec5e5e0db2
158 changed files with 1536 additions and 2098 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Makefile.inc
View File

@ -456,6 +456,11 @@ tools: $(objutil)/kconfig/conf $(objutil)/cbfstool/cbfstool $(objutil)/cbfstool/
# Common recipes for all stages
###########################################################################
# loadaddr can determine the load address of a stage, which may be needed for
# platform-specific image headers (only works *after* the stage has been built)
loadaddr = $(shell $(OBJDUMP_$(1)) -p $(objcbfs)/$(1).debug | \
sed -ne '/LOAD/s/^.*vaddr 0x\([0-9a-fA-F]\{8\}\).*$$/0x\1/p')
# find-substr is required for stages like romstage_null and romstage_xip to
# eliminate the _* part of the string
find-substr = $(word 1,$(subst _, ,$(1)))

29
src/arch/arm/Makefile.inc
View File

@ -63,11 +63,9 @@ bootblock-y += memmove.S
bootblock-y += div0.c
bootblock-y += clock.c
bootblock-y += bootblock.ld
$(objcbfs)/bootblock.debug: $(obj)/arch/arm/bootblock.bootblock.ld $$(bootblock-objs) $$(VERSTAGE_LIB)
$(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/arm/bootblock.bootblock.ld --start-group $(bootblock-objs) --end-group
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
endif # CONFIG_ARCH_BOOTBLOCK_ARM
@ -75,9 +73,9 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM
# verification stage
###############################################################################
$(objcbfs)/verstage.debug: $$(verstage-objs) $(obj)/arch/arm/verstage.verstage.ld $$(VB2_LIB)
$(objcbfs)/verstage.debug: $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $$(VB2_LIB)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/arm/verstage.verstage.ld --start-group $(verstage-objs) --end-group
$(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(verstage-objs) --end-group
verstage-y += div0.c
verstage-y += eabi_compat.c
@ -86,8 +84,6 @@ verstage-y += memcpy.S
verstage-y += memmove.S
verstage-y += stages.c
verstage-y += verstage.ld
###############################################################################
# romstage
###############################################################################
@ -107,13 +103,11 @@ rmodules_arm-y += memcpy.S
rmodules_arm-y += memmove.S
rmodules_arm-y += eabi_compat.c
romstage-y += romstage.ld
VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/arm/romstage.romstage.ld
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/arm/romstage.romstage.ld --start-group $(romstage-objs) --end-group
$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
endif # CONFIG_ARCH_ROMSTAGE_ARM
@ -133,20 +127,15 @@ ramstage-y += memset.S
ramstage-y += memcpy.S
ramstage-y += memmove.S
ramstage-y += clock.c
rmodules_arm-y += memset.S
rmodules_arm-y += memcpy.S
rmodules_arm-y += memmove.S
rmodules_arm-y += eabi_compat.c
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
ramstage-y += ramstage.ld
$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/arm/ramstage.ramstage.ld
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/arch/arm/ramstage.ramstage.ld --start-group $(ramstage-objs) --end-group
$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group
$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
endif # CONFIG_ARCH_RAMSTAGE_ARM

20
src/arch/arm/armv4/bootblock.S
View File

@ -44,10 +44,8 @@ ENTRY(_start)
* Initialize the stack to a known value. This is used to check for
* stack overflow later in the boot process.
*/
ldr r0, .Stack
ldr r1, .Stack_size
sub r0, r0, r1
ldr r1, .Stack
ldr r0, =_stack
ldr r1, =_estack
ldr r2, =0xdeadbeef
init_stack_loop:
str r2, [r0]
@ -57,7 +55,7 @@ init_stack_loop:
/* Set stackpointer in internal RAM to call bootblock main() */
call_bootblock:
ldr sp, .Stack /* Set up stack pointer */
ldr sp, =_estack /* Set up stack pointer */
ldr r0,=0x00000000
/*
* The current design of cpu_info places the
@ -75,15 +73,3 @@ call_bootblock:
*/
bl main
ENDPROC(_start)
/* we do it this way because it's a 32-bit constant and
* in some cases too far away to be loaded as just an offset
* from IP
*/
.align 2
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in coreboot_ram.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

20
src/arch/arm/armv7/bootblock.S
View File

@ -62,10 +62,8 @@ ENTRY(_thumb_start)
* Initialize the stack to a known value. This is used to check for
* stack overflow later in the boot process.
*/
ldr r0, .Stack
ldr r1, .Stack_size
sub r0, r0, r1
ldr r1, .Stack
ldr r0, =_stack
ldr r1, =_estack
ldr r2, =0xdeadbeef
init_stack_loop:
str r2, [r0]
@ -75,7 +73,7 @@ init_stack_loop:
/* Set stackpointer in internal RAM to call bootblock main() */
call_bootblock:
ldr sp, .Stack /* Set up stack pointer */
ldr sp, =_estack /* Set up stack pointer */
ldr r0,=0x00000000
/*
* The current design of cpu_info places the struct at the top of the
@ -89,15 +87,3 @@ wait_for_interrupt:
wfi
mov pc, lr @ back to my caller
ENDPROC(_thumb_start)
/* we do it this way because it's a 32-bit constant and
* in some cases too far away to be loaded as just an offset
* from IP
*/
.align 2
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in coreboot_ram.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

5
src/arch/arm/armv7/mmu.c
View File

@ -31,6 +31,7 @@
#include <config.h>
#include <stdlib.h>
#include <stdint.h>
#include <symbols.h>
#include <cbmem.h>
#include <console/console.h>
@ -90,7 +91,7 @@ typedef uint32_t pmd_t;
static const unsigned int denom = 1;
#endif /* CONFIG_ARM_LPAE */
static pmd_t *const ttb_buff = (pmd_t *)CONFIG_TTB_BUFFER;
static pmd_t *const ttb_buff = (pmd_t *)_ttb;
/*
* mask/shift/size for pages and blocks
@ -186,7 +187,7 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
void mmu_init(void)
{
if (CONFIG_ARM_LPAE) {
pgd_t *const pgd_buff = (pgd_t*)(CONFIG_TTB_BUFFER + 16*KiB);
pgd_t *const pgd_buff = (pgd_t*)(_ttb + 16*KiB);
pmd_t *pmd = ttb_buff;
int i;

37
src/arch/arm/bootblock.ld → src/arch/arm/include/arch/header.ld
View File

@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -27,34 +26,8 @@ PHDRS
to_load PT_LOAD;
}
#ifdef __BOOTBLOCK__
ENTRY(_start)
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
.bootblock . : {
*(.text._start);
KEEP(*(.id));
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
*(.bss);
*(.bss.*);
*(.sbss);
*(.sbss.*);
_end = .;
} : to_load = 0xff
preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.ARM.*)
}
}
#else
ENTRY(stage_entry)
#endif

38
src/arch/arm/include/arch/memlayout.h Normal file
View File

@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
#define TTB(addr, size) \
REGION(ttb, addr, size, 16K) \
_ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \
"TTB must be 16K (+ 32 for LPAE)!");
/* ARM stacks need 8-byte alignment and stay in one place through ramstage. */
#define STACK(addr, size) REGION(stack, addr, size, 8)
#define DMA_COHERENT(addr, size) \
REGION(dma_coherent, addr, size, (1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) \
_ = ASSERT(size % ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) == 0, \
"DMA coherency buffer must fit exactly in full superpages!");
#endif /* __ARCH_MEMLAYOUT_H */

2
src/arch/arm/include/arch/stages.h
View File

@ -22,7 +22,7 @@
extern void main(void);
void stage_entry(void) __attribute__((section(".text.stage_entry.arm")));
void stage_entry(void);
void stage_exit(void *);
#endif

134
src/arch/arm/ramstage.ld
View File

@ -1,134 +0,0 @@
/*
* Memory map:
*
* CONFIG_RAMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_RAMSTAGE_BASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_text = .;
_start = .;
*(.text.stage_entry.arm);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
_rodata = .;
. = ALIGN(4);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
LONG(0);
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
/* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
*/
. = ALIGN(4);
_erodata = .;
}
/* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
* whereas __data_loadstart and __data_loadend shows where in rom to
* copy from.
*/
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
.bss . : {
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
/* coreboot really "ends" here. Only heap and stack are placed after
* this line.
*/
.heap . : {
_heap = .;
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = CONFIG_HEAP_SIZE ;
. = ALIGN(4);
_eheap = .;
}
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* The stack lives in SRAM in a different location, so keep
* it out of ram_seg
*/
_stack = CONFIG_STACK_BOTTOM;
_estack = CONFIG_STACK_TOP;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

79
src/arch/arm/romstage.ld
View File

@ -1,79 +0,0 @@
/*
* Memory map:
*
* CONFIG_ROMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_start = .;
*(.text.stage_entry.arm);
*(.text.startup);
*(.text);
*(.text.*);
} : to_load
.romdata . : {
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
. = ALIGN(8);
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

8
src/arch/arm/stages.c
View File

@ -22,10 +22,10 @@
* execution (bootblock entry and ramstage exit will depend on external
* loading).
*
* Entry points must be placed at the location the previous stage jumps
* to (the lowest address in the stage image). This is done by giving
* stage_entry() its own section in .text and placing it first in the
* linker script.
* Entry points should be set in the linker script and honored by CBFS,
* so text section layout shouldn't matter. Still, it doesn't hurt to put
* stage_entry first (which XXXstage.ld will do automatically through the
* .text.stage_entry section created by -ffunction-sections).
*/
#include <arch/stages.h>

66
src/arch/arm/verstage.ld
View File

@ -1,66 +0,0 @@
/*
* Memory map:
*
* CONFIG_VERSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
PHDRS
{
to_load PT_LOAD;
}
ENTRY(stage_entry)
SECTIONS
{
. = CONFIG_VERSTAGE_BASE;
.romtext . : {
_start = .;
*(.text.stage_entry.arm);
*(.text.startup);
*(.text);
*(.text.*);
} : to_load
.romdata . : {
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
. = ALIGN(8);
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
*/
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

21
src/arch/arm64/Makefile.inc
View File

@ -68,13 +68,11 @@ bootblock-y += ../../lib/memset.c
bootblock-y += ../../lib/memcpy.c
bootblock-y += ../../lib/memmove.c
bootblock-y += bootblock.ld
# Build the bootblock
$(objcbfs)/bootblock.debug: $(obj)/arch/arm64/bootblock.bootblock.ld $$(bootblock-objs) $(obj)/config.h
$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(obj)/arch/arm64/bootblock.bootblock.ld
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld
endif # CONFIG_ARCH_BOOTBLOCK_ARM64
@ -96,8 +94,6 @@ romstage-y += ../../lib/memmove.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
romstage-y += transition.c transition_asm.S
romstage-y += romstage.ld
rmodules_arm64-y += ../../lib/memset.c
rmodules_arm64-y += ../../lib/memcpy.c
rmodules_arm64-y += ../../lib/memmove.c
@ -106,9 +102,9 @@ rmodules_arm64-y += eabi_compat.c
# Build the romstage
VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o
$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/arm64/romstage.romstage.ld
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(romstage-objs) --end-group -T $(obj)/arch/arm64/romstage.romstage.ld
$(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld
endif # CONFIG_ARCH_ROMSTAGE_ARM64
@ -144,18 +140,13 @@ secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcmp.c
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcpy.c
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-y += ramstage.ld
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
# Build the ramstage
$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/arm64/ramstage.ramstage.ld
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(ramstage-objs) --end-group -T $(obj)/arch/arm64/ramstage.ramstage.ld
$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group
$(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld
endif # CONFIG_ARCH_RAMSTAGE_ARM64

40
src/arch/arm64/bootblock.ld → src/arch/arm64/include/arch/header.ld
View File

@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -27,38 +26,7 @@ PHDRS
to_load PT_LOAD;
}
ENTRY(stage_entry)
#ifdef __BOOTBLOCK__
TARGET(binary)
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
.bootblock . : {
*(.text.stage_entry);
KEEP(*(.id));
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
*(.bss);
*(.bss.*);
*(.sbss);
*(.sbss.*);
} : to_load = 0xff
/* arm64 chipsets need to define CONFIG_BOOTBLOCK_STACK_(TOP|BOTTOM) */
_stack = CONFIG_BOOTBLOCK_STACK_BOTTOM;
_estack = CONFIG_BOOTBLOCK_STACK_TOP;
preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.ARM.*)
}
}
#endif
ENTRY(stage_entry)

35
src/arch/arm64/include/arch/memlayout.h Normal file
View File

@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
/* TODO: add SRAM TTB region and figure out the correct size/alignment for it */
/* ARM64 stacks need 16-byte alignment. The ramstage will set up its own stacks
* in BSS, so this is only used for the SRAM stages. */
#ifdef __PRE_RAM__
#define STACK(addr, size) REGION(stack, addr, size, 16)
#else
#define STACK(addr, size) REGION(preram_stack, addr, size, 16)
#endif
#endif /* __ARCH_MEMLAYOUT_H */

119
src/arch/arm64/ramstage.ld
View File

@ -1,119 +0,0 @@
/*
* Memory map:
*
* CONFIG_RAMBASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Copyright 2013 Google Inc.
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_RAMSTAGE_BASE;
.text : {
_text = .;
_start = .;
*(.text.stage_entry);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
. = ALIGN(64);
_rodata = .;
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(64);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
LONG(0);
LONG(0);
_bs_init_end = .;
. = ALIGN(64);
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
. = ALIGN(64);
_data = .;
*(.data)
*(.data.*)
. = ALIGN(64);
_edata = .;
}
.bss : {
. = ALIGN(64);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss.*)
*(COMMON)
. = ALIGN(64);
_ebss = .;
}
.heap : {
_heap = .;
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = . + CONFIG_HEAP_SIZE ;
. = ALIGN(64);
_eheap = .;
}
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

87
src/arch/arm64/romstage.ld
View File

@ -1,87 +0,0 @@
/*
* Memory map:
*
* CONFIG_ROMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
PHDRS
{
to_load PT_LOAD;
}
ENTRY(stage_entry)
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_start = .;
*(.text.stage_entry);
*(.text.startup);
*(.text);
*(.text.*);
} : to_load
.romdata . : {
*(.rodata);
*(.rodata.*);
*(.machine_param);
*(.data);
*(.data.*);
. = ALIGN(8);
_erom = .;
}
__image_copy_end = .;
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
/* arm64 chipsets need to define CONFIG_ROMSTAGE_STACK_(TOP|BOTTOM) */
_stack = CONFIG_ROMSTAGE_STACK_BOTTOM;
_estack = CONFIG_ROMSTAGE_STACK_TOP;
preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

19
src/arch/mips/Makefile.inc
View File

@ -43,17 +43,15 @@ bootblock-y += ../../lib/memcpy.c
bootblock-y += ../../lib/memmove.c
bootblock-y += ../../lib/memset.c
bootblock-y += bootblock.ld
# Much of the assembly code is generated by the compiler, and may contain
# terms which the preprocessor will happily go on to replace. For example
# "mips" would be replaced with "1". Clear all the built in definitions to
# prevent that.
bootblock-S-ccopts += -undef
$(objcbfs)/bootblock.debug: $(obj)/arch/mips/bootblock.bootblock.ld $$(bootblock-objs) $(obj)/config.h
$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/mips/bootblock.bootblock.ld --start-group $(bootblock-objs) --end-group
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
endif # CONFIG_ARCH_BOOTBLOCK_MIPS
@ -71,11 +69,9 @@ romstage-y += ../../lib/memcpy.c
romstage-y += ../../lib/memmove.c
romstage-y += ../../lib/memset.c
romstage-y += romstage.ld
$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/mips/romstage.romstage.ld
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/mips/romstage.romstage.ld --start-group $(romstage-objs) --end-group
$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
endif # CONFIG_ARCH_ROMSTAGE_MIPS
@ -93,12 +89,11 @@ ramstage-y += timer.c
ramstage-y += ../../lib/memcpy.c
ramstage-y += ../../lib/memmove.c
ramstage-y += ../../lib/memset.c
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
ramstage-y += ramstage.ld
$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/mips/ramstage.ramstage.ld
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/mips/ramstage.ramstage.ld --start-group $(ramstage-objs) --end-group
$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
endif # CONFIG_ARCH_RAMSTAGE_MIPS

6
src/arch/mips/bootblock.S
View File

@ -19,17 +19,17 @@
.set noreorder /* Prevent assembler from "optimizing" this code. */
.section ".start", "ax", %progbits
.section ".text._start", "ax", %progbits
.globl _start
_start:
/* Set the stack pointer */
li $sp, CONFIG_BOOTBLOCK_STACK_TOP
la $sp, _estack
/*
* Initialise the stack to a known value, used later to check for
* overflow.
*/
li $t0, CONFIG_BOOTBLOCK_STACK_BOTTOM
la $t0, _stack
addi $t1, $sp, -4
li $t2, 0xdeadbeef
1: sw $t2, 0($t0)

39
src/arch/mips/bootblock.ld → src/arch/mips/include/arch/header.ld
View File

@ -1,9 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright (C) 2014 Imagination Technologies
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -19,39 +17,16 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_ARCH(mips)
ENTRY(_start)
PHDRS
{
to_load PT_LOAD;
}
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
/* This section might be better named .setup */
.rom : {
_rom = .;
*(.start);
*(.id);
*(.text);
*(.text.*);
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
*(.rodata.*);
_erom = .;
} : to_load = 0xff
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
}
}
#ifdef __BOOTBLOCK__
ENTRY(_start)
#else
ENTRY(stage_entry)
#endif

31
src/arch/mips/include/arch/memlayout.h Normal file
View File

@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
/* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */
/* TODO: Double-check that that's the correct alignment for our ABI. */
#define STACK(addr, size) REGION(stack, addr, size, 8)
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */

121
src/arch/mips/ramstage.ld
View File

@ -1,121 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* Based on src/arch/arm/ramstage.ld:
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
OUTPUT_ARCH(mips)
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_SYS_SDRAM_BASE;
.text : {
_text = .;
_start = .;
*(.text.stage_entry.mips);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
*(.ctors);
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
_rodata = .;
. = ALIGN(4);
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(4);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
. = ALIGN(4);
_erodata = .;
}
.data : {
_data = .;
*(.data)
_edata = .;
}
/* bss will be cleared by cbfs_load_stage */
_bss = .;
.bss . : {
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_end = .;
/*
* coreboot from the perspective of the loader really "ends"
* here. Only symbols are placed after this.
*/
_heap = .;
_eheap = . + CONFIG_HEAP_SIZE;
_stack = CONFIG_STACK_BOTTOM;
_estack = CONFIG_STACK_TOP;
/*
* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

72
src/arch/mips/romstage.ld
View File

@ -1,72 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
OUTPUT_ARCH(mips)
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_rom = .;
_start = .;
*(.text.stage_entry.mips);
*(.text.startup);
*(.text);
} : to_load
.romdata . : {
*(.rodata);
*(.data);
. = ALIGN(16);
_erom = .;
}
/* bss will be cleared by cbfs_load_stage */
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_end = .;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

2
src/arch/mips/stages.c
View File

@ -20,7 +20,7 @@
#include <arch/stages.h>
#include <arch/cache.h>
__attribute__((section(".text.stage_entry.mips"))) void stage_entry(void)
void stage_entry(void)
{
main();
}

18
src/arch/riscv/Makefile.inc
View File

@ -38,12 +38,10 @@ bootblock-y += \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
bootblock-y += bootblock.ld
$(objcbfs)/bootblock.debug: $(obj)/arch/riscv/bootblock.bootblock.ld $$(bootblock-objs)
$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
-T $(obj)/arch/riscv/bootblock.bootblock.ld --start-group $(bootblock-objs) \
-T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) \
$(LIBGCC_FILE_NAME_bootblock) --end-group
endif
@ -65,13 +63,11 @@ romstage-y += \
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
romstage-y += romstage.ld
# Build the romstage
$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/riscv/romstage.romstage.ld
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/riscv/romstage.romstage.ld --start-group $(romstage-objs) --end-group
$(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
romstage-c-ccopts += $(riscv_flags)
romstage-S-ccopts += $(riscv_asm_flags)
@ -103,15 +99,13 @@ $(eval $(call create_class_compiler,rmodules,riscv))
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-y += ramstage.ld
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
# Build the ramstage
$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/riscv/ramstage.ramstage.ld
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/riscv/ramstage.ramstage.ld --start-group $(ramstage-objs) --end-group
$(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
ramstage-c-ccopts += $(riscv_flags)
ramstage-S-ccopts += $(riscv_asm_flags)

2
src/arch/riscv/bootblock.S
View File

@ -21,7 +21,7 @@
// See LICENSE for license details. relating to the _start code in this file.
#include <arch/encoding.h>
.section ".start", "ax", %progbits
.section ".text._start", "ax", %progbits
// Maybe there's a better way.
.space 0x2000
.globl _start

33
src/arch/riscv/bootblock.ld → src/arch/riscv/include/arch/header.ld
View File

@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -19,7 +18,6 @@
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
OUTPUT_ARCH(riscv)
PHDRS
@ -27,30 +25,9 @@ PHDRS
to_load PT_LOAD;
}
#ifdef __BOOTBLOCK__
ENTRY(_start)
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
#else
ENTRY(stage_entry)
#endif
.bootblock . : {
*(.start);
KEEP(*(.id));
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
*(.bss);
*(.bss.*);
*(.sbss);
*(.sbss.*);
} : to_load = 0xff
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
}
}

31
src/arch/riscv/include/arch/memlayout.h Normal file
View File

@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
/* TODO: Double-check that that's the correct alignment for our ABI. */
#define STACK(addr, size) REGION(stack, addr, size, 8)
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */

2
src/arch/riscv/include/arch/stages.h
View File

@ -22,7 +22,7 @@
extern void main(void);
void stage_entry(void) __attribute__((section(".text.stage_entry.riscv")));
void stage_entry(void) __attribute__((section(".text.stage_entry")));
void stage_exit(void *);
void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size);

134
src/arch/riscv/ramstage.ld
View File

@ -1,134 +0,0 @@
/*
* Memory map:
*
* CONFIG_RAMBASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Copyright 2013 Google Inc.
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = 0x100000; /*CONFIG_SYS_SDRAM_BASE;*/
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_text = .;
_start = .;
*(.text.stage_entry.riscv);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
*(.ctors);
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
_rodata = .;
. = ALIGN(4);
console_drivers = .;
*(.rodata.console_drivers)
econsole_drivers = . ;
. = ALIGN(4);
pci_drivers = . ;
*(.rodata.pci_driver)
epci_drivers = . ;
cpu_drivers = . ;
*(.rodata.cpu_driver)
ecpu_drivers = . ;
_bs_init_begin = .;
*(.bs_init)
LONG(0);
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
/* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
*/
. = ALIGN(4);
_erodata = .;
}
/* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
* whereas __data_loadstart and __data_loadend shows where in rom to
* copy from.
*/
.data : {
_data = .;
*(.data)
_edata = .;
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
_bss = .;
.bss . : {
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_end = .;
/* coreboot really "ends" here. Only heap and stack are placed after
* this line.
*/
_heap = .;
.heap . : {
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = CONFIG_HEAP_SIZE ;
. = ALIGN(4);
}
_eheap = .;
_stack = CONFIG_STACK_BOTTOM;
_estack = CONFIG_STACK_TOP;
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

83
src/arch/riscv/romstage.ld
View File

@ -1,83 +0,0 @@
/*
* Memory map:
*
* CONFIG_ROMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
OUTPUT_ARCH(riscv)
PHDRS
{
to_load PT_LOAD;
}
ENTRY(stage_entry)
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_start = .;
*(.text.stage_entry.riscv);
*(.text.startup);
*(.text);
*(.text.*);
} : to_load
.romdata . : {
*(.rodata);
*(.rodata.*);
*(.machine_param);
*(.data);
*(.data.*);
. = ALIGN(8);
_erom = .;
}
__image_copy_end = .;
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

2
src/arch/x86/Makefile.inc
View File

@ -303,7 +303,7 @@ ramstage-srcs += $(src)/arch/x86/ramstage.ld
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
$(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld
endif

6
src/arch/x86/boot/boot.c
View File

@ -3,6 +3,7 @@
#include <program_loading.h>
#include <ip_checksum.h>
#include <string.h>
#include <symbols.h>
/* When the ramstage is relocatable the elf loading ensures an elf image cannot
* be loaded over the ramstage code. */
@ -25,11 +26,10 @@ static void jmp_payload_no_bounce_buffer(void *entry)
static void jmp_payload(void *entry, unsigned long buffer, unsigned long size)
{
extern unsigned char _ram_seg, _eram_seg;
unsigned long lb_start, lb_size;
lb_start = (unsigned long)&_ram_seg;
lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
lb_start = (unsigned long)&_program;
lb_size = _program_size;
printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry);
printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start);

8
src/arch/x86/init/romstage.ld
View File

@ -60,12 +60,12 @@ SECTIONS
*(.car.global_data);
_car_data_end = .;
/* The preram cbmem console area comes last to take advantage
* of a zero-sized array to hold the memconsole contents that
* grows to a bound of CONFIG_CONSOLE_PRERAM_BUFFER_SIZE.
* of a zero-sized array to hold the memconsole contents.
* However, collisions within the cache-as-ram region cannot be
* statically checked because the cache-as-ram region usage is
* cpu/chipset dependent. */
preram_cbmem_console = .;
_preram_cbmem_console = .;
_epreram_cbmem_console = . + 0xc00;
}
/* Global variables are not allowed in romstage
@ -83,5 +83,5 @@ SECTIONS
*(.sbss.*)
}
_bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
}

2
src/arch/x86/lib/c_start.S
View File

@ -16,7 +16,7 @@ thread_stacks:
.space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS
#endif
.section ".textfirst", "ax", @progbits
.section ".text._start", "ax", @progbits
.code32
.globl _start
.globl __rmodule_entry

117
src/arch/x86/ramstage.ld
View File

@ -8,121 +8,18 @@
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
ENTRY(_start)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_RAMBASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_text = .;
*(.textfirst);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
}
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
__CTOR_END__ = .;
}
INCLUDE "lib/ramstage.ramstage.ld"
.rodata : {
_rodata = .;
. = ALIGN(4);
/* If any changes are made to the driver start/symbols or the
* section names the equivalent changes need to made to
* rmodule.ld. */
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
LONG(0);
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
/* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
*/
. = ALIGN(4);
_erodata = .;
}
/* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
* whereas __data_loadstart and __data_loadend shows where in rom to
* copy from.
*/
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
_bss = .;
.bss . : {
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(COMMON)
}
_ebss = .;
_heap = .;
.heap . : {
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = CONFIG_HEAP_SIZE ;
. = ALIGN(4);
}
_eheap = .;
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* CONFIG_RAMTOP is the upper address of cached memory (among other
* things). We must not exceed beyond that address, there be dragons.
*/
_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
}

10
src/console/Kconfig
View File

@ -189,16 +189,6 @@ config CONSOLE_PRERAM_BUFFER_BASE
default 0xabadbeef if !CACHE_AS_RAM || LATE_CBMEM_INIT
default 0x0
config CONSOLE_PRERAM_BUFFER_SIZE
hex
default 0x0 if CONSOLE_PRERAM_BUFFER_BASE = 0xabadbeef
default 0xc00
help
Console is used before RAM is initialized. This is the room reserved
in the DCACHE based RAM, SRAM, etc. to keep console output before it
can be saved in a CBMEM buffer. 3K bytes should be enough even for
the BIOS_SPEW level.
endif
config CONSOLE_QEMU_DEBUGCON

36
src/cpu/allwinner/a10/Kconfig
View File

@ -15,11 +15,6 @@ config CPU_SPECIFIC_OPTIONS
select BOOTBLOCK_CONSOLE
select CPU_HAS_BOOTBLOCK_INIT
# The "eGON.BT0" header takes 32 bytes
config BOOTBLOCK_BASE
hex
default 0x20
config BOOTBLOCK_ROM_OFFSET
hex
default 0x00
@ -36,41 +31,10 @@ config CBFS_HEADER_ROM_OFFSET
config CBFS_ROM_OFFSET
default 0x5fc0
# Arbitrarily chosen to be at the base of SDRAM
config RAMSTAGE_BASE
hex
default SYS_SDRAM_BASE
# 16 MiB above ramstage, so there is no overlap
config ROMSTAGE_BASE
hex
default 0x41000000
# Keep the stack in SRAM block A2.
# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up
# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32KiB
# to use however we see fit.
config STACK_TOP
hex
default 0x00008000
config STACK_BOTTOM
hex
default 0x00006000
config STACK_SIZE
hex
default 0x00002000
## TODO Change this to some better address not overlapping bootblock when
## cbfstool supports creating header in arbitrary location.
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x40
config SYS_SDRAM_BASE
hex
default 0x40000000
endif # if CPU_ALLWINNER_A10

3
src/cpu/allwinner/a10/cpu.c
View File

@ -9,11 +9,12 @@
#include <device/device.h>
#include <cpu/cpu.h>
#include <cbmem.h>
#include <symbols.h>
static void cpu_enable_resources(struct device *dev)
{
ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10,
ram_resource(dev, 0, (uintptr_t)_dram/KiB,
CONFIG_DRAM_SIZE_MB << 10);
/* TODO: Declare CBFS cache as reserved? There's no guarantee we won't
* overwrite it. It seems to stay intact, being so high in RAM

3
src/cpu/allwinner/a10/ram_segs.h
View File

@ -6,13 +6,14 @@
*/
#include <config.h>
#include <symbols.h>
/*
* Put CBMEM at top of RAM
*/
static inline void *a1x_get_cbmem_top(void)
{
return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20);
return _dram + (CONFIG_DRAM_SIZE_MB << 20);
}
/*

32
src/cpu/ti/am335x/Kconfig
View File

@ -12,46 +12,14 @@ config CPU_TI_AM335X
if CPU_TI_AM335X
config BOOTBLOCK_BASE
hex
default 0x402f0400
config CBFS_ROM_OFFSET
# Calculated by BL1 + max bootblock size.
default 0x4c00
# We need to leave a gap between the bootblock and the ROM stage so that when
# it is "loaded" to a slightly different place in on chip memory, it doesn't
# clobber the metadata needed to actually enter it.
config ROMSTAGE_BASE
hex
default 0x402f5400
# Stack may reside in either IRAM or DRAM. We will define it to live
# at the top of IRAM for now.
#
# Stack grows downward, push operation stores register contents in
# consecutive memory locations ending just below SP
config STACK_TOP
hex
default 0x4030ce00
config STACK_BOTTOM
hex
default 0x4030be00
config STACK_SIZE
hex
default 0x1000
## TODO Change this to some better address not overlapping bootblock when
## cbfstool supports creating header in arbitrary location.
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x40
config SYS_SDRAM_BASE
hex
default 0x40000000
endif

10
src/cpu/ti/am335x/Makefile.inc
View File

@ -23,14 +23,14 @@ $(eval $(call create_class_compiler,omap-header,arm))
real-target: $(obj)/MLO
header_ld = $(src)/cpu/ti/am335x/header.ld
header_ld = $(obj)/cpu/ti/am335x/header.omap-header.ld
get_header_size= \
$(eval omap_header_info=$(shell $(CBFSTOOL) $(1) print | grep $(2))) \
$(shell echo $$(($(word 2,$(omap_header_info)) + \
$(word 4,$(omap_header_info)))))
$(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) $(obj)/coreboot.rom
$(obj)/omap-header.bin: $$(omap-header-objs) $(obj)/coreboot.rom
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC_omap-header) -nostdlib -nostartfiles -static -include $(obj)/config.h \
-Wl,--defsym,header_load_size=$(strip \
@ -46,3 +46,9 @@ $(obj)/MLO: $(obj)/coreboot.rom $(obj)/omap-header.bin
$(Q)cat $(obj)/omap-header.bin $(obj)/coreboot.rom > $@
omap-header-y += header.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld
omap-header-y += memlayout.ld
omap-header-y += header.ld

6
src/cpu/ti/am335x/bootblock_media.c
View File

@ -20,6 +20,7 @@
#include <cbfs.h>
#include <console/console.h>
#include <string.h>
#include <symbols.h>
static int dummy_open(struct cbfs_media *media)
{
@ -34,7 +35,7 @@ static int dummy_close(struct cbfs_media *media)
static void * on_chip_memory_map(struct cbfs_media *media, size_t offset,
size_t count)
{
return (void *)((uintptr_t)CONFIG_BOOTBLOCK_BASE + offset);
return _dram + offset;
}
static void * dummy_unmap(struct cbfs_media *media, const void *address)
@ -54,8 +55,7 @@ static size_t on_chip_memory_read(struct cbfs_media *media, void *dest,
int init_default_cbfs_media(struct cbfs_media *media)
{
struct cbfs_header *header =
(struct cbfs_header *)((uintptr_t)CONFIG_BOOTBLOCK_BASE +
CONFIG_CBFS_HEADER_ROM_OFFSET);
(struct cbfs_header *)(_dram + CONFIG_CBFS_HEADER_ROM_OFFSET);
if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);

3
src/cpu/ti/am335x/cbmem.c
View File

@ -17,8 +17,9 @@
#include <stddef.h>
#include <cbmem.h>
#include <symbols.h>
void *cbmem_top(void)
{
return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20);
return _dram + (CONFIG_DRAM_SIZE_MB << 20);
}

3
src/cpu/ti/am335x/header.c
View File

@ -20,6 +20,7 @@
#include <config.h>
#include <stddef.h>
#include <stdint.h>
#include <symbols.h>
#include "header.h"
@ -70,6 +71,6 @@ struct omap_image_headers headers __attribute__((section(".header"))) = {
},
.image_header = {
.size = (uintptr_t)&header_load_size,
.destination = CONFIG_BOOTBLOCK_BASE
.destination = (uintptr_t)_dram
}
};

13
src/cpu/ti/am335x/header.ld
View File

@ -21,14 +21,5 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
TARGET(binary)
SECTIONS
{
.header : {
*(.header);
}
/DISCARD/ : {
*(*)
}
}
#define OMAP_HEADER 1
#include "memlayout.ld"

42
src/cpu/ti/am335x/memlayout.ld Normal file
View File

@ -0,0 +1,42 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
DRAM_START(0x40000000)
BOOTBLOCK(0x402f0400, 20K)
ROMSTAGE(0x402f5400, 90K)
STACK(0x4030be00, 4K)
RAMSTAGE(0x80200000, 192K)
#ifdef OMAP_HEADER
.header : {
*(.header);
} : to_load
/DISCARD/ : {
*(*)
}
#endif
}

1
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -27,6 +27,7 @@
#include <halt.h>
#include <lib.h>
#include <string.h>
#include <symbols.h>
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>

1
src/cpu/x86/mp_init.c
View File

@ -39,6 +39,7 @@
#include <lib.h>
#include <smp/atomic.h>
#include <smp/spinlock.h>
#include <symbols.h>
#include <thread.h>
#define MAX_APIC_IDS 256

4
src/cpu/x86/smm/smm.ld
View File

@ -11,6 +11,7 @@ SECTIONS
*/
. = 0xa0000;
.handler (.): {
_program = .;
/* Assembler stub */
*(.handler)
@ -35,9 +36,10 @@ SECTIONS
*(.sbss)
*(.sbss.*)
/* What is this? */
/* What is this? (Something we don't need with -fno-common.) */
*(COMMON)
. = ALIGN(4);
_eprogram = .;
}
/* We are using the ASEG interleaved to stuff the SMM handlers

2
src/cpu/x86/smm/smm_tseg.ld
View File

@ -31,6 +31,7 @@ SECTIONS
/* 16KB for the heap at 64KB */
. = 0x10000;
.heap : {
_program = .;
_heap = .;
. = 0x4000;
_eheap = .;
@ -65,6 +66,7 @@ SECTIONS
. = ALIGN(4);
_smm_c_handler_end = .;
_eprogram = .;
}
/DISCARD/ : {

5
src/include/lib.h
View File

@ -45,11 +45,6 @@ int primitive_memtest(uintptr_t base, uintptr_t size);
/* Defined in src/lib/stack.c */
int checkstack(void *top_of_stack, int core);
#ifndef __PRE_RAM__ // fails in bootblock compiled with romcc
/* currently defined by a ldscript */
extern unsigned char _estack[];
#endif
/* Defined in src/lib/hexdump.c */
void hexdump(const void *memory, size_t length);
void hexdump32(char LEVEL, const void *d, size_t len);

105
src/include/memlayout.h Normal file
View File

@ -0,0 +1,105 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __MEMLAYOUT_H
#define __MEMLAYOUT_H
#include <arch/memlayout.h>
#define STR(x) #x
#define SET_COUNTER(name, addr) \
_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
. = addr;
#define SYMBOL(name, addr) \
SET_COUNTER(name, addr) \
_##name = .;
#define REGION(name, addr, size, expected_align) \
SYMBOL(name, addr) \
_ = ASSERT(. == ALIGN(expected_align), \
STR(name must be aligned to expected_align!)); \
SYMBOL(e##name, addr + size)
/* Declare according to SRAM/DRAM ranges in SoC hardware-defined address map. */
#define SRAM_START(addr) SYMBOL(sram, addr)
#define SRAM_END(addr) SYMBOL(esram, addr)
#define DRAM_START(addr) SYMBOL(dram, addr)
#define PRERAM_CBMEM_CONSOLE(addr, size) \
REGION(preram_cbmem_console, addr, size, 4)
/* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */
#define CBFS_CACHE(addr, size) REGION(cbfs_cache, addr, size, 4)
/* TODO: This only works if you never access CBFS in romstage before RAM is up!
* If you need to change that assumption, you have some work ahead of you... */
#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
#define POSTRAM_CBFS_CACHE(addr, size) \
REGION(unused_cbfs_cache, addr, size, 4)
#else
#define PRERAM_CBFS_CACHE(addr, size) \
REGION(unused_cbfs_cache, addr, size, 4)
#define POSTRAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
#endif
/* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
#ifdef __BOOTBLOCK__
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
_ = ASSERT(_ebootblock - _bootblock <= sz, \
STR(Bootblock exceeded its allotted size! (sz))); \
INCLUDE "lib/bootblock.bootblock.ld"
#else
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
. += sz;
#endif
#ifdef __ROMSTAGE__
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
_ = ASSERT(_eromstage - _romstage <= sz, \
STR(Romstage exceeded its allotted size! (sz))); \
INCLUDE "lib/romstage.romstage.ld"
#else
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
. += sz;
#endif
#ifdef __RAMSTAGE__
#define RAMSTAGE(addr, sz) \
SET_COUNTER(ramstage, addr) \
_ = ASSERT(_eramstage - _ramstage <= sz, \
STR(Ramstage exceeded its allotted size! (sz))); \
INCLUDE "lib/ramstage.ramstage.ld"
#else
#define RAMSTAGE(addr, sz) \
SET_COUNTER(ramstage, addr) \
. += sz;
#endif
#endif /* __MEMLAYOUT_H */

76
src/include/symbols.h Normal file
View File

@ -0,0 +1,76 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
#ifndef __SYMBOLS_H
#define __SYMBOLS_H
#include <types.h>
extern u8 _sram[];
extern u8 _esram[];
#define _sram_size (_esram - _sram)
extern u8 _dram[];
extern u8 _preram_cbmem_console[];
extern u8 _epreram_cbmem_console[];
#define _preram_cbmem_console_size \
(_epreram_cbmem_console - _preram_cbmem_console)
extern u8 _stack[];
extern u8 _estack[];
#define _stack_size (_estack - _stack)
extern u8 _cbfs_cache[];
extern u8 _ecbfs_cache[];
#define _cbfs_cache_size (_ecbfs_cache - _cbfs_cache)
extern u8 _payload[];
extern u8 _epayload[];
#define _payload_size (_epayload - _payload)
/* Careful: _e<stage> and _<stage>_size only defined for the current stage! */
extern u8 _bootblock[];
extern u8 _ebootblock[];
#define _bootblock_size (_ebootblock - _bootblock)
extern u8 _romstage[];
extern u8 _eromstage[];
#define _romstage_size (_eromstage - _romstage)
extern u8 _ramstage[];
extern u8 _eramstage[];
#define _ramstage_size (_eramstage - _ramstage)
/* "program" always refers to the current execution unit, except for x86 ROM. */
extern u8 _program[];
extern u8 _eprogram[];
#define _program_size (_eprogram - _program)
/* Arch-specific, move to <arch/symbols.h> if they become too many. */
extern u8 _ttb[];
extern u8 _ettb[];
#define _ttb_size (_ettb - _ttb)
extern u8 _dma_coherent[];
extern u8 _edma_coherent[];
#define _dma_coherent_size (_edma_coherent - _dma_coherent)
#endif /* __SYMBOLS_H */

17
src/lib/Makefile.inc
View File

@ -39,7 +39,8 @@ romstage-y += prog_ops.c
romstage-y += memchr.c
romstage-y += memcmp.c
$(foreach arch,$(ARCH_SUPPORTED),\
$(eval rmodules_$(arch)-y += memcmp.c))
$(eval rmodules_$(arch)-y += memcmp.c) \
$(eval rmodules_$(arch)-y += rmodule.ld))
romstage-$(CONFIG_I2C_TPM) += delay.c
romstage-y += cbfs.c cbfs_core.c
@ -122,12 +123,20 @@ ramstage-y += halt.c
smm-y += halt.c
secmon-y += halt.c
ifneq ($(CONFIG_ARCH_X86),y)
# X86 bootblock and romstage use custom ldscripts that are all glued together,
# so we need to exclude it here or it would pick these up as well
bootblock-y += bootblock.ld
romstage-y += romstage.ld
endif
ramstage-y += ramstage.ld
ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
ramstage-y += rmodule.c
romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c
RMODULE_LDSCRIPT := $(src)/lib/rmodule.ld
RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic -T$(RMODULE_LDSCRIPT)
RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic -T $(RMODULE_LDSCRIPT)
# rmodule_link_rules is a function that should be called with:
# (1) the object name to link
@ -137,8 +146,8 @@ RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic
# It will create the necessary Make rules to create a rmodule. The resulting
# rmdoule is named $(1).rmod
define rmodule_link
$(strip $(1)): $(strip $(2)) $$(RMODULE_LDSCRIPT) $$(RMODTOOL)
$$(LD_rmodules_$(4)) $$(RMODULE_LDFLAGS) --defsym=__heap_size=$(strip $(3)) -o $$@ --start-group $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) --end-group
$(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL)
$$(LD_rmodules_$(4)) --gc-sections -static -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --start-group $(filter-out %.ld,$(2)) --end-group
$$(NM_rmodules_$(4)) -n $$@ > $$(basename $$@).map
$(strip $(1)).rmod: $(strip $(1))

49
src/lib/bootblock.ld Normal file
View File

@ -0,0 +1,49 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file is included inside a SECTIONS block */
.bootblock . : {
_program = .;
_bootblock = .;
*(.text._start);
*(.text.stage_entry);
KEEP(*(.id));
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
*(.bss);
*(.bss.*);
*(.sbss);
*(.sbss.*);
_ebootblock = .;
_eprogram = .;
} : to_load = 0xff
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.ARM.*)
*(.MIPS.*)
}

5
src/lib/cbfs_spi.c
View File

@ -25,6 +25,7 @@
#include <cbfs.h>
#include <spi_flash.h>
#include <symbols.h>
/* SPI flash as CBFS media. */
struct cbfs_spi_context {
@ -80,8 +81,8 @@ static int init_cbfs_media_context(void)
if (!spi_context.spi_flash_info)
return -1;
spi_context.buffer.buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
spi_context.buffer.size = CONFIG_CBFS_CACHE_SIZE;
spi_context.buffer.buffer = (void *)_cbfs_cache;
spi_context.buffer.size = _cbfs_cache_size;
}
return 0;

9
src/lib/cbmem_console.c
View File

@ -21,6 +21,7 @@
#include <console/cbmem_console.h>
#include <cbmem.h>
#include <arch/early_variables.h>
#include <symbols.h>
#include <string.h>
/*
@ -44,11 +45,9 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p,
/*
* While running from ROM, before DRAM is initialized, some area in cache as
* ram space is used for the console buffer storage. The size and location of
* the area are defined in the config.
* the area are defined by the linker script with _(e)preram_cbmem_console.
*/
extern struct cbmem_console preram_cbmem_console;
#else
/*
@ -112,8 +111,8 @@ void cbmemc_init(void)
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
flags = 0;
init_console_ptr(&preram_cbmem_console,
CONFIG_CONSOLE_PRERAM_BUFFER_SIZE, flags);
init_console_ptr(_preram_cbmem_console,
_preram_cbmem_console_size, flags);
#else
/*
* Initializing before CBMEM is available, use static buffer to store

1
src/lib/loaders/load_and_run_payload.c
View File

@ -24,6 +24,7 @@
#include <fallback.h>
#include <lib.h>
#include <program_loading.h>
#include <symbols.h>
#include <timestamp.h>
extern const struct prog_loader_ops vboot_payload_loader;

116
src/lib/ramstage.ld Normal file
View File

@ -0,0 +1,116 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file is included inside a SECTIONS block */
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_program = .;
_ramstage = .;
_text = .;
*(.text._start);
*(.text.stage_entry);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
#ifdef CONFIG_COVERAGE
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
LONG(0);
__CTOR_END__ = .;
}
#endif
/* TODO: align data sections to cache lines? (is that really useful?) */
.rodata : {
_rodata = .;
. = ALIGN(8);
/* If any changes are made to the driver start/symbols or the
* section names the equivalent changes need to made to
* rmodule.ld. */
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(8);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
LONG(0);
LONG(0);
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
/* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
*/
. = ALIGN(8);
_erodata = .;
}
.data : {
/* Move to different cache line to avoid false sharing with .rodata. */
. = ALIGN(64); /* May not be actual line size, not that important. */
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
.bss . : {
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
.heap . : {
_heap = .;
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. += CONFIG_HEAP_SIZE ;
. = ALIGN(4);
_eheap = .;
_eramstage = .;
_eprogram = .;
}
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}

10
src/lib/rmodule.ld
View File

@ -22,18 +22,21 @@ SECTIONS
.payload : {
/* C code of the module. */
_ram_seg = .;
*(.textfirst);
_program = .;
*(.text._start);
*(.text.stage_entry);
*(.text);
*(.text.*);
/* C read-only data. */
. = ALIGN(16);
#ifdef CONFIG_COVERAGE
__CTOR_LIST__ = .;
*(.ctors);
LONG(0);
LONG(0);
__CTOR_END__ = .;
#endif
/* The driver sections are to allow linking coreboot's
* ramstage with the rmodule linker. Any changes made in
@ -68,6 +71,7 @@ SECTIONS
. = ALIGN(8);
/* Data section. */
. = ALIGN(64); /* Mirror cache line alignment from ramstage. */
_sdata = .;
*(.data);
*(.data.*);
@ -95,7 +99,7 @@ SECTIONS
_heap = .;
. = . + __heap_size;
_eheap = .;
_eram_seg = .;
_eprogram = .;
}
/DISCARD/ : {

58
src/lib/romstage.ld Normal file
View File

@ -0,0 +1,58 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file is included inside a SECTIONS block */
.text . : {
_program = .;
_romstage = .;
*(.text._start);
*(.text.stage_entry);
*(.text);
*(.text.*);
} : to_load
.data . : {
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
. = ALIGN(8);
}
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
_eromstage = .;
_eprogram = .;
}
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}

9
src/lib/selfboot.c
View File

@ -24,17 +24,14 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <symbols.h>
#include <cbfs.h>
#include <lib.h>
#include <bootmem.h>
#include <program_loading.h>
/* from ramstage.ld: */
extern unsigned char _ram_seg;
extern unsigned char _eram_seg;
static const unsigned long lb_start = (unsigned long)&_ram_seg;
static const unsigned long lb_end = (unsigned long)&_eram_seg;
static const unsigned long lb_start = (unsigned long)&_program;
static const unsigned long lb_end = (unsigned long)&_eprogram;
struct segment {
struct segment *next;

4
src/mainboard/cubietech/cubieboard/Makefile.inc
View File

@ -1,2 +1,6 @@
bootblock-y += bootblock.c
romstage-y += romstage.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

36
src/mainboard/cubietech/cubieboard/memlayout.ld Normal file
View File

@ -0,0 +1,36 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
SRAM_START(0x0)
/* eGON.BT0: 32 bytes */
BOOTBLOCK(0x20, 0x5fa0)
STACK(0x6000, 8K)
SRAM_END(0x8000)
DRAM_START(0x40000000)
RAMSTAGE(0x40000000, 16M)
ROMSTAGE(0x41000000, 108K)
}

35
src/mainboard/emulation/qemu-armv7/Kconfig
View File

@ -49,45 +49,10 @@ config MAINBOARD_VENDOR
string
default "ARM Ltd."
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x01000000
config DRAM_SIZE_MB
int
default 1024
# Memory map for qemu vexpress-a9:
#
# 0x0000_0000: jump instruction (by qemu)
# 0x0001_0000: bootblock (entry of kernel / firmware)
# 0x0002_0000: romstage, assume up to 128KB in size.
# 0x0007_ff00: stack pointer
# 0x0010_0000: CBFS header
# 0x0011_0000: CBFS data
# 0x0100_0000: reserved for ramstage
# 0x1000_0000: I/O map address
#
config STACK_TOP
hex
default 0x00100000
config STACK_BOTTOM
hex
default 0x0007FF00
config BOOTBLOCK_BASE
hex
default 0x00010000
config ROMSTAGE_BASE
hex
default 0x00020000
config RAMSTAGE_BASE
hex
default SYS_SDRAM_BASE
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0

4
src/mainboard/emulation/qemu-armv7/Makefile.inc
View File

@ -28,3 +28,7 @@ ramstage-y += timer.c
bootblock-y += mmio.c
romstage-y += mmio.c
ramstage-y += mmio.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

3
src/mainboard/emulation/qemu-armv7/cbmem.c
View File

@ -17,8 +17,9 @@
#include <stddef.h>
#include <cbmem.h>
#include <symbols.h>
void *cbmem_top(void)
{
return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20);
return _dram + (CONFIG_DRAM_SIZE_MB << 20);
}

3
src/mainboard/emulation/qemu-armv7/media.c
View File

@ -14,6 +14,7 @@
*/
#include <cbfs.h>
#include <string.h>
#include <symbols.h>
#include <console/console.h>
/* Simple memory-mapped ROM emulation. */
@ -25,7 +26,7 @@ static int emu_rom_open(struct cbfs_media *media)
static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count)
{
return (void*)(offset + CONFIG_BOOTBLOCK_BASE);
return (void*)offset;
}
static void *emu_rom_unmap(struct cbfs_media *media, const void *address)

47
src/mainboard/emulation/qemu-armv7/memlayout.ld Normal file
View File

@ -0,0 +1,47 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
/*
* Memory map for qemu vexpress-a9:
*
* 0x0000_0000: jump instruction (by qemu)
* 0x0001_0000: bootblock (entry of kernel / firmware)
* 0x0002_0000: romstage, assume up to 128KB in size.
* 0x0007_ff00: stack pointer
* 0x0010_0000: CBFS header
* 0x0011_0000: CBFS data
* 0x0100_0000: reserved for ramstage
* 0x1000_0000: I/O map address
*/
SECTIONS
{
/* TODO: does this thing emulate SRAM? */
BOOTBLOCK(0x10000, 64K)
ROMSTAGE(0x20000, 128K)
STACK(0x000FC000, 16K)
DRAM_START(0x01000000)
RAMSTAGE(0x01000000, 16M)
}

24
src/mainboard/emulation/qemu-riscv/Kconfig
View File

@ -54,18 +54,6 @@ config DRAM_SIZE_MB
# 0x0011_0000: CBFS data
# 0x0100_0000: reserved for ramstage
config BOOTBLOCK_BASE
hex
default 0x00000000
config ROMSTAGE_BASE
hex
default 0x00020000
config RAMSTAGE_BASE
hex
default 0x100000
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
@ -82,16 +70,4 @@ config RAMTOP
hex
default 0x1000000
config STACK_TOP
hex
default 0x0007ff00
config STACK_BOTTOM
hex
default 0x00040000
config STACK_SIZE
hex
default 0x0003ff00
endif # BOARD_EMULATION_QEMU_UCB_RISCV

4
src/mainboard/emulation/qemu-riscv/Makefile.inc
View File

@ -17,3 +17,7 @@ bootblock-y += uart.c
romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += uart.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

33
src/mainboard/emulation/qemu-riscv/memlayout.ld Normal file
View File

@ -0,0 +1,33 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
DRAM_START(0x0)
BOOTBLOCK(0x0, 64K)
ROMSTAGE(0x20000, 128K)
STACK(0x40000, 0x3ff00)
PRERAM_CBMEM_CONSOLE(0x80000, 8K)
RAMSTAGE(0x100000, 16M)
}

4
src/mainboard/google/daisy/Makefile.inc
View File

@ -26,3 +26,7 @@ romstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

14
src/mainboard/google/daisy/mainboard.c
View File

@ -36,20 +36,17 @@
#include <soc/samsung/exynos5250/dp.h>
#include <soc/samsung/exynos5250/periph.h>
#include <soc/samsung/exynos5250/usb.h>
#include <symbols.h>
#include "exynos5250.h"
#define MMC0_GPIO_PIN (58)
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_START ((uintptr_t)_dram/MiB)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
/* Arbitrary range of DMA memory for depthcharge's drivers */
#define DMA_START (0x77300000)
#define DMA_SIZE (0x00100000)
static struct edid edid = {
.ha = 1366,
.va = 768,
@ -333,7 +330,8 @@ static void mainboard_enable(device_t dev)
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_mmu_enable();
@ -359,6 +357,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (intptr_t)DMA_START;
dma->range_size = DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/daisy/memlayout.ld Normal file
View File

@ -0,0 +1 @@
#include <soc/samsung/exynos5250/memlayout.ld>

8
src/mainboard/google/nyan/Kconfig
View File

@ -42,14 +42,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan"
config DRAM_DMA_START
hex
default 0x90000000
config DRAM_DMA_SIZE
hex
default 0x00200000
choice
prompt "BCT boot media"
default NYAN_BCT_CFG_SPI

4
src/mainboard/google/nyan/Makefile.inc
View File

@ -42,3 +42,7 @@ ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/nyan/mainboard.c
View File

@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@ -268,6 +269,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/nyan/memlayout.ld Normal file
View File

@ -0,0 +1 @@
#include <soc/nvidia/tegra124/memlayout.ld>

24
src/mainboard/google/nyan/romstage.c
View File

@ -39,6 +39,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@ -52,24 +53,25 @@ static void __attribute__((noinline)) romstage(void)
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
u32 dram_size = dram_end - dram_start;
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();

8
src/mainboard/google/nyan_big/Kconfig
View File

@ -44,14 +44,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan Big"
config DRAM_DMA_START
hex
default 0x90000000
config DRAM_DMA_SIZE
hex
default 0x00200000
choice
prompt "BCT boot media"
default NYAN_BIG_BCT_CFG_SPI

4
src/mainboard/google/nyan_big/Makefile.inc
View File

@ -41,3 +41,7 @@ ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/nyan_big/mainboard.c
View File

@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@ -266,6 +267,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/nyan_big/memlayout.ld Normal file
View File

@ -0,0 +1 @@
#include <soc/nvidia/tegra124/memlayout.ld>

24
src/mainboard/google/nyan_big/romstage.c
View File

@ -39,6 +39,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@ -52,24 +53,25 @@ static void __attribute__((noinline)) romstage(void)
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
u32 dram_size = dram_end - dram_start;
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();

8
src/mainboard/google/nyan_blaze/Kconfig
View File

@ -45,14 +45,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan Blaze"
config DRAM_DMA_START
hex
default 0x90000000
config DRAM_DMA_SIZE
hex
default 0x00200000
choice
prompt "BCT boot media"
default NYAN_BLAZE_BCT_CFG_SPI

5
src/mainboard/google/nyan_blaze/Makefile.inc
View File

@ -45,3 +45,8 @@ ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += memlayout.ld
verstage-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/nyan_blaze/mainboard.c
View File

@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@ -266,6 +267,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/nyan_blaze/memlayout.ld Normal file
View File

@ -0,0 +1 @@
#include <soc/nvidia/tegra124/memlayout.ld>

24
src/mainboard/google/nyan_blaze/romstage.c
View File

@ -39,6 +39,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@ -52,29 +53,30 @@ static void __attribute__((noinline)) romstage(void)
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
u32 dram_size = dram_end - dram_start;
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
#if !CONFIG_VBOOT2_VERIFY_FIRMWARE
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
#endif
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/*
* A watchdog reset only resets part of the system so it ends up in

4
src/mainboard/google/peach_pit/Makefile.inc
View File

@ -26,3 +26,7 @@ romstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

14
src/mainboard/google/peach_pit/mainboard.c
View File

@ -40,15 +40,12 @@
#include <drivers/parade/ps8625/ps8625.h>
#include <ec/google/chromeec/ec.h>
#include <stdlib.h>
#include <symbols.h>
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_START ((uintptr_t)_dram/MiB)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
/* Arbitrary range of DMA memory for depthcharge's drivers */
#define DMA_START (0x77300000)
#define DMA_SIZE (0x00100000)
static struct edid edid = {
.ha = 1366,
.va = 768,
@ -469,7 +466,8 @@ static void mainboard_enable(device_t dev)
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
@ -493,6 +491,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (intptr_t)DMA_START;
dma->range_size = DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/peach_pit/memlayout.ld Normal file
View File

@ -0,0 +1 @@
#include <soc/samsung/exynos5420/memlayout.ld>

4
src/mainboard/google/rush/Makefile.inc
View File

@ -40,3 +40,7 @@ ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-y += reset.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

1
src/mainboard/google/rush/memlayout.ld Normal file
View File

@ -0,0 +1 @@
#include <soc/nvidia/tegra132/memlayout.ld>

4
src/mainboard/google/rush_ryu/Makefile.inc
View File

@ -41,3 +41,7 @@ ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-y += reset.c
ramstage-y += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

1
src/mainboard/google/rush_ryu/memlayout.ld Normal file
View File

@ -0,0 +1 @@
#include <soc/nvidia/tegra132/memlayout.ld>

8
src/mainboard/google/storm/Kconfig
View File

@ -48,12 +48,4 @@ config DRAM_SIZE_MB
default 512 if BOARD_VARIANT_AP148
default 1024
config DRAM_DMA_START
hex
default 0x5a000000
config DRAM_DMA_SIZE
hex
default 0x00200000
endif # BOARD_GOOGLE_STORM

4
src/mainboard/google/storm/Makefile.inc
View File

@ -25,3 +25,7 @@ romstage-y += cdp.c
ramstage-y += boardid.c
ramstage-y += cdp.c
ramstage-y += mainboard.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

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