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mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5 

Assign 7-bit address of the targeted slave SPD.

TEST=Able to read correct SPD data from SMBUS.

Change-Id: If24e61b583638be7c055541c6eb126da28b542f6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2021-02-15 21:48:51 +05:30
parent a7adf77afe
commit d93a5bc115
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/intel/adlrvp/romstage_fsp_params.c
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@ -39,12 +39,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = {
.addr_dimm[0] = 0xa0,
.addr_dimm[1] = 0xa2,
.addr_dimm[0] = 0x50,
.addr_dimm[1] = 0x51,
},
[1] = {
.addr_dimm[0] = 0xa4,
.addr_dimm[1] = 0xa6,
.addr_dimm[0] = 0x52,
.addr_dimm[1] = 0x53,
},
},
};