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sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported 

The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.

We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.

Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.

Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Patrick Rudolph 2019-07-15 18:04:23 +02:00 committed by Patrick Rudolph
parent fa0ef81d15
commit b30a47b841
47 changed files with 8 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/apple/macbookair4_2/devicetree.cb
View File

@ -38,7 +38,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x001c0301"
register "gen4_dec" = "0x00fc0701"
register "gpi7_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/asrock/b75pro3-m/devicetree.cb
View File

@ -58,7 +58,6 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0241"
register "gen3_dec" = "0x000c0251"
register "p_cnt_throttling_supported" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "0"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/asus/maximus_iv_gene-z/devicetree.cb
View File

@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x
register "c2_latency" = "101"
register "gen1_dec" = "0x00000295" # Super I/O HWM
register "p_cnt_throttling_supported" = "1"
register "sata_port_map" = "0x3f"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"

1
src/mainboard/asus/p8h61-m_lx/devicetree.cb
View File

@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x
register "c2_latency" = "101"
register "gen1_dec" = "0x00000295" # Super I/O HWM
register "p_cnt_throttling_supported" = "1"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"

1
src/mainboard/asus/p8h61-m_pro/devicetree.cb
View File

@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
register "gen1_dec" = "0x000c0291" # HWM
register "p_cnt_throttling_supported" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"

1
src/mainboard/compulab/intense_pc/devicetree.cb
View File

@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
register "gen3_dec" = "0x000406f1"
register "gen4_dec" = "0x000c06a1"
register "gpi7_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
View File

@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge
register "sata_interface_speed_support" = "0x3"
register "pcie_port_coalesce" = "0"
register "p_cnt_throttling_supported" = "0"
register "docking_supported" = "0"
register "c2_latency" = "0x0065"

1
src/mainboard/google/butterfly/devicetree.cb
View File

@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1

1
src/mainboard/google/link/devicetree.cb
View File

@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2

1
src/mainboard/google/parrot/devicetree.cb
View File

@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2

1
src/mainboard/google/stout/devicetree.cb
View File

@ -73,7 +73,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1

1
src/mainboard/hp/2570p/devicetree.cb
View File

@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/2760p/devicetree.cb
View File

@ -61,7 +61,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x007c0281"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/8460p/devicetree.cb
View File

@ -60,7 +60,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/8470p/devicetree.cb
View File

@ -61,7 +61,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/8770w/devicetree.cb
View File

@ -49,7 +49,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
View File

@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge
register "docking_supported" = "0"
register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/folio_9470m/devicetree.cb
View File

@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/revolve_810_g1/devicetree.cb
View File

@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/hp/z220_sff_workstation/devicetree.cb
View File

@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge
register "docking_supported" = "0"
register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/intel/emeraldlake2/devicetree.cb
View File

@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x003c0701"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2

1
src/mainboard/kontron/ktqm77/devicetree.cb
View File

@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "0"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"

1
src/mainboard/lenovo/l520/devicetree.cb
View File

@ -46,7 +46,6 @@ chip northbridge/intel/sandybridge
register "gen4_dec" = "0x00000000"
register "gpi13_routing" = "2"
register "gpi6_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/lenovo/s230u/devicetree.cb
View File

@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge
register "gen4_dec" = "0x000c06a1"
register "gpi13_routing" = "2"
register "gpi7_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/lenovo/t420/devicetree.cb
View File

@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
# device specific SPI configuration
register "spi_uvscc" = "0x2005"

1
src/mainboard/lenovo/t420s/devicetree.cb
View File

@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

1
src/mainboard/lenovo/t430/devicetree.cb
View File

@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x000c06a1"
register "gpi13_routing" = "2"
register "gpi1_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/lenovo/t430s/devicetree.cb
View File

@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "docking_supported" = "1"
register "spi_uvscc" = "0x2005"

1
src/mainboard/lenovo/t520/variants/t520/devicetree.cb
View File

@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"

1
src/mainboard/lenovo/t520/variants/w520/devicetree.cb
View File

@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"

1
src/mainboard/lenovo/t530/variants/t530/devicetree.cb
View File

@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"

1
src/mainboard/lenovo/t530/variants/w530/devicetree.cb
View File

@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x007c1601"
register "gen2_dec" = "0x000c15e1"
register "gen4_dec" = "0x000c06a1"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/mainboard/lenovo/x131e/devicetree.cb
View File

@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "0x0065"
register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

1
src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
View File

@ -70,7 +70,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

1
src/mainboard/lenovo/x201/devicetree.cb
View File

@ -68,7 +68,6 @@ chip northbridge/intel/nehalem
register "gen3_dec" = "0x1c1681"
register "gen4_dec" = "0x040069"
register "p_cnt_throttling_supported" = "1"
register "c2_latency" = "1"
register "docking_supported" = "1"

1
src/mainboard/lenovo/x220/devicetree.cb
View File

@ -69,7 +69,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

1
src/mainboard/lenovo/x230/devicetree.cb
View File

@ -72,7 +72,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

1
src/mainboard/msi/ms7707/devicetree.cb
View File

@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge
register "docking_supported" = "0"
register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0a01"
register "p_cnt_throttling_supported" = "1"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"

1
src/mainboard/roda/rv11/variants/rv11/devicetree.cb
View File

@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
register "p_cnt_throttling_supported" = "1"
register "xhci_overcurrent_mapping" = "0x00080401"
register "xhci_switchable_ports" = "0x0f"

1
src/mainboard/roda/rv11/variants/rw11/devicetree.cb
View File

@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
register "p_cnt_throttling_supported" = "1"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0f"

1
src/mainboard/samsung/lumpy/devicetree.cb
View File

@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x00fc1601"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2

1
src/mainboard/samsung/stumpy/devicetree.cb
View File

@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
register "gen1_dec" = "0x00fc1601"
# SuperIO range is 0x700-0x73f

1
src/mainboard/sapphire/pureplatinumh61/devicetree.cb
View File

@ -50,7 +50,6 @@ chip northbridge/intel/sandybridge
register "gen2_dec" = "0x000c0a01"
register "gen3_dec" = "0x00000000"
register "gen4_dec" = "0x00000000"
register "p_cnt_throttling_supported" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"

1
src/southbridge/intel/bd82x6x/chip.h
View File

@ -82,7 +82,6 @@ struct southbridge_intel_bd82x6x_config {
uint8_t pcie_aspm_f6;
uint8_t pcie_aspm_f7;
int p_cnt_throttling_supported;
int c2_latency;
int docking_supported;

10
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -768,12 +768,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
if (chip->p_cnt_throttling_supported) {
fadt->duty_width = 3;
} else {
fadt->duty_width = 0;
}
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;

10
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -680,12 +680,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
if (chip->p_cnt_throttling_supported) {
fadt->duty_width = 3;
} else {
fadt->duty_width = 0;
}
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x32;

1
util/autoport/bd82x6x.go
View File

@ -233,7 +233,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
"c2_latency": FormatHexLE16(FADT[96:98]),
"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),