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mb/google/hatch: Remove hatch_whl 

Hatch_whl variant is deprecated.

BUG=b:137180390

Change-Id: I88fa201398ad5fb70da48d022f1ae86fecafa660
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34432
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Philip Chen 2019-07-18 21:34:01 -07:00 committed by Martin Roth
parent d03ae8c33a
commit b3042ed234
8 changed files with 0 additions and 289 deletions
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3
src/mainboard/google/hatch/Kconfig
View File

@ -63,7 +63,6 @@ config GBB_HWID
string
depends on CHROMEOS
default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL
default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS
default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED
default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU
@ -79,7 +78,6 @@ config MAINBOARD_FAMILY
config MAINBOARD_PART_NUMBER
string
default "Hatch" if BOARD_GOOGLE_HATCH
default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL
default "Helios" if BOARD_GOOGLE_HELIOS
default "Kindred" if BOARD_GOOGLE_KINDRED
default "Kohaku" if BOARD_GOOGLE_KOHAKU
@ -103,7 +101,6 @@ config TPM_TIS_ACPI_INTERRUPT
config VARIANT_DIR
string
default "hatch" if BOARD_GOOGLE_HATCH
default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL
default "helios" if BOARD_GOOGLE_HELIOS
default "kindred" if BOARD_GOOGLE_KINDRED
default "kohaku" if BOARD_GOOGLE_KOHAKU

6
src/mainboard/google/hatch/Kconfig.name
View File

@ -6,12 +6,6 @@ config BOARD_GOOGLE_HATCH
select BOARD_ROMSIZE_KB_32768
select SOC_INTEL_COMETLAKE
config BOARD_GOOGLE_HATCH_WHL
bool "-> Hatch_whl"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_32768
select SOC_INTEL_WHISKEYLAKE
config BOARD_GOOGLE_KOHAKU
bool "-> Kohaku"
select BOARD_GOOGLE_BASEBOARD_HATCH

22
src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc
View File

@ -1,22 +0,0 @@
## This file is part of the coreboot project.
##
## Copyright 2019 Google LLC
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
SPD_SOURCES = 4G_2400 # 0b000
SPD_SOURCES += empty_ddr4 # 0b001
SPD_SOURCES += empty_ddr4 # 0b010
SPD_SOURCES += empty_ddr4 # 0b011
SPD_SOURCES += empty_ddr4 # 0b100
SPD_SOURCES += 8G_2666 # 0b101
ramstage-y += gpio.c

32
src/mainboard/google/hatch/variants/hatch_whl/gpio.c
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = {
/* C13 : EC_PCH_INT_L
* TODO Configure it back to invert mode, when
* ITSS IPCx configuration is fixed in FSP.
*/
PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, NONE)};
const struct pad_config *override_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}

16
src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl
View File

@ -1,16 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/dptf.asl>

21
src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h
View File

@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_EC_H
#define VARIANT_EC_H
#include <baseboard/ec.h>
#endif

27
src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h
View File

@ -1,27 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
/* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_F20
#define GPIO_MEM_CONFIG_1 GPP_F21
#define GPIO_MEM_CONFIG_2 GPP_F11
#define GPIO_MEM_CONFIG_3 GPP_F22
#endif

162
src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb
View File

@ -1,162 +0,0 @@
chip soc/intel/cannonlake
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| GSPI1 | FP MCU |
#| I2C0 | Touchpad |
#| I2C1 | Touch screen |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
}"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"
# USB configuration
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete BT
device domain 0 on
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""Discrete bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)"
device usb 2.4 on end
end
end
end
end # USB xHCI
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)"
register "wake" = "GPE0_DW0_21"
device i2c 15 on end
end
end # I2C #0
device pci 15.1 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
register "probed" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "reset_delay_ms" = "100"
register "reset_off_delay_ms" = "5"
register "has_power_resource" = "1"
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
register "stop_off_delay_ms" = "5"
device i2c 49 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""GDIX0000""
register "generic.desc" = ""Goodix Touchscreen""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "generic.reset_delay_ms" = "10"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
register "key.wake" = "GPE0_DW0_08"
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 on
chip drivers/i2c/sx9310
register "desc" = ""SAR Proximity Sensor""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "1"
register "reg_prox_ctrl0" = "0x10"
register "reg_prox_ctrl1" = "0x00"
register "reg_prox_ctrl2" = "0x84"
register "reg_prox_ctrl3" = "0x0e"
register "reg_prox_ctrl4" = "0x07"
register "reg_prox_ctrl5" = "0xc6"
register "reg_prox_ctrl6" = "0x20"
register "reg_prox_ctrl7" = "0x0d"
register "reg_prox_ctrl8" = "0x8d"
register "reg_prox_ctrl9" = "0x43"
register "reg_prox_ctrl10" = "0x1f"
register "reg_prox_ctrl11" = "0x00"
register "reg_prox_ctrl12" = "0x00"
register "reg_prox_ctrl13" = "0x00"
register "reg_prox_ctrl14" = "0x00"
register "reg_prox_ctrl15" = "0x00"
register "reg_prox_ctrl16" = "0x00"
register "reg_prox_ctrl17" = "0x00"
register "reg_prox_ctrl18" = "0x00"
register "reg_prox_ctrl19" = "0x00"
register "reg_sar_ctrl0" = "0x50"
register "reg_sar_ctrl1" = "0x8a"
register "reg_sar_ctrl2" = "0x3c"
device i2c 28 on end
end
end # I2C #3
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
register "property_count" = "1"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end #I2C #4
device pci 1e.3 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
device spi 1 on end
end # FPMCU
end # GSPI #1
end
end