diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index d35a07ed5957..0a79ed7b98f2 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -49,6 +49,7 @@ ramstage-y += ../common/pmic_wrap.c
 ramstage-y += ../common/rtc.c rtc.c
 ramstage-y += soc.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += sspm.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/usb.c
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index e9f80d160777..0f085b2c8dfb 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -34,6 +34,8 @@ enum {
 	EMI_BASE		= IO_PHYS + 0x00219000,
 	EMI_MPU_BASE		= IO_PHYS + 0x00226000,
 	DRAMC_CH_BASE		= IO_PHYS + 0x00228000,
+	SSPM_SRAM_BASE		= IO_PHYS + 0x00400000,
+	SSPM_CFG_BASE		= IO_PHYS + 0x00440000,
 	AUXADC_BASE		= IO_PHYS + 0x01001000,
 	UART0_BASE		= IO_PHYS + 0x01002000,
 	SPI0_BASE		= IO_PHYS + 0x0100A000,
diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h
new file mode 100644
index 000000000000..627088fdc770
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/sspm.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_SSPM_H
+#define SOC_MEDIATEK_MT8183_SSPM_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8183_sspm_regs {
+	u32 sw_rstn;
+};
+static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_CFG_BASE;
+void sspm_init(void);
+#endif  /* SOC_MEDIATEK_MT8183_SSPM_H */
diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c
new file mode 100644
index 000000000000..559034eacbfc
--- /dev/null
+++ b/src/soc/mediatek/mt8183/sspm.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/barrier.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <arch/mmio.h>
+#include <soc/sspm.h>
+#include <string.h>
+
+#define BUF_SIZE (64 * KiB)
+static uint8_t sspm_bin[BUF_SIZE] __aligned(8);
+
+void sspm_init(void)
+{
+	const char *file_name = "sspm.bin";
+	size_t fw_size = cbfs_boot_load_file(file_name,
+					     sspm_bin,
+					     sizeof(sspm_bin),
+					     CBFS_TYPE_RAW);
+
+	if (fw_size == 0)
+		die("SSPM file :sspm.bin not found.");
+
+	memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size);
+	/* Memory barrier to ensure that all fw code is loaded
+	   before we release the reset pin. */
+	mb();
+	write32(&mt8183_sspm->sw_rstn, 0x1);
+}