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superio/smsc: pass the chip-specific ops struct to pnp_enable_devices 

Pass the address of the chip-specific ops struct instead of the one of the
generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.

Change-Id: I16e485494e448ae02e0a7b9e21b90ddbb1a53a4b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Felix Held 2018-07-06 23:39:00 +02:00 committed by Martin Roth
parent c40275bce0
commit b0d868e8fe
14 changed files with 87 additions and 92 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/superio/smsc/dme1737/superio.c
View File

@ -50,18 +50,18 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, DME1737_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, DME1737_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, DME1737_RT, PNP_IO0, 0x0780, },
{ NULL, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, DME1737_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, DME1737_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, DME1737_RT, PNP_IO0, 0x0780, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_dme1737_ops = {

9
src/superio/smsc/fdc37n972/superio.c
View File

@ -46,16 +46,15 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, FDC37N972_SP2,
{ NULL, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, FDC37N972_SP2,
PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ NULL, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_fdc37n972_ops = {

7
src/superio/smsc/kbc1100/superio.c
View File

@ -45,14 +45,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, KBC1100_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x7ff,
0x7ff, },
{ NULL, KBC1100_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x7ff, 0x7ff, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
static void kbc1100_init(struct device *dev)

16
src/superio/smsc/lpc47b272/superio.c
View File

@ -61,12 +61,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, LPC47B272_RT, PNP_IO0, 0x0780, },
{ NULL, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, LPC47B272_RT, PNP_IO0, 0x0780, },
};
/**
@ -77,8 +78,7 @@ static struct pnp_info pnp_dev_info[] = {
*/
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_lpc47b272_ops = {

18
src/superio/smsc/lpc47b397/superio.c
View File

@ -135,19 +135,19 @@ static struct device_operations ops_hwm = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, },
{ &ops, LPC47B397_RT, PNP_IO0, 0x0780, },
{ NULL, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, },
{ NULL, LPC47B397_RT, PNP_IO0, 0x0780, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_lpc47b397_ops = {

16
src/superio/smsc/lpc47m10x/superio.c
View File

@ -59,12 +59,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, LPC47M10X2_PME, PNP_IO0, 0x0f80, },
{ NULL, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, LPC47M10X2_PME, PNP_IO0, 0x0f80, },
};
/**
@ -75,8 +76,7 @@ static struct pnp_info pnp_dev_info[] = {
*/
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_lpc47m10x_ops = {

14
src/superio/smsc/lpc47m15x/superio.c
View File

@ -45,17 +45,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ NULL, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
static void lpc47m15x_init(struct device *dev)

9
src/superio/smsc/lpc47n217/superio.c
View File

@ -57,9 +57,9 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }
{ NULL, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }
};
/**
@ -70,8 +70,7 @@ static struct pnp_info pnp_dev_info[] = {
*/
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
/**

11
src/superio/smsc/lpc47n227/superio.c
View File

@ -55,10 +55,10 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ NULL, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
};
/**
@ -69,8 +69,7 @@ static struct pnp_info pnp_dev_info[] = {
*/
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
/**

17
src/superio/smsc/mec1308/superio.c
View File

@ -49,19 +49,18 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, MEC1308_PM1, PNP_IO0, 0x7ff },
{ &ops, MEC1308_EC1, PNP_IO0, 0x7ff },
{ &ops, MEC1308_EC2, PNP_IO0, 0x7ff },
{ &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, MEC1308_KBC, PNP_IRQ0, 0 /* IO Fixed at 0x60/0x64 */ },
{ &ops, MEC1308_EC0, PNP_IO0, 0x7ff },
{ &ops, MEC1308_MBX, PNP_IO0, 0x7ff },
{ NULL, MEC1308_PM1, PNP_IO0, 0x7ff },
{ NULL, MEC1308_EC1, PNP_IO0, 0x7ff },
{ NULL, MEC1308_EC2, PNP_IO0, 0x7ff },
{ NULL, MEC1308_UART, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ NULL, MEC1308_KBC, PNP_IRQ0, 0 /* IO Fixed at 0x60/0x64 */ },
{ NULL, MEC1308_EC0, PNP_IO0, 0x7ff },
{ NULL, MEC1308_MBX, PNP_IO0, 0x7ff },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_mec1308_ops = {

5
src/superio/smsc/sch4037/superio.c
View File

@ -48,12 +48,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x7ff, 0x7ff, },
{ NULL, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x7ff, 0x7ff, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_sch4037_ops = {

2
src/superio/smsc/sio1036/superio.c
View File

@ -41,7 +41,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
};
static void enable_dev(struct device *dev)

5
src/superio/smsc/sio10n268/superio.c
View File

@ -47,13 +47,12 @@ static struct device_operations ops = {
/* TODO: FDC, PP, AUX. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, 0x07f8, 0x07f8, },
{ NULL, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, 0x07f8, 0x07f8, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_smsc_sio10n268_ops = {

34
src/superio/smsc/smscsuperio/superio.c
View File

@ -194,21 +194,22 @@ static struct device_operations ops = {
* TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet).
*/
static struct pnp_info pnp_dev_info[] = {
{ &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LD_RTC, },
{ &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, LD_AUX, },
{ &ops, LD_XBUS, },
{ &ops, LD_HWM, PNP_IO0, 0x07f0, },
{ &ops, LD_GAME, },
{ &ops, LD_PME, },
{ &ops, LD_MPU401, },
{ &ops, LD_RT, PNP_IO0, 0x0780, },
{ &ops, LD_ACPI, },
{ &ops, LD_SMB, },
{ NULL, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ NULL, LD_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LD_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, LD_RTC, },
{ NULL, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x07ff, 0x07ff, },
{ NULL, LD_AUX, },
{ NULL, LD_XBUS, },
{ NULL, LD_HWM, PNP_IO0, 0x07f0, },
{ NULL, LD_GAME, },
{ NULL, LD_PME, },
{ NULL, LD_MPU401, },
{ NULL, LD_RT, PNP_IO0, 0x0780, },
{ NULL, LD_ACPI, },
{ NULL, LD_SMB, },
};
/**
@ -281,8 +282,7 @@ static void enable_dev(struct device *dev)
}
/* Enable the specified devices (if present on the chip). */
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
&pnp_dev_info[0]);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
/* Restore LD_FOO values. */
for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)