mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
This is another readily available (used market) system. Based on autoport. * All peripherals should work. * Automatic fan control as well as S3 are working. * The board was tested to boot Linux and Windows. EHCI debug is untested. * When using MrChromebox edk2 with secure boot build in, the board will hang on each boot for about 20 seconds before continuing. There are some quirks for doing the first flash, see the documentation. Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Joel Linn
Felix Singer
parent
934a32d752
commit
a70493d5b2
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# HP Pro 3500 Series
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This page describes how to run coreboot on the [Pro 3500 Series]
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desktop from [HP].
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## State
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All peripherals should work. Automatic fan control as well as S3 are
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working. The board was tested to boot Linux and Windows. EHCI debug
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is untested. When using MrChromebox edk2 with secure boot build in, the
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board will hang on each boot for about 20 seconds before continuing.
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With disabled ME, the SuperIO will not get CPU temperatures via PECI and
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therefore the automatic fan control will not increase the fan speed.
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## Flashing coreboot
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```{eval_rst}
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+---------------------+-------------------------+
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| Type | Value |
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+=====================+=========================+
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| Socketed flash | No |
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+---------------------+-------------------------+
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| Model | W25Q64FVSIG |
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+---------------------+-------------------------+
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| Size | 8 MiB |
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+---------------------+-------------------------+
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| In circuit flashing | Yes |
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+---------------------+-------------------------+
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| Package | SOIC-8 |
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+---------------------+-------------------------+
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| Write protection | See below |
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+---------------------+-------------------------+
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| Dual BIOS feature | No |
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+---------------------+-------------------------+
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| Internal flashing | Yes |
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+---------------------+-------------------------+
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```
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### Flash layout
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The original layout of the flash should look like this:
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```
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00000000:00000fff fd
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00400000:007fffff bios
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00001000:003fffff me
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00fff000:00000fff gbe
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00fff000:00000fff pd
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```
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### Internal programming
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The SPI flash can be accessed using [flashrom] (although it reports as
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"N25Q064..3E", it works fine).
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With a missing FDO jumper, `fd` region is read-only, `bios` region is
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read-write and `me` region is locked. Vendor firmware will additionally
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protect the flash chip. After shorting the FDO jumper (E2) full
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read-write access is granted.
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Do **NOT shutdown** the operating system **after flashing** coreboot
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from the vendor firmware! This will brick your device because the bios
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region will be modified on shutdown. Cut the AC power or do a restart
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from the OS.
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**Position of FDO jumper (E2) close to the F_USB3**
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![][pro_3500_jumper]
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[pro_3500_jumper]: pro_3500_series_jumper.avif
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### External programming
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External programming with an SPI adapter and [flashrom] does work, but
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it powers the whole southbridge complex. The average current will be
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400mA but spikes may be higher. Connect the power to the flash or the
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programming header next to the flash otherwise programming is unstable.
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The supply needs to quickly reach 3V3 or else the chip is also unstable
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until cleanly power cycled.
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**Position of SOIC-8 flash and pin-header near ATX power connector**
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![][pro_3500_flash]
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[pro_3500_flash]: pro_3500_series_flash.avif
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## Technology
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```{eval_rst}
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x (bd82h61) |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| SuperIO | IT8779E (identifies as IT8772F via register) |
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+------------------+--------------------------------------------------+
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| EC | Fixed function as part of SuperIO |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel ME |
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+------------------+--------------------------------------------------+
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```
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[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089
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[HP]: https://www.hp.com/
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[flashrom]: https://flashrom.org/Flashrom
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Binary file not shown.
Binary file not shown.
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@ -127,6 +127,7 @@ GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
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Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
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Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
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Pro 3500 Series <hp/pro_3500_series.md>
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Z220 Workstation SFF <hp/z220_sff.md>
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```
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# SPDX-License-Identifier: GPL-2.0-or-later
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if BOARD_HP_PRO_3500_SERIES
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_USES_IFD_GBE_REGION
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select NO_UART_ON_SUPERIO
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_ITE_IT8772F
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select USE_NATIVE_RAMINIT
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config CBFS_SIZE
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default 0x400000
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config MAINBOARD_DIR
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default "hp/pro_3500_series"
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config MAINBOARD_PART_NUMBER
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default "Pro 3500 Series"
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config VGA_BIOS_ID
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default "8086,0152"
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config DRAM_RESET_GATE_GPIO
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default 60
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config USBDEBUG_HCD_INDEX
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default 2
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endif
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# SPDX-License-Identifier: GPL-2.0-or-later
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config BOARD_HP_PRO_3500_SERIES
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bool "Pro 3500 Series"
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# SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += early_init.c
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bootblock-y += gpio.c
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bootblock-y += led.c
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romstage-y += early_init.c
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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smm-y += led.c
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: CC-PDDC */
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/* Please update the license if adding licensable material. */
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/* SPDX-License-Identifier: GPL-2.0-only */
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Method(_WAK, 1)
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{
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Return(Package() {0, 0})
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}
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Method(_PTS, 1)
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{
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Values should match those defined in devicetree.cb */
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#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
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#undef SIO_ENABLE_COM1 // pnp 2e.1: Disable Serial Port 1
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#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard
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#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse
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#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
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#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
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#define SIO_ENVC_IO0 0xa30 // pnp 2e.4: io 0x60
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#define SIO_ENVC_IO1 0xa20 // pnp 2e.4: io 0x62
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#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
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#define SIO_GPIO_IO0 0x0 // pnp 2e.7: io 0x60
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#define SIO_GPIO_IO1 0xa00 // pnp 2e.7: io 0x62
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#include <superio/ite/it8772f/acpi/superio.asl>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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@ -0,0 +1,6 @@
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Category: desktop
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2012
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __MAINBOARD_COMMON_DEFINES_H
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#define __MAINBOARD_COMMON_DEFINES_H
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#include <superio/ite/it8772f/it8772f.h>
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#define IT8772F_BASE 0x2e
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#define EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC)
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#define GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
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#endif /* __MAINBOARD_COMMON_DEFINES_H */
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Binary file not shown.
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/sandybridge
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# XMM1: CH0S0 0x50
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# XMM3: CH1S0 0x52
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register "spd_addresses" = "{0x50, 0, 0x52, 0}"
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device domain 0x0 on
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subsystemid 0x103c 0x2abf inherit
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device ref peg10 on end
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device ref igd on end
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "gen1_dec" = "0x003c0a01"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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# SATA0: ata1 0x01
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# SATA1: ata2 0x02
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# SATA2: ata5 0x10
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# SATA3: ata6 0x20
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register "sata_port_map" = "0x33"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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device ref ehci2 on end
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device ref hda on end
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device ref pcie_rp2 on end # MINI_PCIE
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device ref pcie_rp3 on end # PCIEx1_1
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device ref pcie_rp4 on end # PCIEx1_2
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device ref pcie_rp5 on end # PCIEx1_3
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device ref pcie_rp6 on end # RTL8171EH
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device ref ehci1 on end
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device ref lpc on
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chip superio/ite/it8772f
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# GPIO registers all zero or written by LED code
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register "ec.smbus_en" = "1"
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register "TMPIN1.mode" = "THERMAL_MODE_DISABLED"
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register "TMPIN2.mode" = "THERMAL_DIODE" # Near ATX_CPU connector
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register "TMPIN3.mode" = "THERMAL_PECI"
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# TMPIN3.offset is set to TJ_MAX at runtime
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# CPU fan
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register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
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register "FAN2.smart.tmpin" = "3"
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register "FAN2.smart.tmp_off" = "-127"
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register "FAN2.smart.tmp_start" = "40"
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register "FAN2.smart.tmp_full" = "86"
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register "FAN2.smart.tmp_delta" = "5"
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register "FAN2.smart.pwm_start" = "25"
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register "FAN2.smart.slope" = "6"
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# System fan
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register "FAN3.mode" = "FAN_SMART_AUTOMATIC"
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register "FAN3.smart.tmpin" = "3"
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register "FAN3.smart.tmp_off" = "-127"
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register "FAN3.smart.tmp_start" = "40"
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register "FAN3.smart.tmp_full" = "86"
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register "FAN3.smart.tmp_delta" = "5"
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register "FAN3.smart.pwm_start" = "34"
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register "FAN3.smart.slope" = "11"
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register "FAN_VECA.tmpin" = "2"
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register "FAN_VECA.fanout" = "2"
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register "FAN_VECA.tmp_start" = "57"
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register "FAN_VECA.tmp_delta" = "5"
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register "FAN_VECA.slope" = "26"
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register "FAN_VECB.tmpin" = "2"
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register "FAN_VECB.fanout" = "3"
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register "FAN_VECB.tmp_start" = "48"
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register "FAN_VECB.tmp_delta" = "5"
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register "FAN_VECB.slope" = "5"
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register "ec.vin_mask" = "VIN_ALL"
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device pnp 2e.0 off end # FDC
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device pnp 2e.1 off end # Serial Port 1
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device pnp 2e.4 on # Environment Controller
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io 0x60 = 0xa30
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io 0x62 = 0xa20
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end
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device pnp 2e.7 on # GPIO
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io 0x60 = 0x0
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io 0x62 = 0xa00
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end
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device pnp 2e.5 off end # Keyboard, enabled in vendor firmware but missing connector
|
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device pnp 2e.6 off end # Mouse , enabled in vendor firmware but missing connector
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device pnp 2e.a off end # IR
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end
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end
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device ref sata1 on end
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end
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end
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end
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
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#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
|
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018
|
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)
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{
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#include <acpi/dsdt_top.asl>
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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|
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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}
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}
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||||
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@ -0,0 +1,40 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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||||
|
||||
#include <bootblock_common.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <superio/hwm5_conf.h>
|
||||
#include "common_defines.h"
|
||||
#include "led.h"
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 6, 0 },
|
||||
{ 1, 6, 0 },
|
||||
{ 1, 6, 1 },
|
||||
{ 1, 9, 1 },
|
||||
{ 1, 10, 2 },
|
||||
{ 1, 11, 2 },
|
||||
{ 1, 6, 3 },
|
||||
{ 1, 6, 3 },
|
||||
{ 1, 6, 4 },
|
||||
{ 1, 12, 4 },
|
||||
{ 1, 6, 6 },
|
||||
{ 1, 11, 5 },
|
||||
{ 1, 6, 5 },
|
||||
{ 1, 6, 6 },
|
||||
};
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
|
||||
|
||||
/* Early SuperIO setup */
|
||||
ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
|
||||
/* Clear when resuming from S3: */
|
||||
ite_disable_3vsbsw(GPIO_DEV);
|
||||
ite_disable_pme_out(EC_DEV);
|
||||
ite_ac_resume_southbridge(EC_DEV);
|
||||
|
||||
set_power_led(LED_WHITE);
|
||||
}
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||||
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|
@ -0,0 +1,16 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
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||||
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|
@ -0,0 +1,189 @@
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|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_NATIVE,
|
||||
.gpio3 = GPIO_MODE_NATIVE,
|
||||
.gpio4 = GPIO_MODE_NATIVE,
|
||||
.gpio5 = GPIO_MODE_NATIVE,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_NATIVE,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_NATIVE,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_NATIVE,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio12 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio22 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_INPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio8 = GPIO_LEVEL_HIGH,
|
||||
.gpio12 = GPIO_LEVEL_HIGH,
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_NATIVE,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_NATIVE,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_GPIO,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_NATIVE,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_NATIVE,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_GPIO,
|
||||
.gpio61 = GPIO_MODE_GPIO,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio43 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_OUTPUT,
|
||||
.gpio57 = GPIO_DIR_OUTPUT,
|
||||
.gpio60 = GPIO_DIR_OUTPUT,
|
||||
.gpio61 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio49 = GPIO_LEVEL_HIGH,
|
||||
.gpio57 = GPIO_LEVEL_HIGH,
|
||||
.gpio60 = GPIO_LEVEL_LOW,
|
||||
.gpio61 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0662, /* Codec Vendor / Device ID: Realtek */
|
||||
0x103c2abf, /* Subsystem ID */
|
||||
11, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x103c2abf),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19830),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19831),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "common_defines.h"
|
||||
#include "led.h"
|
||||
|
||||
void set_power_led(int state)
|
||||
{
|
||||
// Board has a dual color LED
|
||||
it8772f_gpio_setup(
|
||||
GPIO_DEV,
|
||||
2, /* set */
|
||||
0xf3 | LED_BOTH, /* select, 0xf3 is default */
|
||||
state, /* polarity */
|
||||
0x00, /* pullup */
|
||||
LED_BOTH, /* output */
|
||||
0x00); /* enable */
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __MAINBOARD_LED_H
|
||||
#define __MAINBOARD_LED_H
|
||||
|
||||
#ifndef __ACPI__
|
||||
void set_power_led(int state);
|
||||
|
||||
enum {
|
||||
LED_WHITE = 1 << 2, // GPIO 22
|
||||
LED_YELLOW = 1 << 3, // GPIO 23
|
||||
LED_BOTH = LED_WHITE | LED_YELLOW,
|
||||
LED_OFF = LED_BOTH
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* __MAINBOARD_LED_H */
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <cpu/intel/model_206ax/model_206ax.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <device/device.h>
|
||||
#include <static_devices.h>
|
||||
#include <superio/ite/it8772f/chip.h>
|
||||
|
||||
static u8 cpu_get_temp_offset(void)
|
||||
{
|
||||
msr_t msr = rdmsr(MSR_TEMPERATURE_TARGET);
|
||||
u8 tj_max = (msr.lo >> 16) & 0xFF;
|
||||
u8 tcc_offset = (msr.lo >> 24) & 0xf;
|
||||
|
||||
msr = rdmsr(MSR_PLATFORM_INFO);
|
||||
if (msr.lo & (1 << 30)) {
|
||||
return tj_max - tcc_offset;
|
||||
} else {
|
||||
return tj_max;
|
||||
}
|
||||
}
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
/* Set PECI TMPIN 3 offset to TJ_MAX temperature */
|
||||
struct superio_ite_it8772f_config *const config = __pnp_002e_04->chip_info;
|
||||
if (config)
|
||||
config->ec.tmpin[2].offset = cpu_get_temp_offset();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include "common_defines.h"
|
||||
#include "led.h"
|
||||
|
||||
/* Change power led state based on sleep type. */
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SMI: sleep S%d\n", slp_typ);
|
||||
switch (slp_typ) {
|
||||
case ACPI_S3:
|
||||
/*
|
||||
* Vendor firmware also only enables this when entering sleep.
|
||||
* This saves some power when entering S5 via shutdown.
|
||||
*/
|
||||
ite_enable_3vsbsw(GPIO_DEV);
|
||||
set_power_led(LED_YELLOW);
|
||||
break;
|
||||
case ACPI_S4:
|
||||
/* Without 3vsbsw enabled the LED will be off in any case */
|
||||
case ACPI_S5:
|
||||
set_power_led(LED_OFF);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue