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sb/intel/common/pciehp: Replace HP dummy device with common code

Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe
ports supporting hotplug. This allows to have control over how much
resources are allocated to hotplug ports.

Tested on thinkpad X220: now hotplugging a dGPU via the expresscard
slot sometimes works.

Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph
changes/68/51068/3
Arthur Heymans 2 months ago
committed by Nico Huber
parent
commit
a560c71109
  1. 3
      src/southbridge/intel/bd82x6x/Kconfig
  2. 10
      src/southbridge/intel/bd82x6x/pcie.c
  3. 39
      src/southbridge/intel/common/pciehp.c
  4. 3
      src/southbridge/intel/i82801ix/Kconfig
  5. 10
      src/southbridge/intel/i82801ix/pcie.c
  6. 3
      src/southbridge/intel/i82801jx/Kconfig
  7. 10
      src/southbridge/intel/i82801jx/pcie.c

3
src/southbridge/intel/bd82x6x/Kconfig

@ -65,4 +65,7 @@ config HIDE_MEI_ON_ERROR
device will be hidden when ME is in an inoperable mode, e.g.
if me_cleaner was used.
config PCIEXP_HOTPLUG
default y
endif

10
src/southbridge/intel/bd82x6x/pcie.c

@ -244,11 +244,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
{
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
pciexp_hotplug_scan_bridge(dev);
} else {
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
}
/* Late Power Management init after bridge device enumeration */

39
src/southbridge/intel/common/pciehp.c

@ -117,42 +117,3 @@ void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number)
acpigen_pop_len();
}
static void slot_dev_read_resources(struct device *dev)
{
struct resource *resource;
resource = new_resource(dev, PCI_BASE_ADDRESS_0);
resource->size = 1 << 23;
resource->align = 22;
resource->gran = 22;
resource->limit = 0xffffffff;
resource->flags |= IORESOURCE_MEM;
resource = new_resource(dev, 0x14);
resource->size = 1 << 23;
resource->align = 22;
resource->gran = 22;
resource->limit = 0xffffffff;
resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource = new_resource(dev, 0x18);
resource->size = 1 << 12;
resource->align = 12;
resource->gran = 12;
resource->limit = 0xffff;
resource->flags |= IORESOURCE_IO;
}
static struct device_operations slot_dev_ops = {
.read_resources = slot_dev_read_resources,
};
/* Add a dummy device to reserve I/O space for hotpluggable devices. */
void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus)
{
struct device *slot;
struct device_path slot_path = { .type = DEVICE_PATH_NONE };
slot = alloc_dev(bus, &slot_path);
slot->ops = &slot_dev_ops;
}

3
src/southbridge/intel/i82801ix/Kconfig

@ -38,4 +38,7 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED
bool
default n
config PCIEXP_HOTPLUG
default y
endif

10
src/southbridge/intel/i82801ix/pcie.c

@ -63,11 +63,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
{
struct southbridge_intel_i82801ix_config *config = dev->chip_info;
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
pciexp_hotplug_scan_bridge(dev);
} else {
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
}
}

3
src/southbridge/intel/i82801jx/Kconfig

@ -39,4 +39,7 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED
bool
default n
config PCIEXP_HOTPLUG
default y
endif

10
src/southbridge/intel/i82801jx/pcie.c

@ -63,11 +63,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
{
struct southbridge_intel_i82801jx_config *config = dev->chip_info;
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
pciexp_hotplug_scan_bridge(dev);
} else {
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
}
}

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