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soc/amd/common/block/data_fabric: add data_fabric_print_mmio_conf 

Output on Picasso at the beginning of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       93     fc00     febf
  1       93  1000000 ffffffff
  2       93     d000     f7ff
  3       90        0        0
  4       93     fed0     fed0
  5       90        0        0
  6       90        0        0
  7       90        0        0

Output on Picasso at the end of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       93     fc00     febf
  1       93  1000000 ffffffff
  2       93     d000     f7ff
  3     1093     fed0     fedf
  4       90        0        0
  5       90        0        0
  6       90        0        0
  7       90        0        0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I74617dfc6099489f3c81d0e385b502f1bbecea78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50640
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-02-13 20:38:08 +01:00
parent 05af850b28
commit 906f9be383
3 changed files with 21 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/amd/common/block/data_fabric/data_fabric_helper.c
View File

@ -2,6 +2,7 @@
#include <amdblocks/data_fabric.h>
#include <amdblocks/pci_devs.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/data_fabric.h>
#include <soc/pci_devs.h>
@ -42,6 +43,21 @@ void data_fabric_write32(uint8_t function, uint16_t reg, uint8_t instance_id, ui
pci_write_config32(SOC_DF_F4_DEV, DF_FICAD_LO, data);
}
void data_fabric_print_mmio_conf(void)
{
printk(BIOS_SPEW,
"=== Data Fabric MMIO configuration registers ===\n"
"Addresses are shifted to the right by 16 bits.\n"
"idx control base limit\n");
for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) {
printk(BIOS_SPEW, " %2u %8x %8x %8x\n",
i,
data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)),
data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)),
data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)));
}
}
void data_fabric_disable_mmio_reg(unsigned int reg)
{
data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),

1
src/soc/amd/common/block/include/amdblocks/data_fabric.h
View File

@ -42,6 +42,7 @@ void data_fabric_broadcast_write32(uint8_t function, uint16_t reg, uint32_t data
pci_write_config32(_SOC_DEV(DF_DEV, function), reg, data);
}
void data_fabric_print_mmio_conf(void);
void data_fabric_disable_mmio_reg(unsigned int reg);
int data_fabric_find_unused_mmio_reg(void);

4
src/soc/amd/picasso/data_fabric.c
View File

@ -39,6 +39,8 @@ void data_fabric_set_mmio_np(void)
const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT;
data_fabric_print_mmio_conf();
for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
/* Adjust all registers that overlap */
ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
@ -92,6 +94,8 @@ void data_fabric_set_mmio_np(void)
data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
(IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE
| MMIO_RE);
data_fabric_print_mmio_conf();
}
static const char *data_fabric_acpi_name(const struct device *dev)