Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"

in device trees. Adapt sconfig as necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-05-05 13:12:42 +00:00
parent 68befd5d34
commit 8d313685b0
114 changed files with 372 additions and 354 deletions

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -59,9 +59,9 @@ chip northbridge/amd/lx
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -9,9 +9,9 @@
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_S1G1
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -9,9 +9,9 @@
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_AM2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,8 +1,8 @@
# sample config for amd/mahogany_fam10
chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_AM2r2 #L1 and DDR2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -32,9 +32,9 @@ chip northbridge/amd/lx
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -9,9 +9,9 @@
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_AM2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,9 +1,9 @@
chip northbridge/amd/gx2
register "setupflash" = "0"
#register "irqmap" = "0xaa5b"
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_gx2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F_1207 #L1 and DDR2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,8 +1,8 @@
# sample config for amd/tilapia_fam10
chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_AM3 #L1 and DDR3
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -32,9 +32,9 @@ chip northbridge/amd/lx
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -9,9 +9,9 @@
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_939
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/amd/socket_939 # Socket 939 CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/amd/socket_939 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/amd/socket_AM2 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i82810 # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_PGA370 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,10 +1,10 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
chip cpu/intel/slot_1 # CPU
device apic 1 on end # APIC
device lapic 1 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,10 +1,10 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
chip cpu/intel/slot_1 # CPU
device apic 1 on end # APIC
device lapic 1 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -56,9 +56,9 @@ chip northbridge/via/cn700 # Northbridge
device pci 12.0 on end # Ethernet
end
end
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/via/model_c7 # VIA C7
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -58,12 +58,12 @@ chip northbridge/intel/e7520 # mch
device pci 04.0 on end
device pci 06.0 on end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604 # cpu 0
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # cpu 1
device apic 6 on end
device lapic 6 on end
end
end
register "intrline" = "0x00070100"

View File

@ -51,9 +51,9 @@ chip northbridge/intel/i855
end
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA479M
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -76,9 +76,9 @@ chip northbridge/amd/lx
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_AM2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_AM2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,8 +1,8 @@
# TODO: i810E actually!
chip northbridge/intel/i82810 # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_PGA370 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on

View File

@ -69,12 +69,12 @@ chip northbridge/amd/amdk8/root_complex
device pci 19.3 on end
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
device lapic 1 on end
end
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -67,9 +67,9 @@ chip northbridge/amd/lx
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -19,9 +19,9 @@
chip northbridge/intel/i945
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_441
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -64,9 +64,9 @@ chip northbridge/intel/i3100
device pci 1f.4 on end # Performance counters
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/bga956
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -68,12 +68,12 @@ chip northbridge/intel/e7520
register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604 # cpu 0
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # cpu 1
device apic 6 on end
device lapic 6 on end
end
end
end

View File

@ -36,9 +36,9 @@ chip northbridge/intel/i3100
device pci 1f.3 on end # SMBus
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA479M
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -46,9 +46,9 @@ chip northbridge/intel/i3100
device pci 1f.4 on end # ?
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/ep80579
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -61,12 +61,12 @@ chip northbridge/intel/e7501
device pci 1f.6 off end # AC97 Modem
end # SB
end # PCI_DOMAIN
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604
device apic 6 on end
device lapic 6 on end
end
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -77,12 +77,12 @@ chip northbridge/amd/amdk8/root_complex
device pci 19.3 on end
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
device lapic 1 on end
end
end
end

View File

@ -56,12 +56,12 @@ chip northbridge/amd/amdk8/root_complex
device pci 19.3 on end
end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
device lapic 1 on end
end
end
end

View File

@ -54,9 +54,9 @@ chip northbridge/via/cn700 # Northbridge
device pci 12.0 on end # Ethernet
end
end
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/via/model_c7 # VIA C7
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
end

View File

@ -1,8 +1,8 @@
chip northbridge/intel/i945
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mFCPGA478
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -9,9 +9,9 @@
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_S1G1
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -81,9 +81,9 @@ chip northbridge/amd/lx
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -82,9 +82,9 @@ chip northbridge/amd/lx
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end
end

View File

@ -19,9 +19,9 @@
##
chip northbridge/intel/i82810 # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_PGA370 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -19,9 +19,9 @@
##
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -19,9 +19,9 @@
##
chip northbridge/intel/i82810 # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_PGA370 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/amd/socket_754 # Socket 754 CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/amd/socket_AM2 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -22,9 +22,9 @@
##
chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F_1207
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i82810 # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_PGA370 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on

View File

@ -1,10 +1,10 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
device lapic 1 on end
end
end

View File

@ -19,9 +19,9 @@
##
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_PGA370 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,9 +1,9 @@
chip northbridge/amd/gx2
register "irqmap" = "0xaa5b"
register "setupflash" = "0"
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_gx2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,9 +1,9 @@
chip northbridge/amd/gx2
register "irqmap" = "0xaa5b"
register "setupflash" = "0"
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_gx2
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -76,9 +76,9 @@ chip northbridge/amd/lx
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i82830 # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -21,9 +21,9 @@
chip northbridge/intel/i945
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mFCPGA478
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -19,9 +19,9 @@
##
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F_1207
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_F_1207
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -52,12 +52,12 @@ chip northbridge/intel/e7525 # mch
device pci 04.0 on end
device pci 08.0 on end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604 # cpu0
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # cpu1
device apic 6 on end
device lapic 6 on end
end
end
end

View File

@ -75,12 +75,12 @@ chip northbridge/intel/e7520 # MCH
device pci 06.0 on end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604 # CPU 0
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # CPU 1
device apic 6 on end
device lapic 6 on end
end
end
end

View File

@ -75,12 +75,12 @@ chip northbridge/intel/e7520 # MCH
device pci 06.0 on end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604 # CPU 0
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # CPU 1
device apic 6 on end
device lapic 6 on end
end
end
end

View File

@ -71,12 +71,12 @@ chip northbridge/intel/e7520 # mch
end
device pci 06.0 on end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604 # cpu 0
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # cpu 1
device apic 6 on end
device lapic 6 on end
end
end
register "intrline" = "0x00070105"

View File

@ -62,12 +62,12 @@ chip northbridge/intel/e7520 # mch
device pci 04.0 on end
device pci 06.0 on end
end
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604 # cpu 0
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604 # cpu 1
device apic 6 on end
device lapic 6 on end
end
end
register "intrline" = "0x00070105"

View File

@ -9,9 +9,9 @@
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_S1G1
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -9,9 +9,9 @@
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_S1G1
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i82830 # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device apic 0 on end # APIC
device lapic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain

View File

@ -73,12 +73,12 @@ chip northbridge/intel/e7501
device pci 1f.6 off end
end # SB
end # PCI_DOMAIN
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/intel/socket_mPGA604
device apic 0 on end
device lapic 0 on end
end
chip cpu/intel/socket_mPGA604
device apic 6 on end
device lapic 6 on end
end
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

View File

@ -1,7 +1,7 @@
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
device lapic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
device lapic 0 on end
end
end
device pci_domain 0 on

Some files were not shown because too many files have changed in this diff Show More