mb/lippert/frontrunner-af: Use common sb800/acpi/pcie.asl
Change-Id: I6e6cdc49da540bd9901128bd1ef9f7060bc91f4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki
Nico Huber
parent
ec2ee184f7
commit
84355a1aad
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@ -62,32 +62,6 @@ DefinitionBlock (
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}
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} /* End _SB scope */
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/* PIC IRQ mapping registers, C00h-C01h. */
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OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
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Field(PRQM, ByteAcc, NoLock, Preserve) {
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PRQI, 0x00000008,
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PRQD, 0x00000008, /* Offset: 1h */
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}
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IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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PIRA, 0x00000008, /* Index 0 */
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PIRB, 0x00000008, /* Index 1 */
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PIRC, 0x00000008, /* Index 2 */
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PIRD, 0x00000008, /* Index 3 */
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PIRE, 0x00000008, /* Index 4 */
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PIRF, 0x00000008, /* Index 5 */
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PIRG, 0x00000008, /* Index 6 */
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PIRH, 0x00000008, /* Index 7 */
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}
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/* PCI Error control register */
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OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
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Field(PERC, ByteAcc, NoLock, Preserve) {
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SENS, 0x00000001,
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PENS, 0x00000001,
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SENE, 0x00000001,
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PENE, 0x00000001,
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}
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/* Client Management index/data registers */
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OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
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Field(CMT, ByteAcc, NoLock, Preserve) {
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@ -257,114 +231,10 @@ DefinitionBlock (
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PWDA, 1,
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}
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Scope(\_SB) {
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/* PCIe Configuration Space for 16 busses */
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OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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/* Byte offsets are computed using the following technique:
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* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
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* The 8 comes from 8 functions per device, and 4096 bytes per function config space
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*/
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Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
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STB5, 32,
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Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
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PT0D, 1,
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PT1D, 1,
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PT2D, 1,
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PT3D, 1,
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PT4D, 1,
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PT5D, 1,
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PT6D, 1,
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PT7D, 1,
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PT8D, 1,
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PT9D, 1,
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Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
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SBIE, 1,
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SBME, 1,
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Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
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SBRI, 8,
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Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
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SBB1, 32,
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Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
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,14,
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P92E, 1, /* Port92 decode enable */
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}
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OperationRegion(SB5, SystemMemory, STB5, 0x1000)
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Field(SB5, AnyAcc, NoLock, Preserve){
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/* Port 0 */
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Offset(0x120), /* Port 0 Task file status */
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P0ER, 1,
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, 2,
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P0DQ, 1,
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, 3,
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P0BY, 1,
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Offset(0x128), /* Port 0 Serial ATA status */
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P0DD, 4,
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, 4,
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P0IS, 4,
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Offset(0x12C), /* Port 0 Serial ATA control */
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P0DI, 4,
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Offset(0x130), /* Port 0 Serial ATA error */
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, 16,
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P0PR, 1,
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/* Port 1 */
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offset(0x1A0), /* Port 1 Task file status */
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P1ER, 1,
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, 2,
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P1DQ, 1,
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, 3,
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P1BY, 1,
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Offset(0x1A8), /* Port 1 Serial ATA status */
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P1DD, 4,
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, 4,
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P1IS, 4,
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Offset(0x1AC), /* Port 1 Serial ATA control */
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P1DI, 4,
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Offset(0x1B0), /* Port 1 Serial ATA error */
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, 16,
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P1PR, 1,
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/* Port 2 */
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Offset(0x220), /* Port 2 Task file status */
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P2ER, 1,
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, 2,
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P2DQ, 1,
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, 3,
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P2BY, 1,
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Offset(0x228), /* Port 2 Serial ATA status */
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P2DD, 4,
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, 4,
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P2IS, 4,
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Offset(0x22C), /* Port 2 Serial ATA control */
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P2DI, 4,
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Offset(0x230), /* Port 2 Serial ATA error */
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, 16,
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P2PR, 1,
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/* Port 3 */
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Offset(0x2A0), /* Port 3 Task file status */
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P3ER, 1,
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, 2,
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P3DQ, 1,
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, 3,
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P3BY, 1,
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Offset(0x2A8), /* Port 3 Serial ATA status */
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P3DD, 4,
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, 4,
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P3IS, 4,
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Offset(0x2AC), /* Port 3 Serial ATA control */
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P3DI, 4,
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Offset(0x2B0), /* Port 3 Serial ATA error */
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, 16,
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P3PR, 1,
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}
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}
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#include "acpi/routing.asl"
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#include <southbridge/amd/cimx/sb800/acpi/pcie.asl>
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Scope(\_SB) {
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Method(OSFL, 0){
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@ -388,341 +258,6 @@ DefinitionBlock (
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Return(OSVR)
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}
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Method(_PIC, 0x01, NotSerialized)
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{
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If (Arg0)
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{
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\_SB.CIRQ()
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}
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PICM = Arg0
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}
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Method(CIRQ, 0x00, NotSerialized){
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PIRA = 0
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PIRB = 0
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PIRC = 0
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PIRD = 0
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PIRE = 0
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PIRF = 0
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PIRG = 0
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PIRH = 0
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}
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Name(IRQB, ResourceTemplate(){
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IRQ(Level,ActiveLow,Shared){15}
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})
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Name(IRQP, ResourceTemplate(){
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IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
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})
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Name(PITF, ResourceTemplate(){
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IRQ(Level,ActiveLow,Exclusive){9}
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})
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Device(INTA) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 1)
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Method(_STA, 0) {
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if (PIRA) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTA._STA) */
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Method(_DIS ,0) {
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PIRA = 0
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} /* End Method(_SB.INTA._DIS) */
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Method(_PRS ,0) {
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Return(IRQP)
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} /* Method(_SB.INTA._PRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRA
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Return(IRQB)
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} /* Method(_SB.INTA._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRA = Local0
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} /* End Method(_SB.INTA._SRS) */
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} /* End Device(INTA) */
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Device(INTB) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 2)
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Method(_STA, 0) {
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if (PIRB) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTB._STA) */
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Method(_DIS ,0) {
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PIRB = 0
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} /* End Method(_SB.INTB._DIS) */
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Method(_PRS ,0) {
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Return(IRQP)
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} /* Method(_SB.INTB._PRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRB
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Return(IRQB)
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} /* Method(_SB.INTB._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRB = Local0
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} /* End Method(_SB.INTB._SRS) */
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} /* End Device(INTB) */
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Device(INTC) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 3)
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Method(_STA, 0) {
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if (PIRC) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTC._STA) */
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Method(_DIS ,0) {
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PIRC = 0
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} /* End Method(_SB.INTC._DIS) */
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Method(_PRS ,0) {
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Return(IRQP)
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} /* Method(_SB.INTC._PRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRC
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Return(IRQB)
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} /* Method(_SB.INTC._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRC = Local0
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} /* End Method(_SB.INTC._SRS) */
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} /* End Device(INTC) */
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Device(INTD) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 4)
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Method(_STA, 0) {
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if (PIRD) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTD._STA) */
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Method(_DIS ,0) {
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PIRD = 0
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} /* End Method(_SB.INTD._DIS) */
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Method(_PRS ,0) {
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Return(IRQP)
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} /* Method(_SB.INTD._PRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRD
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Return(IRQB)
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} /* Method(_SB.INTD._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRD = Local0
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} /* End Method(_SB.INTD._SRS) */
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} /* End Device(INTD) */
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Device(INTE) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 5)
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Method(_STA, 0) {
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if (PIRE) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTE._STA) */
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Method(_DIS ,0) {
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PIRE = 0
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} /* End Method(_SB.INTE._DIS) */
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Method(_PRS ,0) {
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Return(IRQP)
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} /* Method(_SB.INTE._PRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRE
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Return(IRQB)
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} /* Method(_SB.INTE._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRE = Local0
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} /* End Method(_SB.INTE._SRS) */
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} /* End Device(INTE) */
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Device(INTF) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 6)
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Method(_STA, 0) {
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if (PIRF) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTF._STA) */
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Method(_DIS ,0) {
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PIRF = 0
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} /* End Method(_SB.INTF._DIS) */
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Method(_PRS ,0) {
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Return(PITF)
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} /* Method(_SB.INTF._PRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRF
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Return(IRQB)
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} /* Method(_SB.INTF._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRF = Local0
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} /* End Method(_SB.INTF._SRS) */
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} /* End Device(INTF) */
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Device(INTG) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 7)
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Method(_STA, 0) {
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if (PIRG) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTG._STA) */
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Method(_DIS ,0) {
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PIRG = 0
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} /* End Method(_SB.INTG._DIS) */
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Method(_PRS ,0) {
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Return(IRQP)
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} /* Method(_SB.INTG._CRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRG
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Return(IRQB)
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} /* Method(_SB.INTG._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRG = Local0
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} /* End Method(_SB.INTG._SRS) */
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} /* End Device(INTG) */
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Device(INTH) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 8)
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Method(_STA, 0) {
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if (PIRH) {
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Return(0x0B) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTH._STA) */
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Method(_DIS ,0) {
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PIRH = 0
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} /* End Method(_SB.INTH._DIS) */
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Method(_PRS ,0) {
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Return(IRQP)
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} /* Method(_SB.INTH._CRS) */
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Method(_CRS ,0) {
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CreateWordField(IRQB, 0x1, IRQN)
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IRQN = 1 << PIRH
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Return(IRQB)
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} /* Method(_SB.INTH._CRS) */
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Method(_SRS, 1) {
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Local0--
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}
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PIRH = Local0
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} /* End Method(_SB.INTH._SRS) */
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} /* End Device(INTH) */
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} /* End Scope(_SB) */
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/* Contains the supported sleep states for this chipset */
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