drivers/mrc_cache: Always generate an FMAP region
This automatically generates an FMAP region for the MRC_CACHE driver which is easier to handle than a cbfsfile. Adds some spaces and more comments to Makefile.inc to improve readability. Tested on Thinkpad x200 with some proof of concept patches. Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Arthur Heymans
parent
1e931f3e47
commit
82aa8338c7
66
Makefile.inc
66
Makefile.inc
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@ -776,7 +776,11 @@ FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE))
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FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f)
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# position and size of flashmap, relative to BIOS_BASE
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FMAP_FMAP_BASE := 0
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FMAP_FMAP_SIZE := 0x100
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FMAP_FMAP_SIZE := 0x200
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#
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# X86 CONSOLE FMAP region
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#
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# position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled
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ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
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FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
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@ -787,8 +791,36 @@ FMAP_CONSOLE_BASE := 0
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FMAP_CONSOLE_SIZE := 0
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FMAP_CONSOLE_ENTRY :=
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endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
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#
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# X86 RW_MRC_CACHE FMAP region
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#
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# position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled
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ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
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FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
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$(FMAP_CONSOLE_SIZE)), 0x10000)
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else
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FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \
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$(FMAP_FMAP_SIZE)), 0x10000)
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endif
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FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
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FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
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else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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FMAP_MRC_CACHE_BASE := 0
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FMAP_MRC_CACHE_SIZE := 0
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FMAP_MRC_CACHE_ENTRY :=
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endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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#
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# X86 COREBOOT default cbfs FMAP region
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#
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# position and size of CBFS, relative to BIOS_BASE
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ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
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else
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FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE))
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endif
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FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
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else # ifeq ($(CONFIG_ARCH_X86),y)
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DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
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@ -802,6 +834,10 @@ FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
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# position and size of flashmap, relative to BIOS_BASE
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FMAP_FMAP_BASE := 0x20000
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FMAP_FMAP_SIZE := 0x100
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#
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# NON-X86 CONSOLE FMAP region
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#
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# position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled
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ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
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FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
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@ -812,8 +848,33 @@ FMAP_CONSOLE_BASE := 0
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FMAP_CONSOLE_SIZE := 0
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FMAP_CONSOLE_ENTRY :=
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endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
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#
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# NON-X86 RW_MRC_CACHE FMAP region
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#
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# position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled
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ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
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FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
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$(FMAP_CONSOLE_SIZE)), 0x10000)
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else
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FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \
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$(FMAP_FMAP_SIZE)), 0x10000)
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endif
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FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
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FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
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else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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FMAP_MRC_CACHE_BASE := 0
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FMAP_MRC_CACHE_SIZE := 0
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FMAP_MRC_CACHE_ENTRY :=
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endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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#
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# NON-X86 COREBOOT default cbfs FMAP region
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#
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# position and size of CBFS, relative to BIOS_BASE
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FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE) $(FMAP_CONSOLE_SIZE))
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FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE) $(FMAP_CONSOLE_SIZE) \
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$(FMAP_MRC_CACHE_SIZE))
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FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
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endif # ifeq ($(CONFIG_ARCH_X86),y)
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@ -825,6 +886,7 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
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-e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \
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-e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \
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-e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \
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-e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \
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-e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
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-e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
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$(DEFAULT_FLASHMAP) > $@.tmp
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@ -5,10 +5,6 @@ config CACHE_MRC_SETTINGS
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if CACHE_MRC_SETTINGS
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config MRC_SETTINGS_CACHE_BASE
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hex
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default 0xfffe0000
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config MRC_SETTINGS_CACHE_SIZE
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hex
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default 0x10000
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@ -1,19 +1,2 @@
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ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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romstage-y += mrc_cache.c
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ramstage-y += mrc_cache.c
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# Create and add the MRC cache to the cbfs image
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ifneq ($(CONFIG_CHROMEOS),y)
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$(obj)/mrc.cache: $(obj)/config.h
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dd if=/dev/zero count=1 \
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bs=$(shell printf "%d" $(CONFIG_MRC_SETTINGS_CACHE_SIZE) ) | \
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tr '\000' '\377' > $@
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cbfs-files-y += mrc.cache
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mrc.cache-file := $(obj)/mrc.cache
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mrc.cache-position := $(CONFIG_MRC_SETTINGS_CACHE_BASE)
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mrc.cache-type := mrc_cache
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endif # ifneq ($(CONFIG_CHROMEOS),y)
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endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
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romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
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ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
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@ -98,26 +98,9 @@ static const struct cache_region *cache_regions[] = {
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static int lookup_region_by_name(const char *name, struct region *r)
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{
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/* This assumes memory mapped boot media just under 4GiB. */
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const uint32_t pointer_base_32bit = -CONFIG_ROM_SIZE;
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if (fmap_locate_area(name, r) == 0)
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return 0;
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/* CHROMEOS builds must get their MRC cache from FMAP. */
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if (IS_ENABLED(CONFIG_CHROMEOS)) {
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printk(BIOS_ERR, "MRC: Chrome OS lookup failure.\n");
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return -1;
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}
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if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
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return -1;
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/* Base is in the form of a pointer. Make it an offset. */
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r->offset = CONFIG_MRC_SETTINGS_CACHE_BASE - pointer_base_32bit;
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r->size = CONFIG_MRC_SETTINGS_CACHE_SIZE;
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return 0;
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return -1;
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}
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static const struct cache_region *lookup_region_type(int type)
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@ -11,6 +11,7 @@ FLASH@##ROM_BASE## ##ROM_SIZE## {
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BIOS@##BIOS_BASE## ##BIOS_SIZE## {
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FMAP@##FMAP_BASE## ##FMAP_SIZE##
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##CONSOLE_ENTRY##
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##MRC_CACHE_ENTRY##
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COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
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}
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}
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@ -14,6 +14,7 @@ FLASH@##ROM_BASE## ##ROM_SIZE## {
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BOOTBLOCK 128K
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FMAP@##FMAP_BASE## ##FMAP_SIZE##
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##CONSOLE_ENTRY##
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##MRC_CACHE_ENTRY##
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COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
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}
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}
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