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soc/intel/cmn/block/acpi: Add new GPIO ASL Method 

Ths new Method, GSCI, allows control over whether or not IRQs are routed
as SCI#s for the given GPIO.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2022-08-16 14:43:03 -06:00 committed by Felix Held
parent a057d2cfd1
commit 7b42153e58
1 changed files with 19 additions and 0 deletions
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19
src/soc/intel/common/block/acpi/acpi/gpio_op.asl
View File

@ -117,3 +117,22 @@ Method (GRXE, 2, Serialized)
RXDI = !Arg1
}
/*
* Enable/Disable SCI interrupt route
* Arg0 - GPIO Number
* Arg1 - Route to SCI#
* 0 = Disable IRQ route to SCI#
* 1 = Enable IRQ route to SCI#
*/
Method (GSCI, 2, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
, 19,
SCIR, 1,
}
SCIR = Arg1
}