treewide: Replace CONFIG(ARCH_xx) tests
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -12,7 +12,7 @@
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#include <stdlib.h>
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#include <string.h>
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#include <smp/spinlock.h>
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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#include <arch/ebda.h>
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#endif
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#include <timer.h>
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@ -566,7 +566,7 @@ void dev_initialize(void)
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printk(BIOS_INFO, "Initializing devices...\n");
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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/* Ensure EBDA is prepared before Option ROMs. */
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setup_default_ebda();
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#endif
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@ -3,7 +3,7 @@
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#ifndef __OPROM_IO_H__
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#define __OPROM_IO_H__
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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#include <arch/io.h>
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#else
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void outb(u8 val, u16 port);
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@ -72,7 +72,7 @@ unsigned long tb_freq = 0;
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u64 get_time(void)
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{
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u64 act = 0;
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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u32 eax, edx;
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__asm__ __volatile__(
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@ -151,7 +151,7 @@ u8 biosemu_dev_translate_address(int type, unsigned long * addr);
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static inline void
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out32le(void *addr, u32 val)
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{
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#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
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#if ENV_X86 || ENV_ARM || ENV_ARM64
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*((u32*) addr) = cpu_to_le32(val);
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#else
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asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
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@ -162,7 +162,7 @@ static inline u32
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in32le(void *addr)
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{
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u32 val;
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#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
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#if ENV_X86 || ENV_ARM || ENV_ARM64
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val = cpu_to_le32(*((u32 *) addr));
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#else
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asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr));
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@ -173,7 +173,7 @@ in32le(void *addr)
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static inline void
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out16le(void *addr, u16 val)
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{
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#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
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#if ENV_X86 || ENV_ARM || ENV_ARM64
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*((u16*) addr) = cpu_to_le16(val);
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#else
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asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
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@ -184,7 +184,7 @@ static inline u16
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in16le(void *addr)
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{
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u16 val;
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#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
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#if ENV_X86 || ENV_ARM || ENV_ARM64
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val = cpu_to_le16(*((u16*) addr));
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#else
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asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));
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@ -748,7 +748,7 @@ static bool elog_do_add_boot_count(void)
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/* Check and log POST codes from previous boot */
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static void log_last_boot_post(void)
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{
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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u8 code;
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u32 extra;
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@ -145,7 +145,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header);
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* and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top()
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* value stored in nvram to enable early recovery on S3 path.
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*/
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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void backup_top_of_low_cacheable(uintptr_t ramtop);
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uintptr_t restore_top_of_low_cacheable(void);
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#endif
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@ -247,7 +247,7 @@
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(ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_ROMSTAGE || \
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(ENV_SEPARATE_VERSTAGE && !CONFIG(VBOOT_STARTS_IN_ROMSTAGE)))
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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/* Indicates memory layout is determined with arch/x86/car.ld. */
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#define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM))
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/* No .data sections with execute-in-place from ROM. */
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@ -63,7 +63,7 @@ DECLARE_REGION(bl31)
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* (Does not necessarily mean that the memory is accessible.) */
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static inline int preram_symbols_available(void)
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{
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return !CONFIG(ARCH_X86) || ENV_ROMSTAGE_OR_BEFORE;
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return !ENV_X86 || ENV_ROMSTAGE_OR_BEFORE;
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}
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#endif /* __SYMBOLS_H */
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@ -501,7 +501,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
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* another call to edid_set_framebuffer_bits_per_pixel(). As a cheap
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* heuristic, assume that X86 systems require a 64-byte row alignment
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* (since that seems to be true for most Intel chipsets). */
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if (CONFIG(ARCH_X86))
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if (ENV_X86)
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edid_set_framebuffer_bits_per_pixel(out, 32, 64);
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else
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edid_set_framebuffer_bits_per_pixel(out, 32, 0);
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@ -425,7 +425,7 @@ void main(void)
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/* TODO: Understand why this is here and move to arch/platform code. */
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/* For MMIO UART this needs to be called before any other printk. */
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if (CONFIG(ARCH_X86))
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if (ENV_X86)
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init_timer();
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/* console_init() MUST PRECEDE ALL printk()! Additionally, ensure
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@ -7,8 +7,13 @@
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* <lib.h> in case GCC does not have an assembly version for this arch.
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*/
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#if !CONFIG(ARCH_X86) /* work around lack of --gc-sections on x86 */ \
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&& !CONFIG(ARCH_RISCV_RV32) /* defined in rv32 libgcc.a */
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/*
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* FIXME
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* work around lack of --gc-sections on x86
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* defined in rv32 libgcc.a
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*/
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#if !ENV_X86 && !ENV_RISCV
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int __clzsi2(u32 a);
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int __clzsi2(u32 a)
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{
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@ -46,7 +46,7 @@ void run_romstage(void)
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vboot_run_logic();
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if (CONFIG(ARCH_X86) && CONFIG(BOOTBLOCK_NORMAL)) {
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if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) {
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if (legacy_romstage_selector(&romstage))
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goto fail;
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} else {
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* Only x86 systems using ramstage stage cache currently take the same
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* firmware path on resume.
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*/
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if (CONFIG(ARCH_X86) &&
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!CONFIG(NO_STAGE_CACHE))
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if (ENV_X86 && !CONFIG(NO_STAGE_CACHE))
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run_ramstage_from_resume(&ramstage);
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vboot_run_logic();
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@ -3,7 +3,7 @@
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#include <console/console.h>
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#include <device/mmio.h>
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#if CONFIG(ARCH_X86) && CONFIG(SSE2)
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#if ENV_X86 && CONFIG(SSE2)
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/* Assembler in lib/ is ugly. */
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static void write_phys(uintptr_t addr, u32 value)
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{
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@ -11,7 +11,7 @@
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#include <stdint.h>
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#include <reg_script.h>
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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#include <cpu/x86/msr.h>
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#endif
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@ -363,7 +363,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx)
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static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
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{
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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const struct reg_script *step = reg_script_get_step(ctx);
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msr_t msr = rdmsr(step->reg);
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uint64_t value = msr.hi;
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static void reg_script_write_msr(struct reg_script_context *ctx)
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{
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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const struct reg_script *step = reg_script_get_step(ctx);
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msr_t msr;
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msr.hi = step->value >> 32;
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@ -71,7 +71,7 @@ static int timestamp_should_run(void)
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* Only check boot_cpu() in other stages than
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* ENV_PAYLOAD_LOADER on x86.
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*/
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if ((!ENV_PAYLOAD_LOADER && CONFIG(ARCH_X86)) && !boot_cpu())
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if ((!ENV_PAYLOAD_LOADER && ENV_X86) && !boot_cpu())
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return 0;
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return 1;
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#if CONFIG(ARCH_X86)
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#if ENV_X86
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#include <cpu/x86/pae.h>
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#else
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#define memset_pae(a, b, c, d, e) 0
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cbmem_get_region(&baseptr, &size);
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memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE);
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if (CONFIG(ARCH_X86)) {
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if (ENV_X86) {
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/* Find space for PAE enabled memset */
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pgtbl = get_free_memory_range(&mem, MEMSET_PAE_PGTL_ALIGN,
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MEMSET_PAE_PGTL_SIZE);
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range_entry_size(r));
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}
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/* Use PAE if available */
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else if (CONFIG(ARCH_X86)) {
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else if (ENV_X86) {
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if (memset_pae(range_entry_base(r), 0,
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range_entry_size(r), (void *)pgtbl,
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(void *)vmem_addr))
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}
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}
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if (CONFIG(ARCH_X86)) {
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if (ENV_X86) {
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/* Clear previously skipped memory reserved for pagetables */
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printk(BIOS_DEBUG, "%s: Clearing DRAM %016lx-%016lx\n",
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__func__, pgtbl, pgtbl + MEMSET_PAE_PGTL_SIZE);
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