coreboot-mirror
/
coreboot
mirror of https://review.coreboot.org/coreboot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

mb/google/brya: Enable display and DSP audio UPD 

This patch includes changes to enable display and DSP audio UPD.

BUG=b:181219097,b:183482000
TEST=Audio sound card is detected and listed by the linux kernel.
Audio playback and capture is working on the Brya.

Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sugnan Prabhu S 2021-03-16 10:31:23 +05:30 committed by Tim Wawrzynczak
parent 50f8b4ebdd
commit 70299d9168
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/variants/baseboard/devicetree.cb
View File

@ -71,6 +71,12 @@ chip soc/intel/alderlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
register "PchHdaIDispCodecEnable" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |