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soc/mediatek: Fix USB enumeration issue 

Some USB 3.0 devices fail to be enumerated after USB reset, and xhci
port status register shows the device is disconnected. After measuring
the USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.

USB designers suggest changing discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu <changqi.hu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Changqi Hu 2019-08-23 12:01:30 +08:00 committed by Patrick Georgi
parent 1b439d9ced
commit 6b2a54030f
2 changed files with 6 additions and 0 deletions
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2
src/soc/mediatek/common/include/soc/usb_common.h
View File

@ -70,6 +70,8 @@ struct ssusb_ippc_regs {
#define PA6_RG_U2_ISO_EN (0x1 << 31)
#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)
#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)
#define PA6_RG_U2_DISCTH (0xf << 4)
#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4)
#define PA6_RG_U2_SQTH (0xf << 0)
#define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0)

4
src/soc/mediatek/common/usb.c
View File

@ -76,6 +76,10 @@ static void phy_index_power_on(int index)
/* Set USB 2.0 slew rate value */
clrsetbits_le32(&phy->u2phy.usbphyacr5,
PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
/* Set USB 2.0 disconnect threshold */
clrsetbits_le32(&phy->u2phy.usbphyacr6,
PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15));
}
static void u3phy_power_on(void)