soc/amd: introduce and use common IOAPIC IDs

Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.

Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/include/amdblocks/ioapic.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_IOAPIC_H
+#define AMD_BLOCK_IOAPIC_H
+
+#define FCH_IOAPIC_ID		CONFIG_MAX_CPUS
+#define GNB_IOAPIC_ID		(CONFIG_MAX_CPUS + 1)
+
+#endif /* AMD_BLOCK_IOAPIC_H */

src/soc/amd/common/block/smbus/sm.c

@@ -1,18 +1,18 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/ioapic.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include <device/smbus_host.h>
 #include <arch/ioapic.h>
-#include <soc/southbridge.h>
 
 static void sm_init(struct device *dev)
 {
 	fch_enable_ioapic_decode();
-	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
+	setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
 	fch_configure_hpet();
 }
 

src/soc/amd/picasso/Kconfig

@@ -238,24 +238,6 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
-config PICASSO_FCH_IOAPIC_ID
-	hex
-	default 0x8
-	help
-	  The Picasso APU has two IOAPICs, one in the FCH and one in the
-	  northbridge.  Set this value for the intended ID to assign to the
-	  FCH IOAPIC.  The value should be >= MAX_CPUS and different from
-	  the GNB's IOAPIC_ID.
-
-config PICASSO_GNB_IOAPIC_ID
-	hex
-	default 0x9
-	help
-	  The Picasso APU has two IOAPICs, one in the FCH and one in the
-	  northbridge.  Set this value for the intended ID to assign to the
-	  GNB IOAPIC.  The value should be >= MAX_CPUS and different from
-	  the FCH's IOAPIC_ID.
-
 config SERIRQ_CONTINUOUS_MODE
 	bool
 	default n

src/soc/amd/picasso/acpi.c

@@ -21,6 +21,7 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/chip.h>
 #include <amdblocks/cpu.h>
+#include <amdblocks/ioapic.h>
 #include <soc/acpi.h>
 #include <soc/pci_devs.h>
 #include <soc/msr.h>
@@ -36,10 +37,10 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current = acpi_create_madt_lapics(current);
 
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
-			CONFIG_PICASSO_FCH_IOAPIC_ID, IO_APIC_ADDR, 0);
+			FCH_IOAPIC_ID, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
-			CONFIG_PICASSO_GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS);
+			GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS);
 
 	/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */

src/soc/amd/picasso/agesa_acpi.c

@@ -13,6 +13,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <amdblocks/cpu.h>
+#include <amdblocks/ioapic.h>
 #include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <stdlib.h>
@@ -59,7 +60,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
 	ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS |
 				   IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS |
 				   IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS;
-	ivhd_ioapic->handle = CONFIG_PICASSO_FCH_IOAPIC_ID;
+	ivhd_ioapic->handle = FCH_IOAPIC_ID;
 	ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC);
 	ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
 	current += sizeof(ivrs_ivhd_special_t);
@@ -68,7 +69,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
 	memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic));
 
 	ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV;
-	ivhd_ioapic->handle = CONFIG_PICASSO_GNB_IOAPIC_ID;
+	ivhd_ioapic->handle = GNB_IOAPIC_ID;
 	ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1);
 	ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
 	current += sizeof(ivrs_ivhd_special_t);

src/soc/amd/picasso/fsp_params.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <assert.h>
+#include <amdblocks/ioapic.h>
 #include <device/pci.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -148,16 +149,9 @@ static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
 
 static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg)
 {
-	_Static_assert(CONFIG_PICASSO_GNB_IOAPIC_ID >= CONFIG_MAX_CPUS,
-			"PICASSO_GNB_IOAPIC_ID should be >= CONFIG_MAX_CPUS!\n");
-	_Static_assert(CONFIG_PICASSO_FCH_IOAPIC_ID >= CONFIG_MAX_CPUS,
-			"PICASSO_FCH_IOAPIC_ID should be >= CONFIG_MAX_CPUS!\n");
-	_Static_assert(CONFIG_PICASSO_GNB_IOAPIC_ID != CONFIG_PICASSO_FCH_IOAPIC_ID,
-			"PICASSO_GNB_IOAPIC_ID should be != PICASSO_FCH_IOAPIC_ID!\n");
-
 	scfg->gnb_ioapic_base = GNB_IO_APIC_ADDR;
-	scfg->gnb_ioapic_id = CONFIG_PICASSO_GNB_IOAPIC_ID;
-	scfg->fch_ioapic_id = CONFIG_PICASSO_FCH_IOAPIC_ID;
+	scfg->gnb_ioapic_id = GNB_IOAPIC_ID;
+	scfg->fch_ioapic_id = FCH_IOAPIC_ID;
 }
 
 static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,

src/soc/amd/picasso/root_complex.c

@@ -2,6 +2,7 @@
 
 #include <acpi/acpigen.h>
 #include <amdblocks/memmap.h>
+#include <amdblocks/ioapic.h>
 #include <arch/ioapic.h>
 #include <assert.h>
 #include <cbmem.h>
@@ -184,7 +185,7 @@ static void read_resources(struct device *dev)
 
 static void root_complex_init(struct device *dev)
 {
-	setup_ioapic((u8 *)GNB_IO_APIC_ADDR, CONFIG_PICASSO_GNB_IOAPIC_ID);
+	setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID);
 }
 
 static void dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size)

src/soc/amd/stoneyridge/acpi.c

@@ -16,6 +16,7 @@
 #include <device/pci.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/acpi.h>
+#include <amdblocks/ioapic.h>
 #include <soc/acpi.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
@@ -31,10 +32,10 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	/* Write Kern IOAPIC, only one */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
-			CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+			FCH_IOAPIC_ID, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
-			CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);
+			GNB_IOAPIC_ID, IO_APIC2_ADDR, 24);
 
 	/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */

src/soc/amd/stoneyridge/northbridge.c

@@ -18,6 +18,7 @@
 #include <device/pci_ids.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/agesawrapper_call.h>
+#include <amdblocks/ioapic.h>
 #include <agesa_headers.h>
 #include <soc/cpu.h>
 #include <soc/northbridge.h>
@@ -159,7 +160,7 @@ static void set_resources(struct device *dev)
 
 static void northbridge_init(struct device *dev)
 {
-	setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);
+	setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID);
 }
 
 static unsigned long acpi_fill_hest(acpi_hest_t *hest)