coreboot-mirror
/
coreboot
mirror of https://review.coreboot.org/coreboot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

sb/intel/i82801gx: Detect if the southbridge supports AHCI 

This automatically detects whether the southbridge supports AHCI.
If AHCI support is selected it will be used unless "sata_no_ahci" is
set in the devicetree to override the behavior.

Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-01-10 23:13:11 +01:00 committed by Patrick Georgi
parent fefe7afeb0
commit 5eb81bed2e
25 changed files with 49 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/apple/macbook21/devicetree.cb
View File

@ -64,7 +64,6 @@ chip northbridge/intel/i945
register "gpi1_routing" = "2"
register "gpi7_routing" = "2"
register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x04"
register "gpe0_en" = "0x11000006"

1
src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
View File

@ -51,7 +51,6 @@ chip northbridge/intel/x4x # Northbridge
register "gpi13_routing" = "2"
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440"

1
src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
View File

@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge
register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440"

1
src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
View File

@ -44,7 +44,6 @@ chip northbridge/intel/x4x # Northbridge
register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440"

1
src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
View File

@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge
register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "gpe0_en" = "0x440"
device pci 1b.0 on # Audio

1
src/mainboard/asus/p5gc-mx/devicetree.cb
View File

@ -53,7 +53,6 @@ chip northbridge/intel/i945
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
register "p_cnt_throttling_supported" = "0"

1
src/mainboard/asus/p5qpl-am/devicetree.cb
View File

@ -43,7 +43,6 @@ chip northbridge/intel/x4x # Northbridge
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "gpe0_en" = "0x04000440"
device pci 1b.0 on end # Audio

1
src/mainboard/foxconn/d41s/devicetree.cb
View File

@ -40,7 +40,6 @@ chip northbridge/intel/pineview # Northbridge
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x441"

1
src/mainboard/foxconn/g41s-k/devicetree.cb
View File

@ -47,7 +47,6 @@ chip northbridge/intel/x4x # Northbridge
register "ide_enable_primary" = "0x0"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0" # AHCI does not work
register "sata_ports_implemented" = "0x3"
device pci 1b.0 on end # Audio

1
src/mainboard/getac/p470/devicetree.cb
View File

@ -57,7 +57,6 @@ chip northbridge/intel/i945
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
register "c3_latency" = "85"
register "docking_supported" = "1"

1
src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
View File

@ -76,7 +76,6 @@ chip northbridge/intel/i945
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"

1
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
View File

@ -48,7 +48,6 @@ chip northbridge/intel/x4x # Northbridge
register "ide_legacy_combined" = "0x0" # Combined mode broken
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0" # AHCI does not work
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x40"

1
src/mainboard/ibase/mb899/devicetree.cb
View File

@ -36,7 +36,6 @@ chip northbridge/intel/i945
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x1"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"

1
src/mainboard/intel/d510mo/devicetree.cb
View File

@ -38,7 +38,6 @@ chip northbridge/intel/pineview # Northbridge
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x20000040"

1
src/mainboard/intel/d945gclf/devicetree.cb
View File

@ -50,7 +50,6 @@ chip northbridge/intel/i945
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"

1
src/mainboard/intel/dg41wv/devicetree.cb
View File

@ -63,7 +63,6 @@ chip northbridge/intel/x4x # Northbridge
register "gpi15_routing" = "2"
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "gpe0_en" = "0x440"
device pci 1b.0 on # Audio

1
src/mainboard/kontron/986lcd-m/devicetree.cb
View File

@ -36,7 +36,6 @@ chip northbridge/intel/i945
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x1"
register "sata_ahci" = "0x0"
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"

1
src/mainboard/lenovo/t60/devicetree.cb
View File

@ -72,7 +72,6 @@ chip northbridge/intel/i945
register "gpi12_routing" = "2"
register "gpi8_routing" = "2"
register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x01"
register "gpe0_en" = "0x11000006"

1
src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
View File

@ -44,7 +44,6 @@ chip northbridge/intel/x4x # Northbridge
register "gpi13_routing" = "1" # ??vendor
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "gpe0_en" = "0x440"
device pci 1b.0 on end # Audio

1
src/mainboard/lenovo/x60/devicetree.cb
View File

@ -65,7 +65,6 @@ chip northbridge/intel/i945
register "gpi12_routing" = "1"
register "gpi8_routing" = "2"
register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x01"
register "gpe0_en" = "0x11000006"

1
src/mainboard/lenovo/z61t/devicetree.cb
View File

@ -71,7 +71,6 @@ chip northbridge/intel/i945
register "gpi12_routing" = "2"
register "gpi8_routing" = "2"
register "sata_ahci" = "0x1"
register "sata_ports_implemented" = "0x01"
register "gpe0_en" = "0x11000006"

1
src/mainboard/roda/rk886ex/devicetree.cb
View File

@ -61,7 +61,6 @@ chip northbridge/intel/i945
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 on end # PCIe port 1

8
src/southbridge/intel/i82801gx/chip.h
View File

@ -18,6 +18,12 @@
#include <stdint.h>
enum sata_mode {
SATA_MODE_AHCI = 0,
SATA_MODE_IDE_LEGACY_COMBINED,
SATA_MODE_IDE_PLAIN,
};
struct southbridge_intel_i82801gx_config {
/**
* Interrupt Routing configuration
@ -65,7 +71,7 @@ struct southbridge_intel_i82801gx_config {
uint32_t ide_legacy_combined;
uint32_t ide_enable_primary;
uint32_t ide_enable_secondary;
uint32_t sata_ahci;
enum sata_mode sata_mode;
uint32_t sata_ports_implemented;
/* Enable linear PCIe Root Port function numbers starting at zero */

1
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -82,6 +82,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
#define FDVCT 0xe4
#define PCIE_4_PORTS_MAX (1 << 7)
#define AHCI_UNSUPPORTED (1 << 3)
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)

53
src/southbridge/intel/i82801gx/sata.c
View File

@ -51,18 +51,42 @@ static u8 get_ich7_sata_ports(void)
void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
struct southbridge_intel_i82801gx_config *config = dev->chip_info;
if (config->sata_mode == SATA_MODE_AHCI) {
/* Check if the southbridge supports AHCI */
struct device *lpc_dev = pcidev_on_root(31, 0);
if (!lpc_dev) {
/* According to the PCI spec function 0 on a bus:device
needs to be active for other functions to be enabled.
Since SATA is on the same bus:device as the LPC
bridge, it makes little sense to continue. */
die("Couldn't find the LPC device!\n");
}
const bool ahci_supported = !(pci_read_config32(lpc_dev, FDVCT)
& AHCI_UNSUPPORTED);
if (!ahci_supported) {
/* Fallback to IDE PLAIN for sata for the rest of the
initialization */
config->sata_mode = SATA_MODE_IDE_PLAIN;
printk(BIOS_DEBUG,
"AHCI not supported, falling back to plain mode.\n");
}
if (config->sata_ahci) {
/* Set map to ahci */
pci_write_config8(dev, SATA_MAP,
(pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40);
} else {
/* Set map to ide */
pci_write_config8(dev, SATA_MAP,
pci_read_config8(dev, SATA_MAP) & ~0xc3);
}
if (config->sata_mode == SATA_MODE_AHCI) {
/* Set map to ahci */
pci_write_config8(dev, SATA_MAP,
(pci_read_config8(dev, SATA_MAP)
& ~0xc3) | 0x40);
} else {
/* Set map to ide */
pci_write_config8(dev, SATA_MAP,
pci_read_config8(dev, SATA_MAP) & ~0xc3);
}
/* At this point, the new pci id will appear on the bus */
}
@ -89,7 +113,8 @@ static void sata_init(struct device *dev)
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
if (config->ide_legacy_combined) {
switch (config->sata_mode) {
case SATA_MODE_IDE_LEGACY_COMBINED:
printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
/* No AHCI: clear AHCI base */
pci_write_config32(dev, 0x24, 0x00000000);
@ -120,7 +145,8 @@ static void sata_init(struct device *dev)
/* Restrict ports - 0 and 2 only available */
ports &= 0x5;
} else if (config->sata_ahci) {
break;
case SATA_MODE_AHCI:
printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
/* Allow both Legacy and Native mode */
pci_write_config8(dev, 0x09, 0x8f);
@ -131,7 +157,9 @@ static void sata_init(struct device *dev)
ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
ahci_bar[3] = config->sata_ports_implemented;
} else {
break;
default:
case SATA_MODE_IDE_PLAIN:
printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
/* Set Sata Controller Mode. No Mapping(?) */
pci_write_config8(dev, SATA_MAP, 0x00);
@ -168,6 +196,7 @@ static void sata_init(struct device *dev)
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
break;
}
/* Set port control */