soc/amd/picasso: Remove I2C4

Remove I2C4 since it is a slave device used for USB-C mux control
and should not be included with the other master devices.

BUG=b:160624619 b:160292546
TEST=EC can communicate with AP mux I2C4 slave

Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward Hill 2020-07-07 17:34:00 -06:00 committed by Martin Roth
parent 037ee4b556
commit 56b2550316
3 changed files with 2 additions and 48 deletions

View File

@ -139,7 +139,6 @@ Device (AOAC) {
AOAC_DEVICE(I2C2, 7, 0)
AOAC_DEVICE(I2C3, 8, 0)
AOAC_DEVICE(I2C4, 9, 5) /* I2C4 is powered from the S5 power group. */
AOAC_DEVICE(FUR1, 12, 0)
AOAC_DEVICE(FUR2, 16, 0)
AOAC_DEVICE(FUR3, 26, 0)

View File

@ -345,52 +345,6 @@ Device (I2C3)
}
}
Device (I2C4) {
Name (_HID, "AMD0010")
Name (_UID, 0x4)
Method (_CRS, 0) {
Local0 = ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
}
CreateDWordField (Local0, IRQR._INT, IRQN)
If (PMOD) {
IRQN = II24
} Else {
IRQN = PI24
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
})
} Else {
Return (Local0)
}
}
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
}
Name (_PR0, Package () { \_SB.AOAC.I2C4 })
Name (_PR2, Package () { \_SB.AOAC.I2C4 })
Name (_PR3, Package () { \_SB.AOAC.I2C4 })
Method (_PS0, 0, Serialized) {
Printf("I2C4._PS0")
\_SB.AOAC.I2C4.TDS = 1
}
Method (_PS3, 0, Serialized) {
Printf("I2C4._PS3")
\_SB.AOAC.I2C4.TDS = 3
}
}
Device (MISC)
{
Name (_HID, "AMD0040")

View File

@ -39,7 +39,8 @@
/* I2C parameters for lpc_read_resources */
#define I2C_BASE_ADDRESS APU_I2C2_BASE
#define I2C_DEVICE_SIZE 0x00001000
#define I2C_DEVICE_COUNT 3
#define I2C_DEVICE_COUNT (I2C_MASTER_DEV_COUNT \
- I2C_MASTER_START_INDEX)
#define APU_DMAC0_BASE 0xfedc7000
#define APU_DMAC1_BASE 0xfedc8000