diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 39453d9806f3..cf9861f63a63 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -171,12 +171,9 @@ chip soc/intel/alderlake
 
 	# HD Audio
 	register "PchHdaDspEnable" = "1"
-	# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
-	register "PchHdaIDispLinkTmode" = "2"
-	# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
-	register "PchHdaIDispLinkFrequency" = "4"
-	# Not disconnected/enumerable
-	register "PchHdaIDispCodecDisconnect" = "0"
+	register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T"
+	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
+	register "PchHdaIDispCodecEnable" = "1"
 
 	register "CnviBtAudioOffload" = "true"
 
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 30aee7a7fcbf..1e618dd1d841 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -121,12 +121,9 @@ chip soc/intel/alderlake
 
 	# HD Audio
 	register "PchHdaDspEnable" = "1"
-	# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
-	register "PchHdaIDispLinkTmode" = "3"
-	# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
-	register "PchHdaIDispLinkFrequency" = "4"
-	# Not disconnected/enumerable
-	register "PchHdaIDispCodecDisconnect" = "0"
+	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
+	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
+	register "PchHdaIDispCodecEnable" = "1"
 
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index b06e540b84e7..f96844cd46c6 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -111,12 +111,9 @@ chip soc/intel/alderlake
 
 	# HD Audio
 	register "PchHdaDspEnable" = "1"
-	# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
-	register "PchHdaIDispLinkTmode" = "3"
-	# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
-	register "PchHdaIDispLinkFrequency" = "4"
-	# Not disconnected/enumerable
-	register "PchHdaIDispCodecDisconnect" = "0"
+	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
+	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
+	register "PchHdaIDispCodecEnable" = "1"
 
 	# DP port
 	register "DdiPortAConfig" = "1"	# eDP
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index e0d0b6074fee..201150e8fcd3 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -113,9 +113,22 @@ struct soc_intel_alderlake_config {
 
 	/* Audio related */
 	uint8_t PchHdaDspEnable;
-	uint8_t PchHdaIDispLinkTmode;
-	uint8_t PchHdaIDispLinkFrequency;
-	uint8_t PchHdaIDispCodecDisconnect;
+
+	/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
+	enum {
+		HDA_TMODE_2T = 0,
+		HDA_TMODE_4T = 2,
+		HDA_TMODE_8T = 3,
+		HDA_TMODE_16T = 4,
+	} PchHdaIDispLinkTmode;
+
+	/* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
+	enum {
+		HDA_LINKFREQ_48MHZ = 3,
+		HDA_LINKFREQ_96MHZ = 4,
+	} PchHdaIDispLinkFrequency;
+
+	bool PchHdaIDispCodecEnable;
 
 	struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
 	struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 74d127ea9860..9901354190e0 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -143,7 +143,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
 	m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
 	m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
-	m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
+	m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
 
 	/* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
 	for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {