drivers/intel/fsp1_1,fsp2_0: Refactor logo display

Hide the detail of allocation from cbmem from the FSP.

Loading of a BMP logo file from CBFS is not tied to FSP
version and we do not need two copies of the code, move
it under lib/.

Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/drivers/intel/fsp1_1/Kconfig

@@ -78,7 +78,7 @@ config SKIP_FSP_CAR
 	help
 	  Selected by platforms that implement their own CAR setup.
 
-config FSP1_1_DISPLAY_LOGO
+config BMP_LOGO
 	bool "Enable logo"
 	default n
 	help
@@ -87,7 +87,7 @@ config FSP1_1_DISPLAY_LOGO
 
 config FSP1_1_LOGO_FILE_NAME
 	string "Logo file"
-	depends on FSP1_1_DISPLAY_LOGO
+	depends on BMP_LOGO
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
 
 endif #PLATFORM_USES_FSP1_1

src/drivers/intel/fsp1_1/Makefile.inc

@@ -21,7 +21,6 @@ romstage-$(CONFIG_MMA) += mma_core.c
 ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
-ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c
 ramstage-$(CONFIG_MMA) += mma_core.c
@@ -44,7 +43,7 @@ fsp.bin-COREBOOT-position := $(CONFIG_FSP_LOC)
 endif
 
 # Add logo to the cbfs image
-cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp
+cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
 logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME))
 logo.bmp-type := raw
 logo.bmp-compression := LZMA

src/drivers/intel/fsp1_1/include/fsp/ramstage.h

@@ -9,7 +9,6 @@
 /* Perform Intel silicon init. */
 void intel_silicon_init(void);
 void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
-const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size);
 /* Called after the silicon init code has run. */
 void soc_after_silicon_init(void);
 /* Initialize UPD data before SiliconInit call. */
@@ -17,7 +16,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params);
 void mainboard_silicon_init_params(SILICON_INIT_UPD *params);
 void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	SILICON_INIT_UPD *new);
-const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params);
 void load_vbt(SILICON_INIT_UPD *params);
 
 #endif /* _INTEL_COMMON_RAMSTAGE_H_ */

src/drivers/intel/fsp1_1/logo.c

@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cbfs.h>
-#include <cbmem.h>
-#include <soc/ramstage.h>
-
-const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size)
-{
-	const struct cbmem_entry *logo_entry = NULL;
-	void *logo_buffer;
-
-	logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB);
-	if (logo_entry) {
-		logo_buffer = cbmem_entry_start(logo_entry);
-		if (logo_buffer) {
-			*logo_size = cbfs_load("logo.bmp", (void *)logo_buffer,
-						1 * MiB);
-			if (*logo_size)
-				*logo_ptr = (UINT32)logo_buffer;
-		}
-	}
-	return (logo_entry);
-}

src/drivers/intel/fsp1_1/ramstage.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootmode.h>
+#include <bootsplash.h>
 #include <acpi/acpi.h>
 #include <console/console.h>
 #include <fsp/ramstage.h>
@@ -58,7 +59,6 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 	EFI_STATUS status;
 	UPD_DATA_REGION *upd_ptr;
 	VPD_DATA_REGION *vpd_ptr;
-	const struct cbmem_entry *logo_entry = NULL;
 
 	/* Display the FSP header */
 	if (fsp_info_header == NULL) {
@@ -85,8 +85,9 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 		load_vbt(&silicon_init_params);
 	mainboard_silicon_init_params(&silicon_init_params);
 
-	if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup)
-		logo_entry = soc_load_logo(&silicon_init_params);
+	if (CONFIG(BMP_LOGO))
+		bmp_load_logo(&silicon_init_params.PcdLogoPtr,
+			      &silicon_init_params.PcdLogoSize);
 
 	/* Display the UPD data */
 	if (CONFIG(DISPLAY_UPD_DATA))
@@ -106,8 +107,8 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 	printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
 
 	/* The logo_entry can be freed up now as it is not required any longer */
-	if (logo_entry && !is_s3_wakeup)
-		cbmem_entry_remove(logo_entry);
+	if (CONFIG(BMP_LOGO))
+		bmp_release_logo();
 
 	/* Mark graphics init done after SiliconInit if VBT was provided */
 #if CONFIG(RUN_FSP_GOP)

src/drivers/intel/fsp2_0/Kconfig

@@ -184,7 +184,7 @@ config HAVE_FSP_LOGO_SUPPORT
 	bool
 	default n
 
-config FSP2_0_DISPLAY_LOGO
+config BMP_LOGO
 	bool "Enable logo"
 	default n
 	depends on HAVE_FSP_LOGO_SUPPORT
@@ -195,7 +195,7 @@ config FSP2_0_DISPLAY_LOGO
 
 config FSP2_0_LOGO_FILE_NAME
 	string "Logo file"
-	depends on FSP2_0_DISPLAY_LOGO
+	depends on BMP_LOGO
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
 
 config FSP_COMPRESS_FSP_S_LZMA

src/drivers/intel/fsp2_0/Makefile.inc

@@ -22,7 +22,6 @@ ramstage-y += hand_off_block.c
 ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
-ramstage-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.c
 ramstage-y += notify.c
 ramstage-y += silicon_init.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
@@ -86,7 +85,7 @@ $(obj)/Fsp_T.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd
 endif
 
 # Add logo to the cbfs image
-cbfs-files-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.bmp
+cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
 logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME))
 logo.bmp-type := raw
 logo.bmp-compression := LZMA

src/drivers/intel/fsp2_0/include/fsp/api.h

@@ -59,16 +59,13 @@ int soc_fsp_multi_phase_init_is_enable(void);
 uint8_t fsp_memory_mainboard_version(void);
 uint8_t fsp_memory_soc_version(void);
 
-/* Load logo to be displayed by FSP */
-const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size);
-
 /* Callback after processing FSP notify */
 void platform_fsp_notify_status(enum fsp_notify_phase phase);
 
 /* Initialize memory margin analysis settings. */
 void setup_mma(FSP_M_CONFIG *memory_cfg);
 /* Update the SOC specific logo param and load the logo. */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd);
+void soc_load_logo(FSPS_UPD *supd);
 /* Update the SOC specific memory config param for mma. */
 void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
 	struct mma_config_param *mma_cfg);

src/drivers/intel/fsp2_0/logo.c

@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cbfs.h>
-#include <cbmem.h>
-#include <fsp/api.h>
-
-const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size)
-{
-	const struct cbmem_entry *logo_entry = NULL;
-	void *logo_buffer;
-
-	logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB);
-	if (logo_entry) {
-		logo_buffer = cbmem_entry_start(logo_entry);
-		if (logo_buffer) {
-			*logo_size = cbfs_load("logo.bmp", (void *)logo_buffer,
-						1 * MiB);
-			if (*logo_size)
-				*logo_ptr = (UINT32)logo_buffer;
-		}
-	}
-	return (logo_entry);
-}

src/drivers/intel/fsp2_0/silicon_init.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <bootsplash.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <commonlib/fsp.h>
@@ -81,7 +82,6 @@ static void do_silicon_init(struct fsp_header *hdr)
 	FSPS_UPD *upd, *supd;
 	fsp_silicon_init_fn silicon_init;
 	uint32_t status;
-	const struct cbmem_entry *logo_entry = NULL;
 	fsp_multi_phase_si_init_fn multi_phase_si_init;
 	struct fsp_multi_phase_params multi_phase_params;
 	struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
@@ -106,8 +106,8 @@ static void do_silicon_init(struct fsp_header *hdr)
 	platform_fsp_silicon_init_params_cb(upd);
 
 	/* Populate logo related entries */
-	if (CONFIG(FSP2_0_DISPLAY_LOGO))
-		logo_entry = soc_load_logo(upd);
+	if (CONFIG(BMP_LOGO))
+		soc_load_logo(upd);
 
 	/* Call SiliconInit */
 	silicon_init = (void *) (uintptr_t)(hdr->image_base +
@@ -127,8 +127,8 @@ static void do_silicon_init(struct fsp_header *hdr)
 	timestamp_add_now(TS_FSP_SILICON_INIT_END);
 	post_code(POST_FSP_SILICON_EXIT);
 
-	if (logo_entry)
-		cbmem_entry_remove(logo_entry);
+	if (CONFIG(BMP_LOGO))
+		bmp_release_logo();
 
 	fsp_debug_after_silicon_init(status);
 	fsps_return_value_handler(FSP_SILICON_INIT_API, status);
@@ -226,8 +226,4 @@ void fsp_silicon_init(bool s3wake)
 	do_silicon_init(&fsps_hdr);
 }
 
-/* Load bmp and set FSP parameters, fsp_load_logo can be used */
-__weak const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
-{
-	return NULL;
-}
+__weak void soc_load_logo(FSPS_UPD *supd) { }

src/include/bootsplash.h

@@ -14,4 +14,8 @@
 void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution,
 		    unsigned int y_resolution, unsigned int fb_resolution);
 
+
+void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size);
+void bmp_release_logo(void);
+
 #endif

src/lib/Makefile.inc

@@ -139,6 +139,7 @@ ramstage-y += stack.c
 ramstage-y += hexstrtobin.c
 ramstage-y += wrdd.c
 ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
+ramstage-$(CONFIG_BMP_LOGO) += bmp_logo.c
 ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c

src/lib/bmp_logo.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <bootsplash.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <stdint.h>
+
+static const struct cbmem_entry *logo_entry;
+
+void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size)
+{
+	void *logo_buffer;
+
+	/* CBMEM is locked for S3 resume path. */
+	if (acpi_is_wakeup_s3())
+		return;
+
+	logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB);
+	if (!logo_entry)
+		return;
+
+	logo_buffer = cbmem_entry_start(logo_entry);
+	if (!logo_buffer)
+		return;
+
+	*logo_size = cbfs_load("logo.bmp", logo_buffer, 1 * MiB);
+	if (*logo_size)
+		*logo_ptr = (uintptr_t)logo_buffer;
+}
+
+void bmp_release_logo(void)
+{
+	if (logo_entry)
+		cbmem_entry_remove(logo_entry);
+	logo_entry = NULL;
+}

src/mainboard/facebook/fbg1701/board_verified_boot.c

@@ -57,7 +57,7 @@ const verify_item_t postcar_verify_list[] = {
 static const verify_item_t ram_stage_additional_list[] = {
 	{ VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } },
 		HASH_IDX_OPROM, MBOOT_PCR_INDEX_2 },
-#if CONFIG(FSP1_1_DISPLAY_LOGO)
+#if CONFIG(BMP_LOGO)
 	{ VERIFY_FILE, "logo.bmp", { { NULL, CBFS_TYPE_RAW } },
 		HASH_IDX_LOGO, MBOOT_PCR_INDEX_2 },
 #endif

src/soc/intel/apollolake/chip.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpi.h>
+#include <bootsplash.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -850,9 +851,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
 }
 
 /* Handle FSP logo params */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo(FSPS_UPD *supd)
 {
-	return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+	bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
 }
 
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);

src/soc/intel/braswell/chip.c

@@ -136,11 +136,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	board_silicon_USB2_override(params);
 }
 
-const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params)
-{
-	return fsp_load_logo(&params->PcdLogoPtr, &params->PcdLogoSize);
-}
-
 void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
 {
 	/* Display the parameters for SiliconInit */

src/soc/intel/cannonlake/fsp_params.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootsplash.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -589,7 +590,7 @@ const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
 }
 
 /* Handle FSP logo params */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo(FSPS_UPD *supd)
 {
-	return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+	bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
 }

src/soc/intel/skylake/chip.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <bootsplash.h>
 #include <cbmem.h>
 #include <fsp/api.h>
 #include <acpi/acpi.h>
@@ -443,7 +444,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 }
 
 /* Handle FSP logo params */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+void soc_load_logo(FSPS_UPD *supd)
 {
-	return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+	bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
 }