mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Michał Żygowski
Patrick Georgi
parent
dcd3d072d4
commit
48be6b276a
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@ -120,6 +120,7 @@ The boards in this section are not real mainboards, but emulators.
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## Protectli
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- [FW2B / FW4B](protectli/fw2b_fw4b.md)
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- [FW6A / FW6B / FW6C](protectli/fw6.md)
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## Roda
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Binary file not shown.
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After Width: | Height: | Size: 49 KiB |
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@ -0,0 +1,137 @@
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# Protectli Vault FW6 series
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This page describes how to run coreboot on the [Protectli FW6].
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## Required proprietary blobs
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To build a minimal working coreboot image some blobs are required (assuming
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only the BIOS region is being modified).
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```eval_rst
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+-----------------+---------------------------------+---------------------+
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| Binary file | Apply | Required / Optional |
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+=================+=================================+=====================+
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| FSP-M, FSP-S | Intel Firmware Support Package | Required |
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+-----------------+---------------------------------+---------------------+
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| microcode | CPU microcode | Required |
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+-----------------+---------------------------------+---------------------+
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| vgabios | VGA Option ROM | Optional |
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+-----------------+---------------------------------+---------------------+
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```
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FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done
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automatically by the coreboot build system and included into the image) from
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the `3rdparty/fsp` submodule.
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Microcode updates are automatically included into the coreboot image by build
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system from the `3rdparty/intel-microcode` submodule.
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VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
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stage, it should be included (if not using libgfxinit).
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. The first version
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supporting the chipset is flashrom v1.1. Firmware an be easily flashed
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with internal programmer (either BIOS region or full image).
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### External programming
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The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
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This chip is located on the bottom side of the case (the radiator side). One
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has to remove all screws (in order): 4 top cover screws, 4 side cover screws
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(one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up
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the mainboard and turn around it. The flash chip is near the SoC on the DIMM
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slots side. Use a clip (or solder the wires) to program the chip. Specifically,
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it's a Macronix MX25L6406E (3.3V) -[datasheet][MX25L6406E].
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## Known issues
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- After flashing with external programmer it is always required to reset RTC
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with jumper or disconnect coin cell temporarily. Only then the platform will
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boot after flashing.
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- FW6A does not always work reliably with all DIMMs. Linux happens to hang or
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gives many panics. This issue was present also with vendor BIOS.
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- Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs
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connected). A workaround is to power cycle the board (even a few times) or
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temporarily disconnect DIMM when platform is powered off.
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- When using libgfxinit and SeaBIOS bootsplash, the red color is dim
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## Untested
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Not all mainboard's peripherals and functions were tested because of lack of
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the cables or not being populated on the board case.
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- Internal USB 2.0 headers
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- Boot with cleaned ME
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## Working
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- USB 3.0 front ports (SeaBIOS and Linux)
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- 6 Ethernet ports
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- HDMI port with libgfxinit and VGA Option ROM
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- flashrom
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- PCIe WiFi
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- SATA and mSATA
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- Super I/O serial port 0 (RS232 via front RJ45 connector)
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- SMBus (reading SPD from DIMMs)
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- Initialization with KBL FSP 2.0 (with MemoryInit issues)
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- SeaBIOS payload (version rel-1.12.1)
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- Mini PCIe debug card connected to mSATA (mSATA slot has LPC signals routed)
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- Reset switch
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- Booting Debian, Ubuntu, FreeBSD
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## Technology
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There are 3 variants of FW6 boards: FW6A, FW6B and FW6C. They differ only in
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used SoC.
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- FW6A:
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Celeron 3865U |
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+------------------+--------------------------------------------------+
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| PCH | Kaby Lake U w/ iHDCP2.2 Base |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8772E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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- FW6B:
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Core i3-7100U |
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+------------------+--------------------------------------------------+
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| PCH | Kaby Lake U w/ iHDCP2.2 Premium |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8772E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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- FW6C:
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Core i5-7200U |
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+------------------+--------------------------------------------------+
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| PCH | Kaby Lake U w/ iHDCP2.2 Premium |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8772E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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[Protectli FW6]: https://protectli.com/vault-6-port/
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[MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,%2064Mb,%20v1.9.pdf
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[flashrom]: https://flashrom.org/Flashrom
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@ -10,7 +10,6 @@ endchoice
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source "src/mainboard/protectli/*/Kconfig"
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config MAINBOARD_VENDOR
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string "Mainboard Vendor"
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default "Protectli"
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endif # VENDOR_PROTECTLI
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@ -0,0 +1,59 @@
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if BOARD_PROTECTLI_FW6
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_LIBGFXINIT
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select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
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select SOC_INTEL_KABYLAKE
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select SPI_FLASH_MACRONIX
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select SUPERIO_ITE_IT8772F
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAINBOARD_DIR
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string
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default "protectli/vault_kbl"
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config MAINBOARD_PART_NUMBER
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string
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default "FW6"
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config MAX_CPUS
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int
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default 4
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config VGA_BIOS_ID
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string
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default "8086,5916" # 8086,5906 for FW6A
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config PXE_ROM_ID
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string
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default "8086,150c"
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config CBFS_SIZE
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hex
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default 0x600000
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config ADD_FSP_BINARIES
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bool
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default y
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config FSP_USE_REPO
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bool
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default y
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endif
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@ -0,0 +1,2 @@
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config BOARD_PROTECTLI_FW6
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bool "FW6"
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@ -0,0 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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## This file is part of the coreboot project.
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bootblock-y += bootblock.c
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ramstage-y += ramstage.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -0,0 +1,6 @@
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Vendor name: Protectli
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Board name: FW6A/FW6B/FW6C
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Category: sbc
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* This file is part of the coreboot project. */
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#include <bootblock_common.h>
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#include <superio/ite/it8772f/it8772f.h>
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#include <superio/ite/common/ite.h>
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#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
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#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1)
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void bootblock_mainboard_early_init(void)
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{
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ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
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ite_enable_3vsbsw(GPIO_DEV);
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ite_kill_watchdog(GPIO_DEV);
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ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
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}
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Binary file not shown.
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@ -0,0 +1,309 @@
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
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register "s0ix_enable" = "1"
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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register "gen1_dec" = "0x00fc0201"
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register "gen2_dec" = "0x007c0a01"
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register "gen3_dec" = "0x000c03e1"
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register "gen4_dec" = "0x001c02e1"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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register "eist_enable" = "1"
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# Disable DPTF
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register "dptf_enable" = "0"
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# Enable VT-d
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register "ignore_vtd" = "0"
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# Enable SERIRQ continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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register "tcc_offset" = "5" # TCC of 95C
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "1"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPwrOptEnable" = "1"
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register "EnableAzalia" = "0"
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register "DspEnable" = "0"
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register "IoBufferOwnership" = "0"
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register "EnableTraceHub" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "0"
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register "HeciEnabled" = "1"
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register "PmTimerDisabled" = "1"
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register "SaGv" = "SaGv_Enabled"
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register "SaImguEnable" = "0"
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register "IslVrCmd" = "2"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "4" # 4s
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------+-------+
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#| Domain/Setting | SA | IA | GTUS | GTS |
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#+----------------+-------+-------+-------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
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#| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
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#+----------------+-------+-------+-------+-------+
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#Note: IccMax settings are moved to SoC code
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Enable SATA ports 1,2
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "0"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "0"
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# Enable Root ports. 1-6 for LAN and Root Port 9
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[1]" = "1"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[5]" = "1"
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register "PcieRpEnable[8]" = "1" # mPCIe WiFi
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# Enable Advanced Error Reporting for RP 1-6, 9
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register "PcieRpAdvancedErrorReporting[0]" = "1"
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register "PcieRpAdvancedErrorReporting[1]" = "1"
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register "PcieRpAdvancedErrorReporting[2]" = "1"
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register "PcieRpAdvancedErrorReporting[3]" = "1"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpAdvancedErrorReporting[8]" = "1"
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# Enable Latency Tolerance Reporting Mechanism RP 1-6, 9
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register "PcieRpLtrEnable[0]" = "1"
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register "PcieRpLtrEnable[1]" = "1"
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register "PcieRpLtrEnable[2]" = "1"
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register "PcieRpLtrEnable[3]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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# Enable RP 9 CLKREQ# support
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register "PcieRpClkReqSupport[8]" = "1"
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# RP 9 uses CLKREQ0#
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register "PcieRpClkReqNumber[8]" = "0"
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# Clocks 0-5 for RP 1-6
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register "PcieRpClkSrcNumber[0]" = "0"
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register "PcieRpClkSrcNumber[1]" = "1"
|
||||
register "PcieRpClkSrcNumber[2]" = "2"
|
||||
register "PcieRpClkSrcNumber[3]" = "3"
|
||||
register "PcieRpClkSrcNumber[4]" = "4"
|
||||
register "PcieRpClkSrcNumber[5]" = "5"
|
||||
# RP 9 shares CLKSRC5# with RP 6
|
||||
register "PcieRpClkSrcNumber[8]" = "5"
|
||||
|
||||
|
||||
# USB 2.0 enable ports 1-8, disable ports 9-12
|
||||
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port
|
||||
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled
|
||||
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled
|
||||
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled
|
||||
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled
|
||||
|
||||
# USB 3.0 enable ports 1-4, disable ports 5-6
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
|
||||
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
|
||||
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
|
||||
|
||||
register "SerialIoDevMode" = "{ \
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
|
||||
}"
|
||||
|
||||
# Lock Down CHIPSET_LOCKDOWN_COREBOOT
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 08.0 off end # Gaussian Mixture Model
|
||||
device pci 13.0 off end # Integrated Sensor Hub
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 off end # Thermal Subsystem
|
||||
device pci 14.3 off end # Camera I/O Host Controller
|
||||
device pci 15.0 off end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 off end # UART #2
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 off end # I2C #4
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 on end # PCI Express Port 2
|
||||
device pci 1c.2 on end # PCI Express Port 3
|
||||
device pci 1c.3 on end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 on end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on # PCI Express Port 9 - WiFi
|
||||
smbios_slot_desc
|
||||
"SlotTypePciExpressMini52pinWithoutBSKO"
|
||||
"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
|
||||
end
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1e.4 off end # eMMC
|
||||
device pci 1e.5 off end # SDIO
|
||||
device pci 1e.6 off end # SDCard
|
||||
device pci 1f.0 on
|
||||
chip superio/ite/it8772f
|
||||
register "peci_tmpin" = "3"
|
||||
register "tmpin1_mode" = "THERMAL_RESISTOR"
|
||||
register "tmpin2_mode" = "THERMAL_RESISTOR"
|
||||
# FAN2 available on fan header but unused
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 on # Serial Port 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 on # Environment Controller
|
||||
io 0x60 = 0xa40
|
||||
io 0x62 = 0xa30
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.5 off end # Keyboard
|
||||
device pnp 2e.6 off end # Mouse
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.a off end # IR
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 off end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 off end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* This file is part of the coreboot project. */
|
||||
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, /* DSDT revision: ACPI v2.0 and up */
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 /* OEM revision */
|
||||
)
|
||||
{
|
||||
#include <soc/intel/skylake/acpi/platform.asl>
|
||||
#include <soc/intel/skylake/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <soc/intel/skylake/acpi/systemagent.asl>
|
||||
#include <soc/intel/skylake/acpi/pch.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
-- This file is part of the coreboot project.
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* This file is part of the coreboot project. */
|
||||
|
||||
#ifndef _GPIOFW6B_H
|
||||
#define _GPIOFW6B_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
|
||||
/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
|
||||
/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
|
||||
/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
|
||||
/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP),
|
||||
/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
|
||||
/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
|
||||
/* PME# */ PAD_CFG_NF(GPP_A11, 20K_PU, DEEP, NF1),
|
||||
/* ISH_GP6 */ PAD_NC(GPP_A12, NONE),
|
||||
/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
|
||||
/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
|
||||
/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE),
|
||||
/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
|
||||
/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
|
||||
/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
|
||||
/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
|
||||
/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
|
||||
/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
|
||||
/* CORE_VID0 */ PAD_NC(GPP_B0, NONE),
|
||||
/* CORE_VID1 */ PAD_NC(GPP_B1, NONE),
|
||||
/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
|
||||
/* CPU_GP2 */ PAD_NC(GPP_B3, NONE),
|
||||
/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
|
||||
/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE),
|
||||
/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE),
|
||||
/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE),
|
||||
/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE),
|
||||
/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE),
|
||||
/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1),
|
||||
/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE),
|
||||
/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
|
||||
/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
|
||||
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
|
||||
/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE),
|
||||
/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE),
|
||||
/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE),
|
||||
/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
|
||||
/* SM1ALERT# */ PAD_NC(GPP_B23, NONE),
|
||||
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
|
||||
/* SML0_CLK */ PAD_NC(GPP_C3, NONE),
|
||||
/* SML0DATA */ PAD_NC(GPP_C4, NONE),
|
||||
/* SML0ALERT# */ PAD_NC(GPP_C5, NONE),
|
||||
/* UART0_RXD */ PAD_NC(GPP_C8, NONE),
|
||||
/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
|
||||
/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE),
|
||||
/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE),
|
||||
/* UART1_RXD */ PAD_NC(GPP_C12, NONE),
|
||||
/* UART1_TXD */ PAD_NC(GPP_C13, NONE),
|
||||
/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE),
|
||||
/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE),
|
||||
/* I2C0_SDA */ PAD_NC(GPP_C16, NONE),
|
||||
/* I2C0_SCL */ PAD_NC(GPP_C17, NONE),
|
||||
/* I2C1_SDA */ PAD_NC(GPP_C18, NONE),
|
||||
/* I2C1_SCL */ PAD_NC(GPP_C19, NONE),
|
||||
/* UART2_RXD */ PAD_NC(GPP_C20, NONE),
|
||||
/* UART2_TXD */ PAD_NC(GPP_C21, NONE),
|
||||
/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE),
|
||||
/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE),
|
||||
/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE),
|
||||
/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE),
|
||||
/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE),
|
||||
/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE),
|
||||
/* FLASHTRIG */ PAD_NC(GPP_D4, NONE),
|
||||
/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
|
||||
/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
|
||||
/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
|
||||
/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
|
||||
/* GPP_D9 */ PAD_NC(GPP_D9, NONE),
|
||||
/* GPP_D10 */ PAD_NC(GPP_D10, NONE),
|
||||
/* GPP_D11 */ PAD_NC(GPP_D11, NONE),
|
||||
/* GPP_D12 */ PAD_NC(GPP_D12, NONE),
|
||||
/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
|
||||
/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
|
||||
/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE),
|
||||
/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE),
|
||||
/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE),
|
||||
/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE),
|
||||
/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE),
|
||||
/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE),
|
||||
/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE),
|
||||
/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE),
|
||||
/* I2S_MCLK */ PAD_NC(GPP_D23, NONE),
|
||||
/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE),
|
||||
/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE),
|
||||
/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE),
|
||||
/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),
|
||||
/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
|
||||
/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),
|
||||
/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),
|
||||
/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),
|
||||
/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE),
|
||||
/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE),
|
||||
/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE),
|
||||
/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE),
|
||||
/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
/* DDI2_HPD */ PAD_NC(GPP_E14, NONE),
|
||||
/* DDI3_HPD */ PAD_NC(GPP_E15, NONE),
|
||||
/* DDI4_HPD */ PAD_NC(GPP_E16, NONE),
|
||||
/* EDP_HPD */ PAD_NC(GPP_E17, NONE),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
|
||||
/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
|
||||
/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
|
||||
/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
|
||||
/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
|
||||
/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE),
|
||||
/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE),
|
||||
/* I2S2_TXD */ PAD_NC(GPP_F2, NONE),
|
||||
/* I2S2_RXD */ PAD_NC(GPP_F3, NONE),
|
||||
/* I2C2_SDA */ PAD_NC(GPP_F4, NONE),
|
||||
/* I2C2_SCL */ PAD_NC(GPP_F5, NONE),
|
||||
/* I2C3_SDA */ PAD_NC(GPP_F6, NONE),
|
||||
/* I2C3_SCL */ PAD_NC(GPP_F7, NONE),
|
||||
/* I2C4_SDA */ PAD_NC(GPP_F8, NONE),
|
||||
/* I2C4_SDA */ PAD_NC(GPP_F9, NONE),
|
||||
/* I2C5_SDA */ PAD_NC(GPP_F10, NONE),
|
||||
/* I2C5_SCL */ PAD_NC(GPP_F11, NONE),
|
||||
/* EMMC_CMD */ PAD_NC(GPP_F12, NONE),
|
||||
/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE),
|
||||
/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE),
|
||||
/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE),
|
||||
/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE),
|
||||
/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE),
|
||||
/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE),
|
||||
/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE),
|
||||
/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE),
|
||||
/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE),
|
||||
/* EMMC_CLK */ PAD_NC(GPP_F22, NONE),
|
||||
/* GPP_F23 */ PAD_NC(GPP_F23, NONE),
|
||||
/* SD_CMD */ PAD_NC(GPP_G0, NONE),
|
||||
/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
|
||||
/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
|
||||
/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
|
||||
/* SD_DATA3 */ PAD_NC(GPP_G4, NONE),
|
||||
/* SD_CD# */ PAD_NC(GPP_G5, NONE),
|
||||
/* SD_CLK */ PAD_NC(GPP_G6, NONE),
|
||||
/* SD_WP */ PAD_NC(GPP_G7, NONE),
|
||||
/* PCH_BATLOW */ PAD_NC(GPD0, NONE),
|
||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* LAN_WAKE_N */ PAD_NC(GPD2, NONE),
|
||||
/* PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
|
||||
/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP),
|
||||
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE),
|
||||
/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* LANPHYC */ PAD_NC(GPD11, NONE),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* This file is part of the coreboot project. */
|
||||
|
||||
#include <bootstate.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
|
||||
{
|
||||
/*
|
||||
* Configure pads prior to SiliconInit() in case there's any
|
||||
* dependencies during hardware initialization.
|
||||
*/
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
|
||||
params->TurboMode = 1;
|
||||
params->PchThermalDeviceEnable = 0;
|
||||
params->PchPort61hEnable = 1;
|
||||
params->CdClock = 3;
|
||||
}
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* This file is part of the coreboot project. */
|
||||
|
||||
#include <fsp/api.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <spd_bin.h>
|
||||
#include <string.h>
|
||||
|
||||
static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
|
||||
{
|
||||
const u8 dq_map[2][12] = {
|
||||
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
|
||||
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
|
||||
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
|
||||
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
|
||||
memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
|
||||
memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
|
||||
}
|
||||
|
||||
static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
|
||||
{
|
||||
const u8 dqs_map[2][8] = {
|
||||
{ 0, 1, 2, 3, 4, 5, 6, 7 },
|
||||
{ 1, 0, 2, 3, 4, 5, 6, 7 } };
|
||||
memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
|
||||
memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
|
||||
}
|
||||
|
||||
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
|
||||
{
|
||||
const u16 RcompResistor[3] = { 121, 81, 100 };
|
||||
memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
|
||||
}
|
||||
|
||||
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
|
||||
{
|
||||
static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
|
||||
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
FSP_M_CONFIG *mem_cfg;
|
||||
mem_cfg = &mupd->FspmConfig;
|
||||
|
||||
mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
|
||||
&mem_cfg->DqByteMapCh1);
|
||||
mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
|
||||
&mem_cfg->DqsMapCpu2DramCh1);
|
||||
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
|
||||
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
|
||||
|
||||
struct spd_block blk = {
|
||||
.addr_map = { 0x50, 0x52, },
|
||||
};
|
||||
|
||||
mem_cfg->DqPinsInterleaved = 1;
|
||||
mem_cfg->CaVrefConfig = 2;
|
||||
|
||||
get_spd_smbus(&blk);
|
||||
dump_spd_info(&blk);
|
||||
|
||||
mem_cfg->MemorySpdDataLen = blk.len;
|
||||
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
|
||||
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
|
||||
}
|
||||
Loading…
Reference in New Issue