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src: Remove redundant use of ACPI offset(0) 

IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"

example:
    OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
    Field (OPR1)
    {
        Offset (0),     // Never needed
        FLD1, 32,
        Offset (4),     // Redundant, offset is already 4 (bytes)
        FLD2, 8,
        Offset (64),    // OK use of Offset.
        FLD3, 16,
    }

We will have those remarks:
dsdt.asl     14:         Offset (0),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset operator

dsdt.asl     16:         Offset (4),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset operator

Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-07-08 09:22:13 +02:00 committed by Felix Held
parent d477565dbd
commit 48a6c018bc
30 changed files with 10 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/ec/compal/ene932/acpi/ec.asl
View File

@ -16,8 +16,7 @@ Device (EC0)
Field (ERAM, ByteAcc, Lock, Preserve)
{
// EC Name Space Configuration
Offset(0x00),
, 1, // Reserved ; 00h.0
, 1, // Reserved ; 00h.0
LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1
, 6, // Reserved ; 00h.2 ~ 00h.6
HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function

1
src/ec/google/chromeec/acpi/ec.asl
View File

@ -31,7 +31,6 @@ Device (EC0)
OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN)
Field (ERAM, ByteAcc, Lock, Preserve)
{
Offset (0x00),
RAMV, 8, // EC RAM Version
TSTB, 8, // Test Byte
TSTC, 8, // Complement of Test Byte

1
src/ec/google/chromeec/acpi/emem.asl
View File

@ -4,7 +4,6 @@
* EMEM data may be accessed through port 62/66 or through LPC at 900h.
*/
Offset (0x00),
TIN0, 8, // Temperature 0
TIN1, 8, // Temperature 1
TIN2, 8, // Temperature 2

2
src/ec/quanta/it8518/acpi/ec.asl
View File

@ -16,7 +16,7 @@ Device (EC0)
OperationRegion(ERAM, EmbeddedControl, 0, 0xFF)
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // [Configuration Space 0]
// [Configuration Space 0]
, 1, // Reserved bit[0]
ENGA, 1, // Enable Global attention
ENHY, 1, // Enable Hotkey function

1
src/ec/roda/it8518/acpi/ec.asl
View File

@ -14,7 +14,6 @@ Device (EC0)
OperationRegion(ERAM, EmbeddedControl, 0, 0xFF)
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // [Configuration Space 0x0]
Offset(0x02), // [Configuration Space 0x2]
B0ST, 16, // Battery 0 State
B0FC, 16, // Battery 0 Last Full Charge Capacity

1
src/mainboard/facebook/monolith/acpi/ec.asl
View File

@ -29,7 +29,6 @@ Device (EC0)
OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF)
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x00),
CPUT, 8,
}

1
src/mainboard/lenovo/s230u/acpi/ec.asl
View File

@ -12,7 +12,6 @@ Device (EC0)
OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100)
Field (ERAM, ByteAcc, Lock, Preserve)
{
Offset(0x00),
, 1,
, 1,
HKFA, 1, // FN lock (Hotkey / FN row toggle)

3
src/mainboard/lippert/frontrunner-af/dsdt.asl
View File

@ -134,8 +134,7 @@ DefinitionBlock (
PIOD, 0x00000008,
}
IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
Offset(0x00), /* MiscControl */
, 1,
, 1, /* MiscControl */
T1EE, 1,
T2EE, 1,
Offset(0x01), /* MiscStatus */

1
src/soc/amd/picasso/acpi/globalnvs.asl
View File

@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
PCNT, 8, // 0x00 - Processor Count
LIDS, 8, // 0x01 - LID State
PWRS, 8, // 0x02 - AC Power State

1
src/soc/amd/stoneyridge/acpi/globalnvs.asl
View File

@ -12,7 +12,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
PCNT, 8, // 0x00 - Processor Count
LIDS, 8, // 0x01 - LID State
PWRS, 8, // 0x02 - AC Power State

1
src/soc/intel/apollolake/acpi/globalnvs.asl
View File

@ -12,7 +12,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
PCNT, 8, // 0x00 - Processor Count
PPCM, 8, // 0x01 - Max PPC State
LIDS, 8, // 0x02 - LID State

1
src/soc/intel/baytrail/acpi/globalnvs.asl
View File

@ -17,7 +17,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, /* 0x00 - Operating System */
SMIF, 8, /* 0x02 - SMI function */
PRM0, 8, /* 0x03 - SMI function parameter */

1
src/soc/intel/broadwell/pch/acpi/globalnvs.asl
View File

@ -16,7 +16,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter

1
src/soc/intel/broadwell/pch/acpi/xhci.asl
View File

@ -12,7 +12,6 @@ Device (XHCI)
OperationRegion (XPRT, PCI_Config, 0, 0x100)
Field (XPRT, AnyAcc, NoLock, Preserve)
{
Offset (0x0),
DVID, 16,
Offset (0x10),
, 16,

3
src/soc/intel/cannonlake/acpi/scs.asl
View File

@ -23,8 +23,7 @@ Scope (\_SB.PCI0) {
OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
Field(SCSR, WordAcc, NoLock, Preserve) {
Offset (0x0), /* PCI VID DID */
VDID, 32,
VDID, 32, /* PCI VID DID */
Offset (0x84), /* PMECTRLSTATUS */
PMCR, 16,
Offset (0xA2), /* PG_CONFIG */

1
src/soc/intel/denverton_ns/acpi/globalnvs.asl
View File

@ -16,7 +16,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter

1
src/soc/intel/skylake/acpi/globalnvs.asl
View File

@ -17,7 +17,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter

1
src/soc/intel/skylake/acpi/xhci.asl
View File

@ -83,7 +83,6 @@ Device (XHCI)
OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
Field (XPRT, AnyAcc, NoLock, Preserve)
{
Offset (0x0),
DVID, 16, /* VENDORID */
Offset (0x10),
, 16,

3
src/southbridge/amd/cimx/sb800/acpi/fch.asl
View File

@ -213,8 +213,7 @@ Scope(\){
PIOD, 0x00000008,
}
IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
Offset(0x00), /* MiscControl */
, 1,
, 1, /* MiscControl */
T1EE, 1,
T2EE, 1,
Offset(0x01), /* MiscStatus */

1
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
View File

@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter

3
src/southbridge/intel/bd82x6x/acpi/pch.asl
View File

@ -63,8 +63,7 @@ Scope(\)
OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // GPIO Use Select
GU00, 8,
GU00, 8, // GPIO Use Select
GU01, 8,
GU02, 8,
GU03, 8,

1
src/southbridge/intel/i82801ix/acpi/globalnvs.asl
View File

@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter

3
src/southbridge/intel/i82801ix/acpi/ich9.asl
View File

@ -32,8 +32,7 @@ Scope(\)
OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // GPIO Use Select
GU00, 8,
GU00, 8, // GPIO Use Select
GU01, 8,
GU02, 8,
GU03, 8,

1
src/southbridge/intel/i82801jx/acpi/globalnvs.asl
View File

@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter

2
src/southbridge/intel/i82801jx/acpi/ich10.asl
View File

@ -33,7 +33,7 @@ Scope(\)
OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // GPIO Use Select
// GPIO Use Select
GU00, 8,
GU01, 8,
GU02, 8,

1
src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
View File

@ -16,7 +16,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter

1
src/southbridge/intel/lynxpoint/acpi/xhci.asl
View File

@ -12,7 +12,6 @@ Device (XHCI)
OperationRegion (XPRT, PCI_Config, 0, 0x100)
Field (XPRT, AnyAcc, NoLock, Preserve)
{
Offset (0x0),
DVID, 16,
Offset (0x10),
, 16,

5
src/superio/fintek/f81803a/acpi/superio.asl
View File

@ -234,9 +234,8 @@ Device(SUPERIO_DEV) {
OperationRegion(APCx, SystemIO, APC5, 0x01)
Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/
{
Offset(0x00), /*Control Reg 5 */
, 7,
PSIN, 1 /* PSIN_FLAG */
, 7, /*Control Reg 5 */
PSIN, 1 /* PSIN_FLAG */
}
/* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */

2
src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
View File

@ -142,7 +142,6 @@
Add (Arg1, Local0, Local0)
OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
Offset (0x0),
varPciReg32, 32,
}
return (varPciReg32)
@ -160,7 +159,6 @@
Add (Arg1, Local0, Local0)
OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
Offset (0x0),
varPciReg32, 32,
}
Store (Arg2, varPciReg32)

2
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
View File

@ -55,7 +55,6 @@
Add (Arg1, Local0, Local0)
OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
Offset (0x0),
varPciReg32, 32,
}
return (varPciReg32)
@ -73,7 +72,6 @@
Add (Arg1, Local0, Local0)
OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
Offset (0x0),
varPciReg32, 32,
}
Store (Arg2, varPciReg32)