mainboard: Add Supermicro X10SLM+-F
This board runs well with coreboot. The documentation part of this commit lists what works and what doesn't. Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then boots FreeBSD 11.2. It has also been tested with GRUB directly booting Debian GNU/Linux 9.6 (kernel 4.9). Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Tristan Corrick
Philipp Deppenwiese
parent
8e9921178d
commit
44095c1edc
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@ -66,3 +66,7 @@ The boards in this section are not real mainboards, but emulators.
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## SiFive
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- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
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## Supermicro
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- [X10SLM+-F](supermicro/x10slm-f.md)
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@ -0,0 +1,203 @@
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# Supermicro X10SLM+-F
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This section details how to run coreboot on the [Supermicro X10SLM+-F].
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## Required proprietary blobs
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```eval_rst
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Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
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```
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## Building coreboot
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```eval_rst
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If you haven't already, build the coreboot toolchain as described in
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:doc:`../../lessons/lesson1`.
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```
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A fully working image should be possible so long as you have the
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Haswell `mrc.bin` file. You can set the basic config with the following
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commands. However, it is strongly advised to use `make menuconfig`
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afterwards (or instead), so that you can see all of the settings.
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```bash
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make distclean # Note: this will remove your current config, if it exists.
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touch .config
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./util/scripts/config --enable VENDOR_SUPERMICRO
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./util/scripts/config --enable BOARD_SUPERMICRO_X10SLM_PLUS_F
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./util/scripts/config --enable HAVE_MRC
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make olddefconfig
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```
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If you don't plan on using coreboot's serial console to collect logs,
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you might want to disable it at this point (`./util/scripts/config
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--disable CONSOLE_SERIAL`). It should reduce the boot time by several
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seconds. However, a more flexible method is to change the console log
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level from within an OS using `util/nvramtool`, or with the `nvramcui`
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payload.
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Now, run `make` to build the coreboot image.
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## Flashing coreboot
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```eval_rst
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In addition to the information here, please see the
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:doc:`../../flash_tutorial/index`.
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```
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### Internal programming
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Under the vendor firmware, the BIOS region of the flash chip is
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write-protected. Additionally, the vendor flashing tool does not work
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with a coreboot image. So, [external programming](#external-programming)
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needs to be used when first installing coreboot. By default, coreboot is
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not configured to write-protect the BIOS region, so internal programming
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can be used thereafter.
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[flashrom] may be used to flash coreboot internally:
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```bash
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sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
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```
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The use of `--noverify-all` is required since the Management Engine
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region is not readable even by the host.
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### External programming
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The main firmware flash chip is an SOIC-8 package located near the CMOS
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battery and SATA ports. It should come with a sticker attached that
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states the firmware revision (e.g. "X10SLH 4.424"). The chip model is
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an N25Q128A, and the datasheet can be found [here][N25Q128A].
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As with [internal programming](#internal-programming), [flashrom] works
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reliably:
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```bash
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flashrom -p <your-programmer> --ifd -i bios -w coreboot.rom
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```
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For flashing to work, power to the board should be disconnected (ACPI
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G3), and power should be supplied from the external programmer. There is
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a diode attached to Vcc, so such flashing should not damage the board.
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During testing, a single X10SLM+-F has been flashed dozens of times this
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way without issue.
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## BMC (IPMI)
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This board has an ASPEED [AST2400], which has BMC functionality. The
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BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400].
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This chip is an MX25L25635F, whose datasheet can be found
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[here][MX25L25635F].
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### Removing the BMC functionality
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The BMC functionality on this board can be removed. If you do not need
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its features, removing the BMC functionality might increase security.
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This topic has not been widely explored, and you should only **undertake
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this process at your own risk.**
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There is a jumper labelled `JPB1` on the board that states the ability
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to disable the BMC. Though, pins 1 and 2 are fixed together, keeping
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the BMC enabled. It might be possible to disable the BMC by cutting the
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connection between pins 1 and 2 (and then connecting pins 2 and 3). This
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has not been tested so far.
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Another approach is to erase the entire BMC firmware chip. However, if
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this is done, and the board's power cycled, the voltage changes on some
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pins of the flash chip, **so it will be harder to flash it again!**
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To remove the firmware, connect an external programmer to the BMC
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firmware chip. Vcc should **not** be connected via the external
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programmer. The system should be turned off, but the power still
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connected (ACPI S5). Then, erase the chip with [flashrom]. Power cycle
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the board, and the BMC should no longer be active.
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If you erase the BMC firmware while using the **vendor BIOS**, you
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will need to cut the connection between pins 1 and 2 of `JPB1`. The
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system will stall for two minutes each time when booting, but it will
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eventually start. There is no such delay when running coreboot.
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## ECC DRAM
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```eval_rst
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ECC DRAM seems to work, but please see
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:doc:`../../northbridge/intel/haswell/mrc.bin`
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for caveats.
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```
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## Known issues
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- The x8 PCIe slots do not work, as the Haswell code is missing support.
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The code to support it has been written, but it still needs to be
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reviewed and merged.
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- Broadwell CPUs are not supported. They might work with minimal changes
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to the code, but this has not been tested.
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- The PCH thermal sensor doesn't yet have a driver in coreboot, so it
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can't be used for temperature readings.
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- There is no automatic, OS-independent fan control. This is because
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the super I/O hardware monitor can only obtain valid CPU temperature
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readings from the PECI agent, but the required driver doesn't exist
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in coreboot. The `coretemp` driver can still be used for accurate CPU
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temperature readings from an OS, and hence the OS can do fan control.
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## Untested
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- TPM
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- PCIe x4 slot (it will almost certainly work)
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- BMC (IPMI) functionality
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- internal serial port
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- chassis intrusion header
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- SATA DOM header
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- standby power header
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- serial GPIO headers
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- power supply SMBus header
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- jumpers not otherwise mentioned
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- LEDs
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## Working
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- USB
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- S3 suspend/resume
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- Gigabit Ethernet
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- SATA
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- external serial port
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- VGA graphics
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- disabling VGA graphics using the jumper
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- hiding the AST2400 using the CMOS setting
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- super I/O hardware monitor (see [Known issues](#known-issues))
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- initialisation with Haswell MRC version 1.6.1 build 2
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- flashrom under coreboot
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- Wake-on-LAN
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- front panel header
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- internal buzzer
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | :doc:`../../northbridge/intel/haswell/index` |
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+------------------+--------------------------------------------------+
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| PCH | Intel Lynx Point (C224) |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6776 |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel SPS (server version of the ME) |
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+------------------+--------------------------------------------------+
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| Coprocessor | ASPEED AST2400 |
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+------------------+--------------------------------------------------+
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```
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## Extra links
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- [Board manual]
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[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
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[Board manual]: https://www.supermicro.com/manuals/motherboard/C224/MNL-1500.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
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[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
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[Supermicro X10SLM+-F]: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm
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@ -378,6 +378,11 @@ F: src/mainboard/siemens/mc_apl1/
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F: src/mainboard/siemens/mc_bdx1/
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F: src/mainboard/siemens/mc_tcu3/
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SUPERMICRO X10SLM+-F MAINBOARD
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M: Tristan Corrick <tristan@corrick.kiwi>
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S: Maintained
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F: src/mainboard/supermicro/x10slm-f/
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AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE
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M: Timothy Pearson <tpearson@raptorengineeringinc.com>
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S: Supported
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@ -0,0 +1,59 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_SUPERMICRO_X10SLM_PLUS_F
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select CPU_INTEL_HASWELL
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select DRIVERS_ASPEED_AST2050 # Supports AST2400 too.
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select NORTHBRIDGE_INTEL_HASWELL
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_LYNXPOINT
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select SUPERIO_NUVOTON_NCT6776
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select SUPERIO_NUVOTON_NCT6776_COM_A
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select TSC_MONOTONIC_TIMER
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config CBFS_SIZE
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hex
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default 0xb00000
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config MAINBOARD_DIR
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string
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default "supermicro/x10slm-f"
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config MAINBOARD_PART_NUMBER
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string
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default "X10SLM+-F"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x0803
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x15d9
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config MAX_CPUS
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int
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default 8
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endif
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@ -0,0 +1,2 @@
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config BOARD_SUPERMICRO_X10SLM_PLUS_F
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bool "X10SLM+-F"
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@ -0,0 +1,17 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += gpio.c
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK, 1)
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{
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Return (Package() { 0, 0 })
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}
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Method(_PTS, 1)
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{
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define NCT6776_SHOW_SP1
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#define NCT6776_SHOW_HWM
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#undef NCT6776_SHOW_KBC
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#undef NCT6776_SHOW_PP
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#undef NCT6776_SHOW_GPIO
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#include <superio/nuvoton/nct6776/acpi/superio.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/lynxpoint/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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}
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@ -0,0 +1,7 @@
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Category: server
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Board URL: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2013
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@ -0,0 +1,5 @@
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boot_option=Fallback
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debug_level=Debug
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nmi=Enable
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power_on_after_fail=Keep
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hide_ast2400=Disable
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@ -0,0 +1,97 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 3 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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||||
# coreboot config options: console
|
||||
#392 3 r 0 unused
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395 4 e 4 debug_level
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#399 1 r 0 unused
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||||
#400 8 r 0 reserved for century byte
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||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
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||||
409 2 e 5 power_on_after_fail
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# coreboot config options: mainboard
|
||||
416 1 e 1 hide_ast2400
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||||
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||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
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# -----------------------------------------------------------------
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||||
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enumerations
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||||
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#ID value text
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||||
1 0 Disable
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||||
1 1 Enable
|
||||
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
|
||||
3 0 Fallback
|
||||
3 1 Normal
|
||||
|
||||
4 0 Emergency
|
||||
4 1 Alert
|
||||
4 2 Critical
|
||||
4 3 Error
|
||||
4 4 Warning
|
||||
4 5 Notice
|
||||
4 6 Info
|
||||
4 7 Debug
|
||||
4 8 Spew
|
||||
|
||||
5 0 Disable
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 423 984
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
##
|
||||
## This program is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation, either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
chip northbridge/intel/haswell
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/haswell
|
||||
register "c1_acpower" = "1"
|
||||
register "c1_battery" = "1"
|
||||
register "c2_acpower" = "3"
|
||||
register "c2_battery" = "3"
|
||||
register "c3_acpower" = "5"
|
||||
register "c3_battery" = "5"
|
||||
|
||||
device lapic 0 on end
|
||||
device lapic 0xacac off end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x15d9 0x0803 inherit
|
||||
|
||||
device pci 00.0 on end # Host bridge
|
||||
device pci 01.0 on end # PEG 10
|
||||
device pci 01.1 on end # PEG 11
|
||||
device pci 02.0 off end # IGD
|
||||
device pci 03.0 off end # Mini-HD audio
|
||||
|
||||
chip southbridge/intel/lynxpoint
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8a"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x85"
|
||||
|
||||
register "sata_ahci" = "1"
|
||||
register "sata_port_map" = "0x3f"
|
||||
|
||||
register "gen1_dec" = "0x00000295" # Super I/O HWM
|
||||
|
||||
device pci 14.0 on end # xHCI controller
|
||||
device pci 16.0 on end # Management Engine interface 1
|
||||
device pci 16.1 on end # Management Engine interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 19.0 off end # Intel Gigabit Ethernet
|
||||
device pci 1a.0 on end # EHCI controller 2
|
||||
device pci 1b.0 off end # HD audio controller
|
||||
device pci 1c.0 on # PCIe root port 1
|
||||
device pci 00.0 on # ASPEED PCI-to-PCI bridge
|
||||
device pci 00.0 on end # VGA controller
|
||||
end
|
||||
end
|
||||
device pci 1c.1 off end # PCIe root port 2
|
||||
device pci 1c.2 on # PCIe root port 3
|
||||
device pci 00.0 on # Intel I210 Gigabit Ethernet
|
||||
subsystemid 0x15d9 0x1533
|
||||
end
|
||||
end
|
||||
device pci 1c.3 on # PCIe root port 4
|
||||
device pci 00.0 on # Intel I210 Gigabit Ethernet
|
||||
subsystemid 0x15d9 0x1533
|
||||
end
|
||||
end
|
||||
device pci 1c.4 on end # PCIe root port 5
|
||||
device pci 1c.5 off end # PCIe root port 6
|
||||
device pci 1c.6 off end # PCIe root port 7
|
||||
device pci 1c.7 off end # PCIe root port 8
|
||||
device pci 1d.0 on end # EHCI controller 1
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/nuvoton/nct6776
|
||||
device pnp 2e.0 off end # Floppy
|
||||
device pnp 2e.1 off end # Parallel
|
||||
device pnp 2e.2 on # UART A
|
||||
io 0x60 = 0x03f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # UART B
|
||||
io 0x60 = 0x02f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 off end # PS/2 KBC
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GPIO8
|
||||
device pnp 2e.107 off end # GPIO9
|
||||
device pnp 2e.8 off end # WDT
|
||||
device pnp 2e.108 off end # GPIO0
|
||||
device pnp 2e.208 off end # GPIOA
|
||||
device pnp 2e.308 off end # GPIO base
|
||||
device pnp 2e.109 off end # GPIO1
|
||||
device pnp 2e.209 off end # GPIO2
|
||||
device pnp 2e.309 off end # GPIO3
|
||||
device pnp 2e.409 off end # GPIO4
|
||||
device pnp 2e.509 off end # GPIO5
|
||||
device pnp 2e.609 off end # GPIO6
|
||||
device pnp 2e.709 off end # GPIO7
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HWM, LED
|
||||
io 0x60 = 0x0290
|
||||
io 0x62 = 0
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.d off end # VID
|
||||
device pnp 2e.e off end # CIR wake-up
|
||||
device pnp 2e.f off end # GPIO PP/OD
|
||||
device pnp 2e.14 off end # SVID
|
||||
device pnp 2e.16 off end # Deep sleep
|
||||
device pnp 2e.17 off end # GPIOA
|
||||
end
|
||||
end
|
||||
device pci 1f.2 on end # SATA controller 1
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 off end # SATA controller 2
|
||||
device pci 1f.6 on end # PCH thermal sensor
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
|
||||
DefinitionBlock("dsdt.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181220)
|
||||
{
|
||||
#include "acpi/platform.asl"
|
||||
#include <southbridge/intel/lynxpoint/acpi/platform.asl>
|
||||
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <northbridge/intel/haswell/acpi/haswell.asl>
|
||||
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_GPIO,
|
||||
.gpio3 = GPIO_MODE_GPIO,
|
||||
.gpio4 = GPIO_MODE_GPIO,
|
||||
.gpio5 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_GPIO,
|
||||
.gpio10 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio19 = GPIO_MODE_GPIO,
|
||||
.gpio20 = GPIO_MODE_GPIO,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_GPIO,
|
||||
.gpio26 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_OUTPUT,
|
||||
.gpio1 = GPIO_DIR_OUTPUT,
|
||||
.gpio2 = GPIO_DIR_OUTPUT,
|
||||
.gpio3 = GPIO_DIR_INPUT,
|
||||
.gpio4 = GPIO_DIR_INPUT,
|
||||
.gpio5 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_OUTPUT,
|
||||
.gpio7 = GPIO_DIR_OUTPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio9 = GPIO_DIR_INPUT,
|
||||
.gpio10 = GPIO_DIR_INPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_INPUT,
|
||||
.gpio16 = GPIO_DIR_OUTPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio19 = GPIO_DIR_OUTPUT,
|
||||
.gpio20 = GPIO_DIR_OUTPUT,
|
||||
.gpio21 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio25 = GPIO_DIR_INPUT,
|
||||
.gpio26 = GPIO_DIR_INPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio0 = GPIO_LEVEL_HIGH,
|
||||
.gpio1 = GPIO_LEVEL_HIGH,
|
||||
.gpio2 = GPIO_LEVEL_HIGH,
|
||||
.gpio6 = GPIO_LEVEL_HIGH,
|
||||
.gpio7 = GPIO_LEVEL_HIGH,
|
||||
.gpio8 = GPIO_LEVEL_HIGH,
|
||||
.gpio16 = GPIO_LEVEL_HIGH,
|
||||
.gpio19 = GPIO_LEVEL_HIGH,
|
||||
.gpio20 = GPIO_LEVEL_HIGH,
|
||||
.gpio24 = GPIO_LEVEL_HIGH,
|
||||
.gpio27 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio3 = GPIO_INVERT,
|
||||
.gpio14 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_GPIO,
|
||||
.gpio41 = GPIO_MODE_GPIO,
|
||||
.gpio42 = GPIO_MODE_GPIO,
|
||||
.gpio43 = GPIO_MODE_GPIO,
|
||||
.gpio44 = GPIO_MODE_GPIO,
|
||||
.gpio45 = GPIO_MODE_GPIO,
|
||||
.gpio46 = GPIO_MODE_GPIO,
|
||||
.gpio47 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_GPIO,
|
||||
.gpio51 = GPIO_MODE_GPIO,
|
||||
.gpio52 = GPIO_MODE_GPIO,
|
||||
.gpio53 = GPIO_MODE_GPIO,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_GPIO,
|
||||
.gpio59 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_INPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio36 = GPIO_DIR_OUTPUT,
|
||||
.gpio37 = GPIO_DIR_OUTPUT,
|
||||
.gpio40 = GPIO_DIR_INPUT,
|
||||
.gpio41 = GPIO_DIR_INPUT,
|
||||
.gpio42 = GPIO_DIR_INPUT,
|
||||
.gpio43 = GPIO_DIR_INPUT,
|
||||
.gpio44 = GPIO_DIR_INPUT,
|
||||
.gpio45 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio47 = GPIO_DIR_OUTPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_INPUT,
|
||||
.gpio51 = GPIO_DIR_OUTPUT,
|
||||
.gpio52 = GPIO_DIR_INPUT,
|
||||
.gpio53 = GPIO_DIR_OUTPUT,
|
||||
.gpio54 = GPIO_DIR_OUTPUT,
|
||||
.gpio55 = GPIO_DIR_INPUT,
|
||||
.gpio59 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio36 = GPIO_LEVEL_HIGH,
|
||||
.gpio37 = GPIO_LEVEL_HIGH,
|
||||
.gpio47 = GPIO_LEVEL_LOW,
|
||||
.gpio51 = GPIO_LEVEL_HIGH,
|
||||
.gpio53 = GPIO_LEVEL_HIGH,
|
||||
.gpio54 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_GPIO,
|
||||
.gpio65 = GPIO_MODE_GPIO,
|
||||
.gpio66 = GPIO_MODE_GPIO,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio64 = GPIO_DIR_INPUT,
|
||||
.gpio65 = GPIO_DIR_INPUT,
|
||||
.gpio66 = GPIO_DIR_INPUT,
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_OUTPUT,
|
||||
.gpio73 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio72 = GPIO_LEVEL_HIGH,
|
||||
.gpio73 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {};
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <option.h>
|
||||
#include <stdint.h>
|
||||
#include <types.h>
|
||||
|
||||
/*
|
||||
* Hiding the AST2400 might be desirable to reduce attack surface.
|
||||
*
|
||||
* The PCIe root port that the AST2400 is on is disabled, but the
|
||||
* AST2400 itself likely remains in an enabled state.
|
||||
*
|
||||
* The AST2400 is also attached to the LPC. That interface does not get
|
||||
* disabled.
|
||||
*/
|
||||
static void hide_ast2400(void)
|
||||
{
|
||||
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1c, 0));
|
||||
if (!dev)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Marking this device as disabled means that the southbridge code
|
||||
* will properly disable the root port when it configures it later.
|
||||
*/
|
||||
dev->enabled = 0;
|
||||
printk(BIOS_INFO, "The AST2400 is now set to be hidden.\n");
|
||||
}
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
u8 hide = 0;
|
||||
|
||||
if (get_option(&hide, "hide_ast2400") == CB_SUCCESS && hide)
|
||||
hide_ast2400();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("X10SLM+-F")
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cpu/intel/haswell/haswell.h>
|
||||
#include <cpu/intel/romstage.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
#include <northbridge/intel/haswell/pei_data.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
#include <stdint.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
#include <superio/nuvoton/nct6776/nct6776.h>
|
||||
|
||||
static const struct rcba_config_instruction rcba_config[] = {
|
||||
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
|
||||
RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),
|
||||
RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
|
||||
RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),
|
||||
RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),
|
||||
RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
|
||||
RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
|
||||
RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
|
||||
|
||||
RCBA_RMW_REG_32(FD, ~0UL, PCH_DISABLE_ALWAYS),
|
||||
|
||||
RCBA_END_CONFIG,
|
||||
};
|
||||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
|
||||
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
|
||||
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
|
||||
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
|
||||
|
||||
/* Select HWM/LED functions instead of floppy functions. */
|
||||
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
|
||||
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
|
||||
|
||||
/* Power RAM in S3 and let the PCH handle power failure actions. */
|
||||
pnp_set_logical_device(ACPI_DEV);
|
||||
pnp_write_config(ACPI_DEV, 0xe4, 0x70);
|
||||
|
||||
nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = DEFAULT_PCIEXBAR,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.wdbbar = 0x4000000,
|
||||
.wdbsize = 0x1000,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
.system_type = 1, /* desktop/server */
|
||||
.tseg_size = CONFIG_SMM_TSEG_SIZE,
|
||||
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 },
|
||||
.ec_present = 0,
|
||||
.ddr_refresh_2x = 1,
|
||||
.max_ddr3_freq = 1600,
|
||||
.usb2_ports = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0040, 1, 0, USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
|
||||
{ 0x0110, 1, 1, USB_PORT_BACK_PANEL },
|
||||
{ 0x0110, 1, 1, USB_PORT_BACK_PANEL },
|
||||
{ 0x0110, 1, 2, USB_PORT_BACK_PANEL },
|
||||
{ 0x0110, 1, 2, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
|
||||
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
|
||||
},
|
||||
.usb3_ports = {
|
||||
/* Enable, OCn# */
|
||||
{ 1, 1 },
|
||||
{ 1, 1 },
|
||||
{ 0, USB_OC_PIN_SKIP },
|
||||
{ 0, USB_OC_PIN_SKIP },
|
||||
{ 1, 3 },
|
||||
{ 1, 3 },
|
||||
},
|
||||
};
|
||||
|
||||
struct romstage_params romstage_params = {
|
||||
.pei_data = &pei_data,
|
||||
.gpio_map = &mainboard_gpio_map,
|
||||
.rcba_config = rcba_config,
|
||||
.bist = bist,
|
||||
};
|
||||
|
||||
romstage_common(&romstage_params);
|
||||
}
|
||||
Loading…
Reference in New Issue