soc/amd: Move update_microcode.c to common/block/cpu

We also want to support uCode loading on cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Raul E Rangel 2021-02-12 14:37:43 -07:00 committed by Felix Held
parent 844775059d
commit 394c6b0922
5 changed files with 22 additions and 3 deletions

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@ -44,3 +44,16 @@ config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
Select this option to add the common functions for getting the TSC
frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC-
based monotonic timer functionality to the build.
config SOC_AMD_COMMON_BLOCK_UCODE
bool
select SUPPORT_CPU_UCODE_IN_CBFS
default n
help
Builds in support for loading uCode.
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
int
depends on SOC_AMD_COMMON_BLOCK_UCODE
help
Defines the size of the uCode binary in bytes.

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@ -1 +1,2 @@
subdirs-y += ./*
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c

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@ -8,7 +8,10 @@
#include <cpu/amd/msr.h>
#include <cbfs.h>
#define MPB_MAX_SIZE 3200
_Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0,
"SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set");
#define MPB_MAX_SIZE CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE
#define MPB_DATA_OFFSET 32
struct microcode {

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@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SPI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_UCODE
select PROVIDES_ROM_SHARING
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select PARALLEL_MP
@ -58,7 +59,9 @@ config CPU_SPECIFIC_OPTIONS
select FSP_COMPRESS_FSP_S_LZMA
select UDK_2017_BINDING
select HAVE_CF9_RESET
select SUPPORT_CPU_UCODE_IN_CBFS
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
default 3200
config FSP_M_FILE
string "FSP-M (memory init) binary path and filename"

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@ -48,7 +48,6 @@ ramstage-y += uart.c
ramstage-y += finalize.c
ramstage-y += soc_util.c
ramstage-y += fsp_params.c
ramstage-y += update_microcode.c
ramstage-y += graphics.c
ramstage-y += pcie_gpp.c
ramstage-y += xhci.c