doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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# OCP Delta Lake
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This page describes coreboot support status for the [OCP] (Open Compute Project)
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Delta Lake server platform.
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## Introduction
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OCP Delta Lake server platform is a component of multi-host server system
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Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020].
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Delta Lake server is a single socket Cooper Lake Scalable Processor server.
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Yosemite-V3 has multiple configurations. Depending on configurations, it may
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host up to 4 Delta Lake servers in one sled.
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Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners
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jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative solution.
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## Required blobs
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This board currently requires:
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- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
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is not yet available to the public. It will be made public some time after the MP
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(Mass Production) of CooperLake Scalable Processor when the FSP is mature.
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- Microcode: Not yet available to the public.
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- ME binary: Not yet available to the public.
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## Payload
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- LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload.
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U-root as initramfs, is used in the joint development. It can be built
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following [All about u-root].
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## Flashing coreboot
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To do in-band FW image update, use [flashrom]:
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flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \
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-i bios --noverify-all -w <path to coreboot image>
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From OpenBMC, to update FW image:
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fw-util slotx --update bios <path to coreboot image>
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To power off/on the host:
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power-util slotx off
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power-util slotx on
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To connect to console through SOL (Serial Over Lan):
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sol-util slotx
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## Working features
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The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root]
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as initramfs.
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- SMBIOS:
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- Type 0 -- BIOS Information
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- Type 1 -- System Information
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- Type 2 -- Baseboard Information
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- Type 3 -- System Enclosure or Chassis
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- Type 4 -- Processor Information
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- Type 8 -- Port Connector Information
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- Type 9 -- PCI Slot Information
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- Type 11 -- OEM String
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- Type 13 -- BIOS Language Information
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- Type 16 -- Physical Memory Array
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- Type 19 -- Memory Array Mapped Address
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- Type 127 -- End-of-Table
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- BMC integration:
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- BMC readiness check
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- IPMI commands
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- watchdog timer
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- POST complete pin acknowledgement
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- SEL record generation
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- Early serial output
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- port 80h direct to GPIO
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- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
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- Skipping memory training upon subsequent reboots by using MRC cache
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- BMC crash dump
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- Error injection through ITP
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## Firmware configurations
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[ChromeOS VPD] is used to store most of the firmware configurations.
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RO_VPD region holds default values, while RW_VPD region holds customized
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values.
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VPD variables supported are:
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- firmware_version: This variable holds overall firmware version. coreboot
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uses that value to populate smbios type 1 version field.
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## Known issues
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- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not
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support FSP_USES_CB_STACK. An IPS ticket is filed with Intel.
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- VT-d is not supported. An IPS ticket is filed with Intel.
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- PCIe bifuration is not supported. An IPS ticket is filed with Intel.
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- ME based power capping. This is a bug in ME. An IPS ticket is filed
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with Intel.
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- RO_VPD region as well as other RO regions are not write protected.
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- HECI is not set up correctly, so BMC is not able to get PCH and DIMM
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temperature sensor readings.
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## Feature gaps
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- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers
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at the moment.
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- SMBIOS:
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- Type 7 -- Cache Information
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- Type 17 -- Memory Device
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- Type 38 -- IPMI Device Information
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- Type 41 -- Onboard Devices Extended Information
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- ACPI:
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- DMAR
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- PFR/CBnT
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## Technology
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```eval_rst
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+------------------------+---------------------------------------------+
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| Processor (1 socket) | Intel Cooper Lake Scalable Processor |
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+------------------------+---------------------------------------------+
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| BMC | Aspeed AST 2500 |
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+------------------------+---------------------------------------------+
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| PCH | Intel Lewisburg C621 |
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+------------------------+---------------------------------------------+
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```
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[OCP]: https://www.opencompute.org
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[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
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[flashrom]: https://flashrom.org/Flashrom
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[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
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[u-root]: https://u-root.org/
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[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
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