From 348f2a63707cc1711cc836837fc7f5b36b2e0553 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 5 Aug 2020 21:38:59 +0200 Subject: [PATCH] soc/intel/skylake: set MSR LT_LOCK_MEMORY only when using native MP init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSP takes care of setting the MSR LT_LOCK_MEMORY when SkipMpInit=0. Thus, only set the lock when native MP init is used (SkipMpInit=1). Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/44243 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/skylake/finalize.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index ebbd3da2386c..9e9f1ed2ccd6 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -84,7 +84,12 @@ static void soc_lockdown(struct device *dev) pci_write_config8(dev, GEN_PMCON_A, reg8); } - cpu_lt_lock_memory(); + /* + * Lock chipset memory registers to protect SMM. + * When SkipMpInit=0, this is done by FSP. + */ + if (!CONFIG(USE_INTEL_FSP_MP_INIT)) + cpu_lt_lock_memory(); } static void soc_finalize(void *unused)