coreboot-mirror
/
coreboot
mirror of https://review.coreboot.org/coreboot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure 

The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

BUG=b:185631878
TEST=Built image and booted to kernel on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I408fac7ff1185f4aa87bc4ffac7f25e31a4802b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
John Zhao 2021-04-17 13:00:46 -07:00 committed by Patrick Georgi
parent c68ca81589
commit 3062083d42
1 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/soc/intel/tigerlake/acpi.c
View File

@ -198,6 +198,20 @@ static unsigned long soc_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current);
}
/* TCSS Thunderbolt root ports */
for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
if (tbtbar && tbten) {
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
current += acpi_create_dmar_ds_pci_br(current, 0, 7, i);
acpi_dmar_drhd_fixup(tmp, current);
}
}
uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
@ -216,20 +230,6 @@ static unsigned long soc_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current);
}
/* TCSS Thunderbolt root ports */
for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
if (tbtbar && tbten) {
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
current += acpi_create_dmar_ds_pci_br(current, 0, 7, i);
acpi_dmar_drhd_fixup(tmp, current);
}
}
/* Add RMRR entry */
const unsigned long tmp = current;
current += acpi_create_dmar_rmrr(current, 0,