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Code Issues Releases Wiki Activity

treewide: Capitalize 'CMOS' 

Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-02-16 10:01:33 +01:00 committed by Patrick Georgi
parent ebdf298ec2
commit 2119d0ba43
27 changed files with 50 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/mainboard/msi/ms7707/ms7707.md
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@ -75,7 +75,7 @@ Put all back in place and restart the board. It might need 1-2 AC power cycles
to reinitialize (running at full fan speed - don't panic).
* External flashing has been tested with RPi2 without main power connected.
3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html).
* In case of going back to proprietary BIOS create/save cmos settings as early
* In case of going back to proprietary BIOS create/save CMOS settings as early
as possible (do not leave BIOS on first start without saving settings).
The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state
that needs an external flasher to revive. If stuck, reset the Fintek (see

2
Documentation/releases/coreboot-4.6-relnotes.md
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@ -164,7 +164,7 @@ Drivers (29 commits)
* i2c/hid: Add generic I2C HID driver
* i2c/max98927: add i2c driver for Maxim 98927 codec
* i2c/wacom_ts: Add support for WCOM touchscreen device driver
* pc80/rtc: Check cmos checksum BEFORE reading cmos value
* pc80/rtc: Check CMOS checksum BEFORE reading CMOS value
* regulator: Add driver for handling GPIO-based fixed regulator
* storage: Add SD/MMC/eMMC driver based upon depthcharge

2
Makefile.inc
View File

@ -293,7 +293,7 @@ $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h
endef
#######################################################################
# Parse plaintext cmos defaults into binary format
# Parse plaintext CMOS defaults into binary format
# arg1: source file
# arg2: binary file name
cbfs-files-processor-nvramtool= \

8
payloads/libpayload/drivers/options.c
View File

@ -157,7 +157,7 @@ static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *op
struct cb_cmos_entries *cmos_entry;
int len = name ? strnlen(name, CB_CMOS_MAX_NAME_LENGTH) : 0;
/* cmos entries are located right after the option table */
/* CMOS entries are located right after the option table */
cmos_entry = first_cmos_entry(option_table);
while (cmos_entry) {
if (memcmp((const char*)cmos_entry->name, name, len) == 0)
@ -186,12 +186,12 @@ struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cmos_entry)
struct cb_cmos_enums *first_cmos_enum(struct cb_cmos_option_table *option_table)
{
struct cb_cmos_entries *cmos_entry;
/* cmos entries are located right after the option table. Skip them */
/* CMOS entries are located right after the option table. Skip them */
cmos_entry = (struct cb_cmos_entries *)((unsigned char *)option_table + option_table->header_length);
while (cmos_entry->tag == CB_TAG_OPTION)
cmos_entry = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size);
/* cmos enums are located after cmos entries. */
/* CMOS enums are located after CMOS entries. */
return (struct cb_cmos_enums *)cmos_entry;
}
@ -237,7 +237,7 @@ static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table *
{
int len = strnlen(text, CB_CMOS_MAX_TEXT_LENGTH);
/* cmos enums are located after cmos entries. */
/* CMOS enums are located after CMOS entries. */
struct cb_cmos_enums *cmos_enum;
for ( cmos_enum = first_cmos_enum_of_id(option_table, config_id);
cmos_enum;

2
src/Kconfig
View File

@ -205,7 +205,7 @@ config INCLUDE_CONFIG_FILE
Alignment: 64 bytes
Name Offset Type Size
cmos_layout.bin 0x0 cmos layout 1159
cmos_layout.bin 0x0 CMOS layout 1159
fallback/romstage 0x4c0 stage 339756
fallback/ramstage 0x53440 stage 186664
fallback/payload 0x80dc0 payload 51526

12
src/commonlib/include/commonlib/coreboot_tables.h
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@ -431,15 +431,15 @@ struct lb_macs {
#define MAX_SERIALNO_LENGTH 32
/* The following structures are for the cmos definitions table */
/* cmos header record */
/* The following structures are for the CMOS definitions table */
/* CMOS header record */
struct cmos_option_table {
uint32_t tag; /* CMOS definitions table type */
uint32_t size; /* size of the entire table */
uint32_t header_length; /* length of header */
};
/* cmos entry record
/* CMOS entry record
* This record is variable length. The name field may be
* shorter than CMOS_MAX_NAME_LENGTH. The entry may start
* anywhere in the byte, but can not span bytes unless it
@ -459,7 +459,7 @@ struct cmos_entries {
};
/* cmos enumerations record
/* CMOS enumerations record
* This record is variable length. The text field may be
* shorter than CMOS_MAX_TEXT_LENGTH.
*/
@ -473,8 +473,8 @@ struct cmos_enums {
variable length int aligned */
};
/* cmos defaults record
* This record contains default settings for the cmos ram.
/* CMOS defaults record
* This record contains default settings for the CMOS ram.
*/
struct cmos_defaults {
uint32_t tag; /* default type */

4
src/drivers/pc80/rtc/mc146818rtc.c
View File

@ -160,7 +160,7 @@ static void cmos_init_vbnv(bool invalid)
occurred with !CONFIG_USE_OPTION_TABLE. However, __cmos_init() may
clear vbnv data for other internal reasons. For that, always back up
the vbnv contents and conditionally save them when __cmos_init()
indicates cmos was cleared. */
indicates CMOS was cleared. */
read_vbnv_cmos(vbnv);
if (__cmos_init(invalid))
@ -204,7 +204,7 @@ void cmos_check_update_date(void)
year = cmos_read(RTC_CLK_YEAR);
/*
* TODO: If century is 0xFF, 100% that the cmos is cleared.
* TODO: If century is 0xFF, 100% that the CMOS is cleared.
* Other than that, so far rtc_year is the only entry to check
* if the date is valid.
*/

2
src/drivers/pc80/rtc/option.c
View File

@ -26,7 +26,7 @@
/*
* This routine returns the value of the requested bits.
* input bit = bit count from the beginning of the cmos image
* input bit = bit count from the beginning of the CMOS image
* length = number of bits to include in the value
* ret = a character pointer to where the value is to be returned
* returns CB_SUCCESS = successful, cb_err code if an error occurred

2
src/lib/coreboot_table.c
View File

@ -505,7 +505,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
* lb_record...
*/
memcpy(rec_dest, option_table, option_table->size);
/* Create cmos checksum entry in coreboot table */
/* Create CMOS checksum entry in coreboot table */
lb_cmos_checksum(head);
} else {
printk(BIOS_ERR,

4
src/northbridge/intel/gm45/igd.c
View File

@ -153,13 +153,13 @@ void igd_compute_ggc(sysinfo_t *const sysinfo)
if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
sysinfo->ggc = 0x0002;
else {
/* 4 for 32MB, default if not set in cmos */
/* 4 for 32MB, default if not set in CMOS */
u8 gfxsize = 4;
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
2MB GTT + 2MB shadow GTT (0x0b00) else. */
get_option(&gfxsize, "gfx_uma_size");
/* Handle invalid cmos settings */
/* Handle invalid CMOS settings */
/* Only allow settings between 32MB and 352MB */
gfxsize = MIN(MAX(gfxsize, 4), 12);

2
src/northbridge/intel/i945/early_init.c
View File

@ -161,7 +161,7 @@ static void i945_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
/* vram size from cmos option */
/* vram size from CMOS option */
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS)
gfxsize = 2; /* 2 for 8MB */
/* make sure no invalid setting is used */

2
src/northbridge/intel/pineview/early_init.c
View File

@ -43,7 +43,7 @@ static void early_graphics_setup(void)
pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);
/* vram size from cmos option */
/* vram size from CMOS option */
if (get_option(&reg8, "gfx_uma_size") != CB_SUCCESS)
reg8 = 0; /* 0 for 8MB */
/* make sure no invalid setting is used */

4
src/northbridge/intel/x4x/early_init.c
View File

@ -56,8 +56,8 @@ void x4x_early_init(void)
/* Enable internal GFX */
pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
/* Set preallocated IGD size from cmos */
u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */
/* Set preallocated IGD size from CMOS */
u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */
get_option(&gfxsize, "gfx_uma_size");
if (gfxsize > 12)
gfxsize = 6;

4
src/security/vboot/vbnv.h
View File

@ -33,10 +33,10 @@ void vbnv_init(uint8_t *vbnv_copy);
void vbnv_reset(uint8_t *vbnv_copy);
/* CMOS backend */
/* Initialize the vbnv cmos backing store. The vbnv_copy pointer is used for
/* Initialize the vbnv CMOS backing store. The vbnv_copy pointer is used for
optional temporary storage in the init function. */
void vbnv_init_cmos(uint8_t *vbnv_copy);
/* Return non-zero if cmos power was lost. */
/* Return non-zero if CMOS power was lost. */
int vbnv_cmos_failed(void);
void read_vbnv_cmos(uint8_t *vbnv_copy);
void save_vbnv_cmos(const uint8_t *vbnv_copy);

6
src/security/vboot/vbnv_cmos.c
View File

@ -81,13 +81,13 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy)
void vbnv_init_cmos(uint8_t *vbnv_copy)
{
/* If no cmos failure just defer to the normal read path for checking
/* If no CMOS failure just defer to the normal read path for checking
vbnv contents' integrity. */
if (!vbnv_cmos_failed())
return;
/* In the case of cmos failure force the backup. If backup wasn't used
force the vbnv cmos to be reset. */
/* In the case of CMOS failure force the backup. If backup wasn't used
force the vbnv CMOS to be reset. */
if (!restore_from_backup(vbnv_copy)) {
vbnv_reset(vbnv_copy);
/* This parallels the vboot_reference implementation. */

4
src/soc/intel/baytrail/acpi/globalnvs.asl
View File

@ -71,8 +71,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

4
src/soc/intel/braswell/acpi/globalnvs.asl
View File

@ -73,8 +73,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

4
src/soc/intel/broadwell/acpi/globalnvs.asl
View File

@ -63,8 +63,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

4
src/soc/intel/skylake/acpi/globalnvs.asl
View File

@ -78,8 +78,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

4
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
View File

@ -138,8 +138,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

2
src/southbridge/intel/i82371eb/fadt.c
View File

@ -80,7 +80,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->flush_stride = 0;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */
fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
fadt->mon_alrm = 0x0; /* not supported */
fadt->century = 0x0; /* not supported */
/*

4
src/southbridge/intel/i82801gx/acpi/globalnvs.asl
View File

@ -132,8 +132,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

4
src/southbridge/intel/i82801ix/acpi/globalnvs.asl
View File

@ -137,8 +137,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

4
src/southbridge/intel/i82801jx/acpi/globalnvs.asl
View File

@ -137,8 +137,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

4
src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
View File

@ -133,8 +133,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
IPAT, 8, // 0xb9 - IGD panel type CMOS option
ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config

2
util/nvramtool/cli/nvramtool.c
View File

@ -126,7 +126,7 @@ int main(int argc, char *argv[])
if (!nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].found) {
cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, NULL);
if (cmos_default == NULL) {
fprintf(stderr, "Need a cmos.default in the CBFS image or separate cmos file (-D).\n");
fprintf(stderr, "Need a cmos.default in the CBFS image or separate CMOS file (-D).\n");
exit(1);
}
}

2
util/nvramtool/layout.c
View File

@ -93,7 +93,7 @@ static cmos_layout_get_fn_t cmos_layout_get_fn = default_cmos_layout_get_fn;
/****************************************************************************
* entries_overlap
*
* Return 1 if cmos entries 'p' and 'q' overlap. Else return 0.
* Return 1 if CMOS entries 'p' and 'q' overlap. Else return 0.
****************************************************************************/
static inline int entries_overlap(const cmos_entry_t * p,
const cmos_entry_t * q)