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intel/fsp_broadwell_de: Add early timestamps 

Modify intel/fsp_broadwell_de such that timestamp_init() is
before raminit (and CAR teardown of FSP1.0), adding two new
early timestamps while doing so.

Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already
do it this way.

Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35279
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-09-05 19:56:34 +03:00
parent 445394e9ab
commit 03026a2a7d
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
View File

@ -104,6 +104,10 @@ static void enable_integrated_uart(uint8_t port)
void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
{
post_code(0x40);
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (!CONFIG(INTEGRATED_UART)) {
/* Enable decoding of I/O locations for Super I/O devices */
pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
@ -123,6 +127,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
init_rtc();
setup_gpio_io_address();
timestamp_add_now(TS_BEFORE_INITRAM);
/*
* Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB
@ -144,7 +150,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
void *cbmem_hob_ptr;
post_code(0x4a);
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_AFTER_INITRAM);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);