/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__
#define __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__

/* DDRPHY_REG_PHYPLL1 */
DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0)
DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TST_EN, 4)

/* DDRPHY_REG_SHU_PHYPLL0 */
DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 15, 0)
DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_ICHP, 25, 24)

/* DDRPHY_REG_SHU_CLRPLL0 */
DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 15, 0)
DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_ICHP, 25, 24)

/* DDRPHY_REG_SHU_PHYPLL2 */
DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_POSDIV, 2, 0)
DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_PREDIV, 19, 18)

/* DDRPHY_REG_SHU_CLRPLL2 */
DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_POSDIV, 2, 0)
DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_PREDIV, 19, 18)

/* DDRPHY_REG_SHU_PHYPLL1 */
DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0)
DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1)
DEFINE_BITFIELD(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, 31, 16)

/* DDRPHY_REG_SHU_CLRPLL1 */
DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0)
DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1)
DEFINE_BITFIELD(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, 31, 16)

/* DDRPHY_REG_SHU_PLL1 */
DEFINE_BIT(SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 0)
DEFINE_BIT(SHU_PLL1_R_SHU_AUTO_PLL_MUX, 4)

/* DDRPHY_REG_SHU_PHYPLL3 */
DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, 0)
DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, 6)
DEFINE_BITFIELD(SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 9, 8)
DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 12)
DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 16)

/* DDRPHY_REG_SHU_CLRPLL3 */
DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, 0)
DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, 6)
DEFINE_BITFIELD(SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 9, 8)
DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 12)
DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 16)

/* DDRPHY_REG_SHU_MISC_CLK_CTRL0 */
DEFINE_BIT(SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL, 4)

/* DDRPHY_REG_SHU_B0_DQ14 */
DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 2)
DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, 5, 4)
DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 11)
DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 23, 16)

/* DDRPHY_REG_SHU_B1_DQ14 */
DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 2)
DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, 5, 4)
DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 11)
DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 23, 16)

/* DDRPHY_REG_SHU_B0_DQ6 */
DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, 18, 12)
DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, 20)
DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, 21)
DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, 23, 22)
DEFINE_BIT(SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, 29)

/* DDRPHY_REG_SHU_B1_DQ6 */
DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, 18, 12)
DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, 20)
DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, 21)
DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, 23, 22)
DEFINE_BIT(SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, 29)

/* DDRPHY_REG_SHU_CA_CMD11 */
DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0)
DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1)
DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA, 2)
DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, 17, 16)
DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, 19, 18)

/* DDRPHY_REG_SHU_B0_DQ11 */
DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0)
DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, 1)
DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0, 2)
DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0, 7)
DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, 17, 16)
DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, 19, 18)

/* DDRPHY_REG_SHU_B1_DQ11 */
DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0)
DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, 1)
DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1, 2)
DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1, 7)
DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, 17, 16)
DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, 19, 18)

/* DDRPHY_REG_SHU_CA_CMD14 */
DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, 5, 4)
DEFINE_BIT(SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 11)
DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 23, 16)

/* DDRPHY_REG_SHU_CA_CMD6 */
DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 5, 0)
DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, 18, 12)
DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 20)
DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, 21)
DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, 23, 22)
DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 26)
DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 27)
DEFINE_BIT(SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, 29)

/* DDRPHY_REG_SHU_B0_DLL1 */
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 4)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, 6)
DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, 9, 8)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 10)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 11)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 12)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 13)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 14)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 16)
DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 23, 20)
DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 24)

/* DDRPHY_REG_SHU_B1_DLL1 */
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 4)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, 6)
DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, 9, 8)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 10)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 11)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 12)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 13)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 14)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 16)
DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 23, 20)
DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 24)

/* DDRPHY_REG_SHU_CA_DLL1 */
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 4)
DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, 9, 8)
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 10)
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 11)
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 12)
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 13)
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 14)
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 16)
DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 23, 20)
DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 24)

/* DDRPHY_REG_SHU_B0_DQ1 */
DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0, 0)
DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0, 2)
DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, 12, 8)
DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 17, 16)
DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 26)
DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 27)
DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 31)

/* DDRPHY_REG_SHU_B1_DQ1 */
DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1, 0)
DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1, 2)
DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, 12, 8)
DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 17, 16)
DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 26)
DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 27)
DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 31)

/* DDRPHY_REG_SHU_CA_DLL_ARPI3 */
DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 11)
DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, 13)
DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 15)
DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, 16)
DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 17)
DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 19)

/* DDRPHY_REG_SHU_CA_CMD13 */
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, 0)
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, 1)
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 2)
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 7)
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 16)
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 17)
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 24)
DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 25)

/* DDRPHY_REG_SHU_CA_CMD1 */
DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, 0)
DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, 1)
DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, 2)
DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, 12, 8)
DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 17, 16)
DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 27)
DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 31)

/* DDRPHY_REG_SHU_CA_DLL_ARPI2 */
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 10)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 11)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 13)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 15)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 16)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 17)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 19)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 27)
DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 31)

/* DDRPHY_REG_CA_DLL_ARPI5 */
DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 7, 4)
DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 8)
DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 25)
DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 26)
DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 28)
DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, 31, 29)

/* DDRPHY_REG_B0_DLL_ARPI5 */
DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 7, 4)
DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 8)
DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 25)
DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 26)
DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 28)
DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, 31, 29)

/* DDRPHY_REG_B1_DLL_ARPI5 */
DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 7, 4)
DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 8)
DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 25)
DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 26)
DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 28)
DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, 31, 29)

/* DDRPHY_REG_CA_DLL_ARPI1 */
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 11)
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 13)
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 15)
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 16)
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 17)
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 19)
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 20)
DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 21)

/* DDRPHY_REG_B0_DLL_ARPI1 */
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 11)
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 13)
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 14)
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 15)
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 17)
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 19)
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 20)
DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 21)

/* DDRPHY_REG_B1_DLL_ARPI1 */
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 11)
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 13)
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 14)
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 15)
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 17)
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 19)
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 20)
DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 21)

/* DDRPHY_REG_SHU_CA_DLL0 */
DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 15, 12)
DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 23, 20)
DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 25)
DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 26)
DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 27)

/* DDRPHY_REG_SHU_B0_DLL0 */
DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 15, 12)
DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 23, 20)
DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 25)
DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 26)
DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 27)

/* DDRPHY_REG_SHU_B1_DLL0 */
DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 15, 12)
DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 23, 20)
DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 25)
DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 26)
DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 27)

/* DDRPHY_REG_SHU_B0_DLL_ARPI3 */
DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, 11)
DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, 13)
DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, 14)
DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, 15)
DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, 17)
DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0, 19)

/* DDRPHY_REG_SHU_B1_DLL_ARPI3 */
DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, 11)
DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, 13)
DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, 14)
DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, 15)
DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, 17)
DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1, 19)

/* DDRPHY_REG_SHU_CA_CMD2 */
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 0)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 4)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 5)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 6)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 8)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 9)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, 10)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, 11)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 12)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 13)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 16)
DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 17)

/* DDRPHY_REG_SHU_B0_DQ2 */
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 0)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 4)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 5)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 6)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 8)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 9)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, 10)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, 11)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 12)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 13)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 16)
DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, 17)

/* DDRPHY_REG_SHU_B1_DQ2 */
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 0)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 4)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 5)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 6)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 8)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 9)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, 10)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, 11)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 12)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 13)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 16)
DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, 17)

/* DDRPHY_REG_SHU_B0_DQ7 */
DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRANKRXDVS_B0, 3, 0)
DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 6)
DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 7)
DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 11, 8)
DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 12)
DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 13)
DEFINE_BIT(SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 14)
DEFINE_BIT(SHU_B0_DQ7_R_DMRODTEN_B0, 15)
DEFINE_BIT(SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 16)
DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 17)
DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 18)
DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 19)
DEFINE_BIT(SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 20)
DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 24)
DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 27, 25)
DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 28)
DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 31, 29)

/* DDRPHY_REG_SHU_B1_DQ7 */
DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRANKRXDVS_B1, 3, 0)
DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 6)
DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 7)
DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 11, 8)
DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 12)
DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 13)
DEFINE_BIT(SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 14)
DEFINE_BIT(SHU_B1_DQ7_R_DMRODTEN_B1, 15)
DEFINE_BIT(SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 16)
DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 17)
DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 18)
DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 19)
DEFINE_BIT(SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 20)
DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 24)
DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 27, 25)
DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 28)
DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 31, 29)

/* DDRPHY_REG_SHU_CA_CMD7 */
DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 17)
DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 19)
DEFINE_BIT(SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 20)

/* DDRPHY_REG_CA_CMD6 */
DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 6)
DEFINE_BITFIELD(CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 15, 14)
DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 16)
DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 17)
DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 18)
DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 19)
DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_LP4_SEL, 21)

/* DDRPHY_REG_B0_DQ6 */
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 6)
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 7)
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_O1_SEL_B0, 9)
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 12)
DEFINE_BITFIELD(B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 15, 14)
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 16)
DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, 17)
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 18)
DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 19)
DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, 21)
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 28)
DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0, 31)

/* DDRPHY_REG_B1_DQ6 */
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 6)
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 7)
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_O1_SEL_B1, 9)
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 12)
DEFINE_BITFIELD(B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 15, 14)
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 16)
DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, 17)
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 18)
DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 19)
DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, 21)
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 28)
DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1, 31)

/* DDRPHY_REG_CA_CMD2 */
DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0)
DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 1)
DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 2)
DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 3)
DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 14)
DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 15)
DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 20)
DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 21)
DEFINE_BIT(CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 22)
DEFINE_BITFIELD(CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 31, 24)

/* DDRPHY_REG_B0_DQ2 */
DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 1)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 2)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 3)
DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 8)
DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 9)
DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 10)
DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 11)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 12)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 13)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 14)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 15)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 20)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 21)
DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 22)
DEFINE_BITFIELD(B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 31, 24)

/* DDRPHY_REG_B1_DQ2 */
DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 1)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 2)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 3)
DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 8)
DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 9)
DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 10)
DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 11)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 12)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 13)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 14)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 15)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 20)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 21)
DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 22)
DEFINE_BITFIELD(B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 31, 24)

/* DDRPHY_REG_CA_CMD3 */
DEFINE_BIT(CA_CMD3_RG_TX_ARCMD_EN, 2)
DEFINE_BIT(CA_CMD3_RG_ARCMD_RESETB, 3)

/* DDRPHY_REG_B0_DQ3 */
DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1)
DEFINE_BIT(B0_DQ3_RG_TX_ARDQ_EN_B0, 2)
DEFINE_BIT(B0_DQ3_RG_ARDQ_RESETB_B0, 3)
DEFINE_BIT(B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0, 5)
DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0, 7)
DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 10)

/* DDRPHY_REG_B1_DQ3 */
DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1)
DEFINE_BIT(B1_DQ3_RG_TX_ARDQ_EN_B1, 2)
DEFINE_BIT(B1_DQ3_RG_ARDQ_RESETB_B1, 3)
DEFINE_BIT(B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1, 5)
DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1, 7)
DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 10)

/* DDRPHY_REG_SHU_B0_DQ13 */
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, 0)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 2)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 3)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 7)
DEFINE_BITFIELD(SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 13, 12)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 15)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 16)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 17)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 18)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 24)
DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 25)

/* DDRPHY_REG_SHU_B1_DQ13 */
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, 0)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 2)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 3)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 7)
DEFINE_BITFIELD(SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 13, 12)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 15)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 16)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 17)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 18)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 24)
DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 25)

/* DDRPHY_REG_SHU_B0_DQ10 */
DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, 0)
DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1)
DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, 2)
DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, 3)
DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 4)
DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, 10, 8)
DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 15)
DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 19, 18)

/* DDRPHY_REG_SHU_B1_DQ10 */
DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, 0)
DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1)
DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, 2)
DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, 3)
DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 4)
DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, 10, 8)
DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 15)
DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 19, 18)

/* DDRPHY_REG_SHU_CA_CMD10 */
DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 2)
DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 3)
DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA, 15)
DEFINE_BITFIELD(SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, 19, 18)

/* DDRPHY_REG_B0_DQ5 */
DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 13, 8)
DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16)
DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17)
DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 23, 20)
DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 24)
DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 25)
DEFINE_BIT(B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 31)

/* DDRPHY_REG_B1_DQ5 */
DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 13, 8)
DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16)
DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17)
DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 23, 20)
DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 24)
DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 25)
DEFINE_BIT(B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 31)

/* DDRPHY_REG_CA_CMD9 */
DEFINE_BIT(CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 0)
DEFINE_BIT(CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 4)

/* DDRPHY_REG_B0_DQ9 */
DEFINE_BIT(B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0)
DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 4)
DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 5)
DEFINE_BIT(B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 6)
DEFINE_BIT(B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 7)
DEFINE_BITFIELD(B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 15, 8)
DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 18, 16)
DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 22, 20)
DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 26, 24)
DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 30, 28)

/* DDRPHY_REG_B1_DQ9 */
DEFINE_BIT(B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0)
DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 4)
DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 5)
DEFINE_BIT(B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 6)
DEFINE_BIT(B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 7)
DEFINE_BITFIELD(B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 15, 8)
DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 18, 16)
DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 22, 20)
DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 26, 24)
DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 30, 28)

/* DDRPHY_REG_CA_CMD8 */
DEFINE_BIT(CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 13)
DEFINE_BIT(CA_CMD8_RG_ARDLL_RESETB_CA, 15)

/* DDRPHY_REG_B0_DQ8 */
DEFINE_BIT(B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 13)
DEFINE_BIT(B0_DQ8_RG_ARDLL_RESETB_B0, 15)

/* DDRPHY_REG_B1_DQ8 */
DEFINE_BIT(B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 13)
DEFINE_BIT(B1_DQ8_RG_ARDLL_RESETB_B1, 15)

/* DDRPHY_REG_CA_CMD11 */
DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVP, 4, 0)
DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVN, 12, 8)
DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 19)
DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_PULL_DN, 20)

/* DDRPHY_REG_MISC_CTRL1 */
DEFINE_BIT(MISC_CTRL1_R_RK_PINMUXSWAP_EN, 0)
DEFINE_BIT(MISC_CTRL1_R_DMPHYRST, 1)
DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCLK_OE, 2)
DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCMD_OE, 3)
DEFINE_BIT(MISC_CTRL1_R_DMARPIDQ_SW, 7)
DEFINE_BITFIELD(MISC_CTRL1_R_DMPINMUX, 9, 8)
DEFINE_BIT(MISC_CTRL1_R_DMRRESETB_I_OPT, 12)
DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_I, 13)
DEFINE_BIT(MISC_CTRL1_R_DMDQSIENCG_EN, 24)
DEFINE_BIT(MISC_CTRL1_R_DMSTBENCMP_RK_OPT, 25)
DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_E, 31)

/* DDRPHY_REG_B0_LP_CTRL0 */
DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0)
DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 4)
DEFINE_BIT(B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 8)
DEFINE_BIT(B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 9)
DEFINE_BIT(B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 12)
DEFINE_BIT(B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 13)
DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 16)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 17)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 18)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 19)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 20)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 21)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 22)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 23)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 24)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 25)
DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 26)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 27)
DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 28)

/* DDRPHY_REG_B1_LP_CTRL0 */
DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0)
DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 4)
DEFINE_BIT(B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 8)
DEFINE_BIT(B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 9)
DEFINE_BIT(B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 12)
DEFINE_BIT(B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 13)
DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 16)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 17)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 18)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 19)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 20)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 21)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 22)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 23)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 24)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 25)
DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 26)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 27)
DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 28)

/* DDRPHY_REG_CA_LP_CTRL0 */
DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0)
DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1)
DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 2)
DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 3)
DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 4)
DEFINE_BIT(CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 8)
DEFINE_BIT(CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 9)
DEFINE_BIT(CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 12)
DEFINE_BIT(CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 13)
DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 15)
DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 16)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 17)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 18)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 19)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 20)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 21)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 22)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 23)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 24)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 25)
DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 26)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 27)
DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 28)

/* DDRPHY_REG_MISC_LP_CTRL */
DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10, 0)
DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1)
DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10, 2)
DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 3)
DEFINE_BIT(MISC_LP_CTRL_RG_RRESETB_LP_SEL, 4)
DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 5)
DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 6)
DEFINE_BIT(MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 7)
DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 8)
DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 9)
DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 10)
DEFINE_BIT(MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, 11)
DEFINE_BIT(MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, 12)
DEFINE_BIT(MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, 13)
DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, 17)
DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, 18)
DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, 19)
DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, 20)

/* DDRPHY_REG_MISC_CG_CTRL9 */
DEFINE_BIT(MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 4)
DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 8)
DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 9)
DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 10)
DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 11)
DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 12)
DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 13)
DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 14)
DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 15)
DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 16)
DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 17)
DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 19)

/* DDRPHY_REG_MISC_SHU_RX_CG_CTRL */
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0)
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 1)
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT, 2)
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN, 4)
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN, 5)
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 8)
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 9)
DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 10)
DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 19, 16)
DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 23, 20)

/* DDRPHY_REG_MISC_SHU_CG_CTRL0 */
DEFINE_BITFIELD(MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 31, 0)

/* DDRPHY_REG_MISC_IMP_CTRL1 */
DEFINE_BIT(MISC_IMP_CTRL1_RG_IMP_EN, 1)
DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 2)
DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 3)
DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 4)
DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 5)
DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 6)
DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 7)
DEFINE_BIT(MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 14)
DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 31)

/* DDRPHY_REG_MISC_CG_CTRL0 */
DEFINE_BIT(MISC_CG_CTRL0_W_CHG_MEM, 0)
DEFINE_BITFIELD(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 3, 1)
DEFINE_BITFIELD(MISC_CG_CTRL0_CLK_MEM_SEL, 5, 4)
DEFINE_BIT(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 7)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 8)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 9)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_PHY_OFF_DISABLE, 10)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 11)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 12)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 13)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 14)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 15)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 16)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 17)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 18)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 19)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 20)
DEFINE_BIT(MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 22)
DEFINE_BIT(MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 29)

/* DDRPHY_REG_MISC_CKMUX_SEL */
DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLMUX, 0)
DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLDCM, 1)
DEFINE_BIT(MISC_CKMUX_SEL_RG_52M_104M_SEL, 12)
DEFINE_BITFIELD(MISC_CKMUX_SEL_FMEM_CK_MUX, 19, 18)

/* DDRPHY_REG_PHYPLL2 */
DEFINE_BIT(PHYPLL2_RG_RPHYPLL_RESETB, 16)
DEFINE_BIT(PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 21)
DEFINE_BIT(PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 22)

/* DDRPHY_REG_PHYPLL0 */
DEFINE_BIT(PHYPLL0_RG_RPHYPLL_EN, 31)

/* DDRPHY_REG_SHU_B0_DLL_ARPI2 */
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 10)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 11)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 13)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 14)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 15)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 17)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 19)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 27)
DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 31)

/* DDRPHY_REG_SHU_B1_DLL_ARPI2 */
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 10)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 11)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 13)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 14)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 15)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 17)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 19)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 27)
DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 31)

/* DDRPHY_REG_SHU_PLL2 */
DEFINE_BIT(SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0)

/* DDRPHY_REG_B0_SHU_MIDPI_CTRL */
DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0, 0)
DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0, 1)

/* DDRPHY_REG_B1_SHU_MIDPI_CTRL */
DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1, 0)
DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1, 1)

/* DDRPHY_REG_CA_SHU_MIDPI_CTRL */
DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, 0)
DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, 1)

/* DDRPHY_REG_CA_DLL_ARPI0 */
DEFINE_BIT(CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 3)

/* DDRPHY_REG_B0_DLL_ARPI0 */
DEFINE_BIT(B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 3)

/* DDRPHY_REG_B1_DLL_ARPI0 */
DEFINE_BIT(B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 3)

/* DDRPHY_REG_MISC_CG_CTRL2 */
DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0)
DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 5, 1)
DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 6)
DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 7)
DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 8)
DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 15, 9)
DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 20, 16)
DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 25, 21)
DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 26)
DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 27)
DEFINE_BIT(MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 28)
DEFINE_BIT(MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 29)
DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 30)
DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 31)

/* DDRPHY_REG_MISC_CTRL0 */
DEFINE_BIT(MISC_CTRL0_R_DMDQSIEN_FIFO_EN, 0)
DEFINE_BIT(MISC_CTRL0_R_DMSTBEN_SYNCOPT, 2)
DEFINE_BIT(MISC_CTRL0_R_DMVALID_DLY_OPT, 4)
DEFINE_BIT(MISC_CTRL0_R_DMVALID_NARROW_IG, 5)
DEFINE_BITFIELD(MISC_CTRL0_R_DMVALID_DLY, 10, 8)
DEFINE_BIT(MISC_CTRL0_IMPCAL_CHAB_EN, 12)
DEFINE_BIT(MISC_CTRL0_IMPCAL_TRACK_DISABLE, 13)
DEFINE_BIT(MISC_CTRL0_IMPCAL_LP_ECO_OPT, 18)
DEFINE_BIT(MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 19)
DEFINE_BIT(MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 20)
DEFINE_BIT(MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF, 27)
DEFINE_BIT(MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL, 28)
DEFINE_BIT(MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL, 29)
DEFINE_BIT(MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL, 30)
DEFINE_BIT(MISC_CTRL0_R_STBENCMP_DIV4CK_EN, 31)

/* DDRPHY_REG_MISC_RXDVS2 */
DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF, 0)
DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG, 8)
DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN, 16)
DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR, 17)
DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN, 18)

/* DDRPHY_REG_MISC_DVFS_EMI_CLK */
DEFINE_BIT(MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 24)

/* DDRPHY_REG_B0_DQ10 */
DEFINE_BIT(B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0, 0)

/* DDRPHY_REG_B1_DQ10 */
DEFINE_BIT(B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1, 0)

/* DDRPHY_REG_MISC_DVFSCTL */
DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW, 3, 0)
DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW, 7, 4)
DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW, 11, 8)
DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW, 15, 12)
DEFINE_BIT(MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT, 18)
DEFINE_BIT(MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE, 26)
DEFINE_BIT(MISC_DVFSCTL_R_DVFS_PICG_POSTPONE, 27)
DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN, 31, 28)

/* DDRPHY_REG_MISC_STBCAL1 */
DEFINE_BIT(MISC_STBCAL1_STBCNT_SHU_RST_EN, 0)
DEFINE_BIT(MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD, 2)
DEFINE_BIT(MISC_STBCAL1_STBCNT_MODESEL, 4)
DEFINE_BIT(MISC_STBCAL1_DQSIEN_7UI_EN, 5)
DEFINE_BIT(MISC_STBCAL1_STB_SHIFT_DTCOUT_IG, 6)
DEFINE_BIT(MISC_STBCAL1_STB_FLAGCLR_OPT, 8)
DEFINE_BIT(MISC_STBCAL1_STBCNT_SW_RST, 15)
DEFINE_BITFIELD(MISC_STBCAL1_STBCAL_FILTER, 31, 16)

/* DDRPHY_REG_MISC_STBCAL2 */
DEFINE_BIT(MISC_STBCAL2_STB_PIDLYCG_IG, 0)
DEFINE_BIT(MISC_STBCAL2_STB_UIDLYCG_IG, 1)
DEFINE_BITFIELD(MISC_STBCAL2_STB_DBG_EN, 7, 4)
DEFINE_BIT(MISC_STBCAL2_STB_DBG_CG_AO, 8)
DEFINE_BIT(MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT, 9)
DEFINE_BIT(MISC_STBCAL2_DQSGCNT_BYP_REF, 10)
DEFINE_BIT(MISC_STBCAL2_STB_PICG_EARLY_1T_EN, 16)
DEFINE_BIT(MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 17)
DEFINE_BIT(MISC_STBCAL2_STB_IG_XRANK_CG_RST, 18)
DEFINE_BIT(MISC_STBCAL2_STB_RST_BY_RANK, 19)
DEFINE_BIT(MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 20)
DEFINE_BIT(MISC_STBCAL2_STB_GERRSTOP, 28)
DEFINE_BIT(MISC_STBCAL2_STB_GERR_RST, 29)
DEFINE_BIT(MISC_STBCAL2_STB_GERR_B01, 30)
DEFINE_BIT(MISC_STBCAL2_STB_GERR_B23, 31)

/* DDRPHY_REG_MISC_SHU_STBCAL */
DEFINE_BITFIELD(MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, 13, 12)
DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_BURST_MODE, 14)
DEFINE_BIT(MISC_SHU_STBCAL_STBCALEN, 16)
DEFINE_BIT(MISC_SHU_STBCAL_STB_SELPHCALEN, 17)

/* DDRPHY_REG_MISC_STBCAL */
DEFINE_BIT(MISC_STBCAL_PIMASK_RKCHG_OPT, 0)
DEFINE_BIT(MISC_STBCAL_STBDLELAST_OPT, 4)
DEFINE_BITFIELD(MISC_STBCAL_STBDLELAST_PULSE, 11, 8)
DEFINE_BIT(MISC_STBCAL_STBDLELAST_FILTER, 12)
DEFINE_BIT(MISC_STBCAL_STBSTATE_OPT, 15)
DEFINE_BIT(MISC_STBCAL_PHYVALID_IG, 16)
DEFINE_BIT(MISC_STBCAL_SREF_DQSGUPD, 17)
DEFINE_BIT(MISC_STBCAL_RKCHGMASKDIS, 19)
DEFINE_BIT(MISC_STBCAL_PICGEN, 20)
DEFINE_BIT(MISC_STBCAL_REFUICHG, 21)
DEFINE_BIT(MISC_STBCAL_STBCAL2R, 23)
DEFINE_BIT(MISC_STBCAL_PICHGBLOCK_NORD, 26)
DEFINE_BIT(MISC_STBCAL_STB_DQIEN_IG, 27)
DEFINE_BIT(MISC_STBCAL_DQSIENCG_CHG_EN, 28)
DEFINE_BIT(MISC_STBCAL_DQSIENCG_NORMAL_EN, 29)
DEFINE_BIT(MISC_STBCAL_DQSIENMODE, 31)

/* DDRPHY_REG_B0_PHY2 */
DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 7, 4)
DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 8)
DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, 24, 16)
DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0, 28)

/* DDRPHY_REG_B1_PHY2 */
DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 7, 4)
DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 8)
DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, 24, 16)
DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1, 28)

/* DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL */
DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 0)
DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 1)
DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 11, 8)
DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 15, 12)

/* DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL */
DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 0)
DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 1)
DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 11, 8)
DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 15, 12)

/* DDRPHY_REG_B0_RXDVS0 */
DEFINE_BIT(B0_RXDVS0_R_RX_RANKINSEL_B0, 0)
DEFINE_BITFIELD(B0_RXDVS0_R_RX_RANKINCTL_B0, 7, 4)
DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0, 9)
DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0, 19)
DEFINE_BIT(B0_RXDVS0_R_HWRESTORE_ENA_B0, 22)
DEFINE_BIT(B0_RXDVS0_R_HWSAVE_MODE_ENA_B0, 24)
DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 28)
DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0, 29)
DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 31)

/* DDRPHY_REG_B1_RXDVS0 */
DEFINE_BIT(B1_RXDVS0_R_RX_RANKINSEL_B1, 0)
DEFINE_BITFIELD(B1_RXDVS0_R_RX_RANKINCTL_B1, 7, 4)
DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1, 9)
DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1, 19)
DEFINE_BIT(B1_RXDVS0_R_HWRESTORE_ENA_B1, 22)
DEFINE_BIT(B1_RXDVS0_R_HWSAVE_MODE_ENA_B1, 24)
DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 28)
DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1, 29)
DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 31)

/* DDRPHY_REG_RK_B0_RXDVS3 */
DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0, 7, 0)
DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0, 15, 8)

/* DDRPHY_REG_RK_B0_RXDVS4 */
DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0, 8, 0)
DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0, 24, 16)

/* DDRPHY_REG_RK_B0_RXDVS2 */
DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0, 17, 16)
DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0, 19, 18)
DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 23)
DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0, 25, 24)
DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0, 27, 26)
DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 28)
DEFINE_BIT(RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0, 29)
DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 31, 30)

/* DDRPHY_REG_RK_B0_RXDVS1 */
DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG, 15, 0)
DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD, 31, 16)

/* DDRPHY_REG_RK_B1_RXDVS3 */
DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1, 7, 0)
DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1, 15, 8)

/* DDRPHY_REG_RK_B1_RXDVS4 */
DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1, 8, 0)
DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1, 24, 16)

/* DDRPHY_REG_RK_B1_RXDVS2 */
DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1, 17, 16)
DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1, 19, 18)
DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 23)
DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1, 25, 24)
DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1, 27, 26)
DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 28)
DEFINE_BIT(RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1, 29)
DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 31, 30)

/* DDRPHY_REG_RK_B1_RXDVS1 */
DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG, 15, 0)
DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD, 31, 16)

/* DDRPHY_REG_MISC_CG_CTRL1 */
DEFINE_BITFIELD(MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL, 31, 0)

/* DDRPHY_REG_B0_RXDVS1 */
DEFINE_BIT(B0_RXDVS1_F_LEADLAG_TRACK_B0, 15)
DEFINE_BIT(B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0, 17)

/* DDRPHY_REG_B1_RXDVS1 */
DEFINE_BIT(B1_RXDVS1_F_LEADLAG_TRACK_B1, 15)
DEFINE_BIT(B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1, 17)

/* DRAMC_REG_DLLFRZ_CTRL */
DEFINE_BIT(DLLFRZ_CTRL_INPUTRXTRACK_BLOCK, 0)
DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 1)
DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_BLOCKLONG, 2)
DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ, 7)
DEFINE_BIT(DLLFRZ_CTRL_UPDBYWR, 8)

/* DDRPHY_REG_MISC_RG_DFS_CTRL */
DEFINE_BIT(MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 0)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN, 2)
DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, 7, 4)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 8)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 9)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 10)
DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, 17, 16)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 18)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 19)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 23)
DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 24)

/* DDRPHY_REG_MISC_CTRL4 */
DEFINE_BIT(MISC_CTRL4_R_OPT2_MPDIV_CG, 0)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_MCK, 1)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQM, 2)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQS, 3)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQ, 4)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQSIEN, 5)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CMD, 6)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CLK, 7)
DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CS, 8)

/* DDRPHY_REG_MISC_CTRL3 */
DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CMD_OPT, 1, 0)
DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CLK_OPT, 3, 2)
DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 4)
DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 5)
DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 6)
DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQ_OPT, 17, 16)
DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQS_OPT, 19, 18)
DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 20)
DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 21)
DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 22)
DEFINE_BIT(MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 26)
DEFINE_BIT(MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 27)

/* DDRPHY_REG_MISC_CG_CTRL5 */
DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 16)
DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 17)
DEFINE_BIT(MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 18)
DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 20)
DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 21)
DEFINE_BIT(MISC_CG_CTRL5_R_CA_PI_DCM_EN, 22)

/* DRAMC_REG_RX_CG_SET0 */
DEFINE_BIT(RX_CG_SET0_RDATCKAR, 30)
DEFINE_BIT(RX_CG_SET0_RDYCKAR, 31)

/* DRAMC_REG_SREF_DPD_CTRL */
DEFINE_BIT(SREF_DPD_CTRL_LPSM_BYPASS_B, 7)
DEFINE_BIT(SREF_DPD_CTRL_CLR_EN, 9)
DEFINE_BIT(SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN, 10)
DEFINE_BIT(SREF_DPD_CTRL_SREF_PRD_OPT, 11)
DEFINE_BIT(SREF_DPD_CTRL_SREF_CG_OPT, 12)
DEFINE_BIT(SREF_DPD_CTRL_SRFPD_DIS, 13)
DEFINE_BITFIELD(SREF_DPD_CTRL_SREFDLY, 19, 16)
DEFINE_BIT(SREF_DPD_CTRL_SREF_HW_EN, 22)
DEFINE_BIT(SREF_DPD_CTRL_CMDCKAR, 26)
DEFINE_BIT(SREF_DPD_CTRL_GT_SYNC_MASK, 29)
DEFINE_BIT(SREF_DPD_CTRL_DAT_SYNC_MASK, 30)
DEFINE_BIT(SREF_DPD_CTRL_PHY_SYNC_MASK, 31)

/* DRAMC_REG_DCM_CTRL0 */
DEFINE_BIT(DCM_CTRL0_BCLKAR, 2)

/* DRAMC_REG_TX_CG_SET0 */
DEFINE_BIT(TX_CG_SET0_SELPH_4LCG_DIS, 0)
DEFINE_BIT(TX_CG_SET0_SELPH_CG_DIS, 1)
DEFINE_BIT(TX_CG_SET0_DWCLKRUN, 2)
DEFINE_BIT(TX_CG_SET0_WDATA_CG_DIS, 3)
DEFINE_BIT(TX_CG_SET0_TX_ATK_CLKRUN, 4)
DEFINE_BIT(TX_CG_SET0_PSELAR, 31)

/* DRAMC_REG_SCSMCTRL_CG */
DEFINE_BIT(SCSMCTRL_CG_SCARB_SM_CGAR, 30)
DEFINE_BIT(SCSMCTRL_CG_SCSM_CGAR, 31)

/* DRAMC_REG_TX_TRACKING_SET0 */
DEFINE_BIT(TX_TRACKING_SET0_TX_TRACKING_OPT, 15)
DEFINE_BIT(TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 16)
DEFINE_BIT(TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 17)
DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 18)
DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 19)
DEFINE_BIT(TX_TRACKING_SET0_HMRRSEL_CGAR, 21)
DEFINE_BIT(TX_TRACKING_SET0_RDDQSOSC_CGAR, 22)

/* DRAMC_REG_ZQ_SET0 */
DEFINE_BITFIELD(ZQ_SET0_ZQCSOP, 7, 0)
DEFINE_BITFIELD(ZQ_SET0_ZQCSAD, 15, 8)
DEFINE_BITFIELD(ZQ_SET0_ZQCS_MASK_SEL, 18, 16)
DEFINE_BIT(ZQ_SET0_ZQCS_MASK_SEL_CGAR, 19)
DEFINE_BIT(ZQ_SET0_ZQMASK_CGAR, 20)
DEFINE_BIT(ZQ_SET0_ZQCSMASK_OPT, 21)
DEFINE_BIT(ZQ_SET0_ZQCSMASK, 29)
DEFINE_BIT(ZQ_SET0_ZQCSDUAL, 30)

/* DRAMC_REG_ACTIMING_CTRL */
DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN3, 0)
DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN2, 1)
DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN, 2)
DEFINE_BIT(ACTIMING_CTRL_REFNA_OPT, 6)
DEFINE_BIT(ACTIMING_CTRL_REFBW_FREN, 8)
DEFINE_BIT(ACTIMING_CTRL_CLKWITRFC, 9)
DEFINE_BIT(ACTIMING_CTRL_TMRRICHKDIS, 21)
DEFINE_BIT(ACTIMING_CTRL_TMRRIBYRK_DIS, 22)
DEFINE_BIT(ACTIMING_CTRL_MRRIOPT, 23)
DEFINE_BIT(ACTIMING_CTRL_FASTW2R, 24)

/* DRAMC_REG_CLKAR */
DEFINE_BITFIELD(CLKAR_REQQUE_PACG_DIS, 14, 0)
DEFINE_BIT(CLKAR_DCMREF_OPT, 24)
DEFINE_BIT(CLKAR_REQQUECLKRUN, 27)

/* DRAMC_REG_DRAMC_PD_CTRL */
DEFINE_BIT(DRAMC_PD_CTRL_DCMEN, 0)
DEFINE_BIT(DRAMC_PD_CTRL_DCMEN2, 1)
DEFINE_BIT(DRAMC_PD_CTRL_DCMENNOTRFC, 2)
DEFINE_BIT(DRAMC_PD_CTRL_PHYGLUECLKRUN, 3)
DEFINE_BIT(DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 5)
DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 6)
DEFINE_BIT(DRAMC_PD_CTRL_PG_DCM_OPT, 9)
DEFINE_BIT(DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 12)
DEFINE_BIT(DRAMC_PD_CTRL_TCKFIXON, 13)
DEFINE_BIT(DRAMC_PD_CTRL_PHYCLKDYNGEN, 30)
DEFINE_BIT(DRAMC_PD_CTRL_COMBCLKCTRL, 31)

/* DRAMC_REG_TEST2_A3 */
DEFINE_BIT(TEST2_A3_ADRDECEN_TARKMODE, 5)
DEFINE_BIT(TEST2_A3_TESTAUDPAT, 7)
DEFINE_BIT(TEST2_A3_TESTCLKRUN, 8)
DEFINE_BIT(TEST2_A3_PAT_SHIFT_SW_EN, 11)
DEFINE_BIT(TEST2_A3_TEST2_PAT_SHIFT, 15)
DEFINE_BIT(TEST2_A3_TEST_AID_EN, 16)
DEFINE_BIT(TEST2_A3_HFIDPAT, 17)
DEFINE_BIT(TEST2_A3_AUTO_GEN_PAT, 18)
DEFINE_BIT(TEST2_A3_TEST2WREN2_HW_EN, 28)
DEFINE_BIT(TEST2_A3_TEST1, 29)
DEFINE_BIT(TEST2_A3_TEST2R, 30)
DEFINE_BIT(TEST2_A3_TEST2W, 31)

/* DRAMC_REG_DVFS_CTRL0 */
DEFINE_BIT(DVFS_CTRL0_R_DRAMC_CHA, 0)
DEFINE_BIT(DVFS_CTRL0_SHU_PHYRST_SEL, 1)
DEFINE_BIT(DVFS_CTRL0_R_DVFS_SREF_OPT, 5)
DEFINE_BIT(DVFS_CTRL0_HWSET_WLRL, 8)
DEFINE_BIT(DVFS_CTRL0_MR13_SHU_EN, 9)
DEFINE_BIT(DVFS_CTRL0_VRCG_EN, 10)
DEFINE_BIT(DVFS_CTRL0_DVFS_RXFIFOST_SKIP, 13)
DEFINE_BIT(DVFS_CTRL0_DVFS_NOQUEFLUSH_EN, 15)
DEFINE_BIT(DVFS_CTRL0_DVFS_CKE_OPT, 16)
DEFINE_BIT(DVFS_CTRL0_DVFS_CG_OPT, 19)
DEFINE_BIT(DVFS_CTRL0_SCARB_PRI_OPT, 20)
DEFINE_BIT(DVFS_CTRL0_R_DMDVFSMRW_EN, 21)
DEFINE_BIT(DVFS_CTRL0_MRWWOPRA, 22)
DEFINE_BIT(DVFS_CTRL0_DVFS_SYNC_MASK, 27)

/* DDRPHY_REG_MISC_DUTYSCAN1 */
DEFINE_BIT(MISC_DUTYSCAN1_REG_SW_RST, 0)
DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1)
DEFINE_BIT(MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 2)
DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 3)
DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 8)
DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 9)
DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 10)
DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 11)
DEFINE_BIT(MISC_DUTYSCAN1_DQSERRCNT_DIS, 14)

/* DDRPHY_REG_SHU_B0_DQ8 */
DEFINE_BITFIELD(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 14, 0)
DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 15)
DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 19)
DEFINE_BIT(SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 20)
DEFINE_BIT(SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 21)
DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 22)
DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 23)
DEFINE_BIT(SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 24)
DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 26)
DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 27)
DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 28)
DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 29)
DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 30)
DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 31)

/* DDRPHY_REG_SHU_B1_DQ8 */
DEFINE_BITFIELD(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 14, 0)
DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 15)
DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 19)
DEFINE_BIT(SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 20)
DEFINE_BIT(SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 21)
DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 22)
DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 23)
DEFINE_BIT(SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 24)
DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 26)
DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 27)
DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 28)
DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 29)
DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 30)
DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 31)

/* DRAMC_REG_DDRCOMMON0 */
DEFINE_BIT(DDRCOMMON0_DISSTOP26M, 0)
DEFINE_BIT(DDRCOMMON0_TRCDEARLY, 3)
DEFINE_BIT(DDRCOMMON0_BK8EN, 8)
DEFINE_BIT(DDRCOMMON0_LPDDR4EN, 19)
DEFINE_BIT(DDRCOMMON0_LPDDR5EN, 20)

/* DRAMC_REG_RX_SET0 */
DEFINE_BIT(RX_SET0_RDATRST, 0)
DEFINE_BIT(RX_SET0_PRE_DLE_VLD_OPT, 1)
DEFINE_BITFIELD(RX_SET0_DATLAT_PDLE_TH, 4, 2)
DEFINE_BIT(RX_SET0_SMRR_UPD_OLD, 6)
DEFINE_BIT(RX_SET0_DM4TO1MODE, 31)

/* DRAMC_REG_REFCTRL0 */
DEFINE_BITFIELD(REFCTRL0_PBREF_BK_REFA_NUM, 2, 0)
DEFINE_BIT(REFCTRL0_PBREF_BK_REFA_ENA, 3)
DEFINE_BIT(REFCTRL0_DMPGVLD_IG, 8)
DEFINE_BIT(REFCTRL0_KEEP_PBREF_OPT, 9)
DEFINE_BIT(REFCTRL0_KEEP_PBREF, 10)
DEFINE_BITFIELD(REFCTRL0_DISBYREFNUM, 14, 12)
DEFINE_BIT(REFCTRL0_PBREF_DISBYREFNUM, 16)
DEFINE_BIT(REFCTRL0_PBREF_DISBYRATE, 17)
DEFINE_BITFIELD(REFCTRL0_REF_PREGATE_CNT, 27, 24)
DEFINE_BIT(REFCTRL0_REFDIS, 29)

/* DRAMC_REG_REFCTRL1 */
DEFINE_BIT(REFCTRL1_PB2AB_OPT, 0)
DEFINE_BIT(REFCTRL1_REFPENDINGINT_OPT1, 3)
DEFINE_BIT(REFCTRL1_REF_QUE_AUTOSAVE_EN, 5)
DEFINE_BIT(REFCTRL1_REFPEND_OPT1, 6)
DEFINE_BIT(REFCTRL1_REFPEND_OPT2, 7)
DEFINE_BIT(REFCTRL1_REFPB2AB_IGZQCS, 8)
DEFINE_BIT(REFCTRL1_REFRATE_MON_CLR, 11)
DEFINE_BIT(REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 13)
DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA, 14)
DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA, 15)
DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA, 24)
DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 25)
DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA, 26)
DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA, 27)

/* DRAMC_REG_REFCTRL2 */
DEFINE_BITFIELD(REFCTRL2_MR4INT_TH, 4, 0)
DEFINE_BITFIELD(REFCTRL2_REF_OVERHEAD_RATE, 31, 16)

/* DRAMC_REG_DRAMCTRL */
DEFINE_BIT(DRAMCTRL_CTOREQ_HPRI_OPT, 0)
DEFINE_BIT(DRAMCTRL_ADRDECEN, 2)
DEFINE_BIT(DRAMCTRL_ADRBIT3DEC, 3)
DEFINE_BIT(DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 8)
DEFINE_BIT(DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 9)
DEFINE_BIT(DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 10)
DEFINE_BIT(DRAMCTRL_AG0MWR, 12)
DEFINE_BIT(DRAMCTRL_DYNMWREN, 13)
DEFINE_BIT(DRAMCTRL_PREALL_OPTION, 19)
DEFINE_BIT(DRAMCTRL_REQQUE_THD_EN, 26)
DEFINE_BIT(DRAMCTRL_SHORTQ_OPT, 31)

/* DRAMC_REG_ARBCTL */
DEFINE_BITFIELD(ARBCTL_MAXPENDCNT, 7, 0)
DEFINE_BIT(ARBCTL_WDATACNTDIS, 9)

/* DRAMC_REG_DRAM_CLK_CTRL */
DEFINE_BIT(DRAM_CLK_CTRL_CLK_EN, 0)

/* DRAMC_REG_RKCFG */
DEFINE_BIT(RKCFG_MRS2RK, 10)
DEFINE_BIT(RKCFG_CKE2RANK, 12)

/* DRAMC_REG_CKECTRL */
DEFINE_BIT(CKECTRL_CKE2RANK_OPT3, 1)
DEFINE_BIT(CKECTRL_CKE1FIXON, 4)
DEFINE_BIT(CKECTRL_CKE1FIXOFF, 5)
DEFINE_BIT(CKECTRL_CKEFIXON, 6)
DEFINE_BIT(CKECTRL_CKEFIXOFF, 7)
DEFINE_BIT(CKECTRL_CKE2RANK_OPT5, 8)
DEFINE_BIT(CKECTRL_CKE2RANK_OPT6, 9)
DEFINE_BIT(CKECTRL_CKE2RANK_OPT7, 10)
DEFINE_BIT(CKECTRL_CKE2RANK_OPT8, 11)
DEFINE_BIT(CKECTRL_CKETIMER_SEL, 13)
DEFINE_BIT(CKECTRL_FASTWAKE_SEL, 14)
DEFINE_BIT(CKECTRL_CKEWAKE_SEL, 15)
DEFINE_BIT(CKECTRL_CKEPBDIS, 22)
DEFINE_BIT(CKECTRL_CKELCKFIX, 23)
DEFINE_BIT(CKECTRL_CKE2RANK_OPT2, 24)
DEFINE_BIT(CKECTRL_CKE2RANK_OPT, 25)
DEFINE_BIT(CKECTRL_RUNTIMEMRRCKEFIX, 27)
DEFINE_BIT(CKECTRL_RUNTIMEMRRMIODIS, 28)
DEFINE_BIT(CKECTRL_CKEON, 31)

/* DRAMC_REG_SCHEDULER_COM */
DEFINE_BIT(SCHEDULER_COM_RWOFOEN, 0)
DEFINE_BIT(SCHEDULER_COM_RWHPRICTL, 4)
DEFINE_BIT(SCHEDULER_COM_RWSPLIT, 5)
DEFINE_BIT(SCHEDULER_COM_MWHPRIEN, 6)
DEFINE_BIT(SCHEDULER_COM_DISRDPHASE1, 8)
DEFINE_BIT(SCHEDULER_COM_PBR2PBR_OPT, 9)

/* DRAMC_REG_PERFCTL0 */
DEFINE_BIT(PERFCTL0_EBG_EN, 0)
DEFINE_BIT(PERFCTL0_RWHPRIEN, 8)
DEFINE_BIT(PERFCTL0_RWLLATEN, 9)
DEFINE_BIT(PERFCTL0_RWAGEEN, 10)
DEFINE_BIT(PERFCTL0_EMILLATEN, 11)
DEFINE_BIT(PERFCTL0_WFLUSHEN, 14)
DEFINE_BIT(PERFCTL0_REORDER_MODE, 18)
DEFINE_BIT(PERFCTL0_REORDEREN, 19)

/* DRAMC_REG_HW_MRR_FUN */
DEFINE_BIT(HW_MRR_FUN_TMRR_ENA, 0)
DEFINE_BIT(HW_MRR_FUN_TRCDMRR_EN, 1)
DEFINE_BIT(HW_MRR_FUN_TRPMRR_EN, 2)
DEFINE_BIT(HW_MRR_FUN_MANTMRR_EN, 3)
DEFINE_BIT(HW_MRR_FUN_TR2MRR_ENA, 4)
DEFINE_BIT(HW_MRR_FUN_R2MRRHPRICTL, 5)
DEFINE_BIT(HW_MRR_FUN_MRR_HW_HIPRI, 11)

/* DRAMC_REG_MPC_OPTION */
DEFINE_BIT(MPC_OPTION_MPCRKEN, 17)

/* DRAMC_REG_MPC_CTRL */
DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT, 0)
DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT1, 1)
DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT2, 2)
DEFINE_BIT(MPC_CTRL_ZQ_BLOCKALE_OPT, 3)
DEFINE_BIT(MPC_CTRL_REFR_BLOCKEN, 5)
DEFINE_BIT(MPC_CTRL_RTMRW_HPRI_EN, 6)
DEFINE_BIT(MPC_CTRL_RTSWCMD_HPRI_EN, 7)

/* DRAMC_REG_HMR4 */
DEFINE_BIT(HMR4_HMR4_TOG_OPT, 1)
DEFINE_BIT(HMR4_SPDR_MR4_OPT, 2)
DEFINE_BIT(HMR4_HMR4_BYTEMODE_EN, 5)
DEFINE_BIT(HMR4_MR4INT_LIMITEN, 6)
DEFINE_BIT(HMR4_REFR_PERIOD_OPT, 7)
DEFINE_BIT(HMR4_REFRDIS, 8)
DEFINE_BIT(HMR4_REFRCNT_OPT, 9)

/* DRAMC_REG_RK_TEST2_A1 */
DEFINE_BITFIELD(RK_TEST2_A1_TEST2_BASE, 31, 3)

/* DRAMC_REG_TEST2_A2 */
DEFINE_BITFIELD(TEST2_A2_TEST2_OFF, 31, 4)

/* DRAMC_REG_TEST2_A4 */
DEFINE_BITFIELD(TEST2_A4_TESTAUDINC, 4, 0)
DEFINE_BIT(TEST2_A4_TESTSSOPAT, 6)
DEFINE_BIT(TEST2_A4_TESTSSOXTALKPAT, 7)
DEFINE_BITFIELD(TEST2_A4_TESTAUDINIT, 12, 8)
DEFINE_BIT(TEST2_A4_TESTAUDBITINV, 14)
DEFINE_BIT(TEST2_A4_TESTAUDMODE, 15)
DEFINE_BIT(TEST2_A4_TESTXTALKPAT, 16)
DEFINE_BIT(TEST2_A4_TEST_REQ_LEN1, 17)
DEFINE_BITFIELD(TEST2_A4_TESTAGENTRK, 25, 24)
DEFINE_BITFIELD(TEST2_A4_TESTAGENTRKSEL, 30, 28)

/* DRAMC_REG_CMD_DEC_CTRL0 */
DEFINE_BIT(CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 4)
DEFINE_BITFIELD(CMD_DEC_CTRL0_RKMODE, 10, 8)

/* DRAMC_REG_MISCTL0 */
DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0)
DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1)
DEFINE_BITFIELD(MISCTL0_PG_WAKEUP_OPT, 15, 14)
DEFINE_BIT(MISCTL0_PAGDIS, 17)
DEFINE_BIT(MISCTL0_REFA_ARB_EN2, 19)
DEFINE_BIT(MISCTL0_PBC_ARB_E1T, 23)
DEFINE_BIT(MISCTL0_PBC_ARB_EN, 24)
DEFINE_BIT(MISCTL0_EMIPREEN, 27)
DEFINE_BIT(MISCTL0_REFP_ARB_EN2, 31)

/* DRAMC_REG_SCSMCTRL */
DEFINE_BIT(SCSMCTRL_SC_PG_UPD_OPT, 0)
DEFINE_BIT(SCSMCTRL_SC_PG_MAN_DIS, 1)

/* DRAMC_REG_SHUCTRL1 */
DEFINE_BITFIELD(SHUCTRL1_FC_PRDCNT, 7, 0)
DEFINE_BITFIELD(SHUCTRL1_CKFSPE_PRDCNT, 15, 8)
DEFINE_BITFIELD(SHUCTRL1_CKFSPX_PRDCNT, 23, 16)
DEFINE_BITFIELD(SHUCTRL1_VRCGEN_PRDCNT, 31, 24)

/* DRAMC_REG_DVFS_TIMING_CTRL1 */
DEFINE_BITFIELD(DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 7, 0)
DEFINE_BITFIELD(DVFS_TIMING_CTRL1_DMSHU_CNT, 21, 16)

/* DRAMC_REG_REFPEND1 */
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH0, 3, 0)
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH1, 7, 4)
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH2, 11, 8)
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH3, 15, 12)
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH4, 19, 16)
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH5, 23, 20)
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH6, 27, 24)
DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH7, 31, 28)

/* DRAMC_REG_CBT_WLEV_CTRL1 */
DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAINLAT, 14, 11)
DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAIN_INTV, 22, 15)
DEFINE_BITFIELD(CBT_WLEV_CTRL1_TCMDO1LAT, 30, 23)

/* DRAMC_REG_TX_SET0 */
DEFINE_BITFIELD(TX_SET0_TXRANK, 1, 0)
DEFINE_BIT(TX_SET0_TXRANKFIX, 2)
DEFINE_BIT(TX_SET0_OE_DOWNGRADE, 6)
DEFINE_BIT(TX_SET0_WPRE2T, 22)
DEFINE_BIT(TX_SET0_DRSCLR_EN, 24)
DEFINE_BIT(TX_SET0_DRSCLR_RK0_EN, 25)
DEFINE_BIT(TX_SET0_RK_SCINPUT_OPT, 30)

/* DRAMC_REG_DQSOSCR */
DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7)
DEFINE_BIT(DQSOSCR_SREF_TXUI_RELOAD_OPT, 23)
DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24)
DEFINE_BIT(DQSOSCR_R_DMDQS2DQ_FILT_OPT, 26)
DEFINE_BIT(DQSOSCR_SREF_TXPI_RELOAD_OPT, 27)
DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31)

/* DRAMC_REG_DUMMY_RD */
DEFINE_BIT(DUMMY_RD_DUMMY_RD_SW, 4)
DEFINE_BIT(DUMMY_RD_DMY_WR_DBG, 6)
DEFINE_BIT(DUMMY_RD_DMY_RD_DBG, 7)
DEFINE_BIT(DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS, 15)
DEFINE_BITFIELD(DUMMY_RD_RANK_NUM, 17, 16)
DEFINE_BIT(DUMMY_RD_DUMMY_RD_EN, 20)
DEFINE_BIT(DUMMY_RD_SREF_DMYRD_EN, 21)
DEFINE_BIT(DUMMY_RD_DQSG_DMYRD_EN, 22)
DEFINE_BIT(DUMMY_RD_DQSG_DMYWR_EN, 23)
DEFINE_BIT(DUMMY_RD_DUMMY_RD_PA_OPT, 24)
DEFINE_BIT(DUMMY_RD_DMYRD_REORDER_DIS, 27)

/* DRAMC_REG_DUMMY_RD_INTV */
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT0, 0)
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT1, 1)
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT2, 2)
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT3, 3)
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT4, 4)
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT5, 5)
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT6, 6)
DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT7, 7)

/* DRAMC_REG_RK_DQSOSC */
DEFINE_BIT(RK_DQSOSC_RK0_BYTE_MODE, 29)
DEFINE_BIT(RK_DQSOSC_DQSOSCR_RK0EN, 30)

/* DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0 */
DEFINE_BIT(TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 31)

/* DRAMC_REG_SWCMD_CTRL1 */
DEFINE_BIT(SWCMD_CTRL1_RDDQC_LP_ENB, 2)
DEFINE_BIT(SWCMD_CTRL1_WRFIFO_MODE2, 31)

/* DRAMC_REG_DBG_CMDDEC_CMDSEL0 */
DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK0_10GBEN, 0)
DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK1_10GBEN, 1)

/* DRAMC_REG_DBIWR_PROTECT */
DEFINE_BIT(DBIWR_PROTECT_DBIWR_IMP_EN, 0)
DEFINE_BIT(DBIWR_PROTECT_DBIWR_PINMUX_EN, 1)
DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B0, 23, 16)
DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B1, 31, 24)

/* DDRPHY_REG_MISC_SRAM_DMA0 */
DEFINE_BIT(MISC_SRAM_DMA0_SW_DMA_FIRE, 0)
DEFINE_BIT(MISC_SRAM_DMA0_SW_MODE, 1)
DEFINE_BIT(MISC_SRAM_DMA0_APB_WR_MODE, 2)
DEFINE_BIT(MISC_SRAM_DMA0_SRAM_WR_MODE, 3)
DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, 7, 4)
DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, 11, 8)
DEFINE_BITFIELD(MISC_SRAM_DMA0_PENABLE_LAT_WR, 15, 14)
DEFINE_BIT(MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA, 16)
DEFINE_BIT(MISC_SRAM_DMA0_KEEP_APB_ARB_ENA, 17)
DEFINE_BIT(MISC_SRAM_DMA0_DMA_TIMER_EN, 18)
DEFINE_BIT(MISC_SRAM_DMA0_SW_STEP_EN_MODE, 23)
DEFINE_BITFIELD(MISC_SRAM_DMA0_APB_SLV_SEL, 29, 28)

/* DDRPHY_MD32_REG_SSPM_MCLK_DIV */
DEFINE_BIT(SSPM_MCLK_DIV_MCLK_DCM_EN, 8)

/* DDRPHY_REG_CA_CMD7 */
DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN, 0)
DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_UP, 1)
DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_DN, 2)
DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_UP, 3)
DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_DN, 4)
DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_UP, 5)
DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_DN, 6)
DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_UP, 7)
DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 16)

/* DDRPHY_REG_B0_DQ7 */
DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0, 0)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0, 1)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0, 2)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0, 3)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0, 4)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0, 5)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_DN_B0, 6)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_UP_B0, 7)
DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 16)

/* DDRPHY_REG_B1_DQ7 */
DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1, 0)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1, 1)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1, 2)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1, 3)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1, 4)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1, 5)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_DN_B1, 6)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_UP_B1, 7)
DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 16)

/* DDRPHY_REG_B0_DQ11 */
DEFINE_BIT(B0_DQ11_DMY_DQ11_B0, 0)

/* DDRPHY_REG_B1_DQ11 */
DEFINE_BIT(B1_DQ11_DMY_DQ11_B1, 0)

/* DDRPHY_REG_MISC_SRAM_DMA1 */
DEFINE_BITFIELD(MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN, 16, 0)
DEFINE_BIT(MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS, 19)
DEFINE_BITFIELD(MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL, 23, 20)

/* DDRPHY_REG_MISC_CG_CTRL7 */
DEFINE_BIT(MISC_CG_CTRL7_CK_BFE_DCM_EN, 11)
DEFINE_BIT(MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL, 16)

/* DDRPHY_REG_MISC_DVFSCTL2 */
DEFINE_BIT(MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS, 3)
DEFINE_BIT(MISC_DVFSCTL2_RG_DLL_SHUFFLE, 4)
DEFINE_BIT(MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 5)
DEFINE_BIT(MISC_DVFSCTL2_RG_MRW_AFTER_DFS, 8)
DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 9)
DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_DLL_CHA, 12)
DEFINE_BIT(MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION, 13)
DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_PARK_N, 14)
DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_OPTION, 15)
DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 29)
DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL, 31)

/* DDRPHY_REG_MISC_DVFSCTL3 */
DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 4)
DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK, 5)
DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 6)
DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 7)
DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 9, 8)
DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 11, 10)
DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 17, 12)
DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 27, 22)
DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 31, 28)

/* DDRPHY_REG_MISC_CLK_CTRL */
DEFINE_BIT(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0)
DEFINE_BIT(MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 1)
DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 10, 9)
DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 13, 12)

/* DDRPHY_REG_MISC_SHU_OPT */
DEFINE_BIT(MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN, 0)
DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN, 3, 2)
DEFINE_BIT(MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN, 8)
DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN, 11, 10)
DEFINE_BIT(MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN, 16)
DEFINE_BITFIELD(MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN, 19, 18)

/* DRAMC_REG_SHU_SELPH_CA1 */
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CKE, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_ODT, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RESET, 14, 12)
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_WE, 18, 16)
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CAS, 22, 20)
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RAS, 26, 24)
DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS1, 30, 28)

/* DRAMC_REG_SHU_SELPH_CA2 */
DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA0, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA1, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA2, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_CKE1, 26, 24)

/* DRAMC_REG_SHU_SELPH_CA3 */
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA0, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA1, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA2, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA3, 14, 12)
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA4, 18, 16)
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA5, 22, 20)
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA6, 26, 24)
DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA7, 30, 28)

/* DRAMC_REG_SHU_SELPH_CA4 */
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA8, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA9, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA10, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA11, 14, 12)
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA12, 18, 16)
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA13, 22, 20)
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA14, 26, 24)
DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA15, 30, 28)

/* DRAMC_REG_SHU_SELPH_CA5 */
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CKE, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_ODT, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RESET, 14, 12)
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_WE, 18, 16)
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CAS, 22, 20)
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RAS, 26, 24)
DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS1, 30, 28)

/* DRAMC_REG_SHU_SELPH_CA6 */
DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA0, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA1, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA2, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_CKE1, 26, 24)

/* DRAMC_REG_SHU_SELPH_CA7 */
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12)
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16)
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20)
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA6, 26, 24)
DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA7, 30, 28)

/* DRAMC_REG_SHU_SELPH_CA8 */
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA8, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA9, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA10, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA11, 14, 12)
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA12, 18, 16)
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA13, 22, 20)
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA14, 26, 24)
DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA15, 30, 28)

/* DDRPHY_REG_SHU_MISC_DRVING2 */
DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN1, 4, 0)
DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP1, 9, 5)
DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN2, 14, 10)
DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP2, 19, 15)
DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVN1, 24, 20)
DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVP1, 29, 25)
DEFINE_BIT(SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, 31)

/* DDRPHY_REG_SHU_MISC_IMPCAL1 */
DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE, 2, 0)
DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVP, 8, 4)
DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVN, 16, 12)
DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE, 19, 17)
DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCALCNT, 27, 20)
DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALICNT, 31, 28)

/* DDRPHY_REG_SHU_CA_CMD12 */
DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_REV, 7, 0)
DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, 14, 8)
DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, 22, 16)
DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_DRV05, 23)
DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, 30, 24)
DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_UNTERM_EN, 31)

/* DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1 */
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, 0)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, 1)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, 2)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, 4)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, 5)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, 6)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 8)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 9)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 10)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 12)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 13)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 14)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 16)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 17)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 18)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS, 20)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS, 21)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS, 22)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, 28)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, 29)
DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, 30)

/* DDRPHY_REG_SHU_MISC_DRVING6 */
DEFINE_BITFIELD(SHU_MISC_DRVING6_IMP_TXDLY_CMD, 5, 0)

/* DRAMC_REG_SHU_COMMON0 */
DEFINE_BIT(SHU_COMMON0_FREQDIV4, 0)
DEFINE_BIT(SHU_COMMON0_FDIV2, 1)
DEFINE_BIT(SHU_COMMON0_DM64BITEN, 4)
DEFINE_BIT(SHU_COMMON0_BL4, 10)
DEFINE_BIT(SHU_COMMON0_BC4OTF, 12)

/* DRAMC_REG_SHU_ACTIMING_CONF */
DEFINE_BITFIELD(SHU_ACTIMING_CONF_SCINTV, 5, 0)
DEFINE_BITFIELD(SHU_ACTIMING_CONF_REFBW_FR, 25, 16)
DEFINE_BIT(SHU_ACTIMING_CONF_TREFBWIG, 31)

/* DRAMC_REG_SHU_DCM_CTRL0 */
DEFINE_BIT(SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 7)
DEFINE_BITFIELD(SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 10, 8)
DEFINE_BITFIELD(SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 15, 12)
DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 19, 16)
DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 23, 20)
DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE2, 29)
DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE, 31)

/* DRAMC_REG_SHU_CONF0 */
DEFINE_BITFIELD(SHU_CONF0_DMPGTIM, 6, 0)
DEFINE_BIT(SHU_CONF0_ADVPREEN, 7)
DEFINE_BIT(SHU_CONF0_PBREFEN, 8)
DEFINE_BITFIELD(SHU_CONF0_REFTHD, 15, 12)

/* DRAMC_REG_SHU_MATYPE */
DEFINE_BITFIELD(SHU_MATYPE_MATYPE, 1, 0)

/* DRAMC_REG_SHU_SCHEDULER */
DEFINE_BIT(SHU_SCHEDULER_DUALSCHEN, 2)

/* DRAMC_REG_SHU_TX_SET0 */
DEFINE_BITFIELD(SHU_TX_SET0_DQOE_CNT, 3, 0)
DEFINE_BIT(SHU_TX_SET0_DQOE_OPT, 4)
DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_SEL, 7, 6)
DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_W2R_SEL, 10, 8)
DEFINE_BIT(SHU_TX_SET0_DBIWR, 12)
DEFINE_BIT(SHU_TX_SET0_WDATRGO, 13)
DEFINE_BIT(SHU_TX_SET0_WPST1P5T, 15)
DEFINE_BITFIELD(SHU_TX_SET0_OE_EXT2UI, 24, 22)
DEFINE_BITFIELD(SHU_TX_SET0_DQS2DQ_FILT_PITHRD, 30, 25)

/* DDRPHY_REG_MISC_SHU_STBCAL1 */
DEFINE_BIT(MISC_SHU_STBCAL1_STB_UPDMASK_EN, 11)
DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_UPDMASKCYC, 15, 12)
DEFINE_BIT(MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL, 16)
DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO, 25, 20)

/* DDRPHY_REG_MISC_SHU_STBCAL */
DEFINE_BITFIELD(MISC_SHU_STBCAL_DMSTBLAT, 3, 0)
DEFINE_BITFIELD(MISC_SHU_STBCAL_PICGLAT, 6, 4)
DEFINE_BIT(MISC_SHU_STBCAL_DQSG_MODE, 8)
DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 9)

/* DDRPHY_REG_MISC_SHU_RANKCTL */
DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 3, 0)
DEFINE_BIT(MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 4)
DEFINE_BIT(MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 15)
DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_STB, 19, 16)
DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL, 23, 20)
DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24)
DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_PHY, 31, 28)

/* DRAMC_REG_SHU_MISC */
DEFINE_BITFIELD(SHU_MISC_REQQUE_MAXCNT, 3, 0)
DEFINE_BITFIELD(SHU_MISC_DCMDLYREF, 18, 16)
DEFINE_BIT(SHU_MISC_DAREFEN, 30)

/* DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL */
DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 2, 0)
DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, 6, 4)

/* DDRPHY_REG_MISC_SHU_RODTENSTB */
DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 0)
DEFINE_BIT(MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE, 1)
DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 3)
DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE, 4)
DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 5)
DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET, 11, 8)
DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET, 15, 12)
DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_EXT, 31, 16)

/* DDRPHY_REG_MISC_SHU_RODTENSTB1 */
DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD, 5, 4)
DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL, 7, 6)

/* DDRPHY_REG_MISC_SHU_RX_SELPH_MODE */
DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE, 1, 0)
DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE, 5, 4)
DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE, 7, 6)

/* DDRPHY_REG_MISC_SHU_RDAT1 */
DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT, 0)
DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT, 1)
DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT, 2)

/* DRAMC_REG_SHURK_CKE_CTRL */
DEFINE_BITFIELD(SHURK_CKE_CTRL_CKE_DBE_CNT, 3, 0)

/* DDRPHY_REG_MISC_SHU_DQSG_RETRY1 */
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET, 0)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_EN, 1)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS, 2)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ONCE, 3)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_3TIMES, 4)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_1RANK, 5)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK, 6)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE, 7)
DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT, 11, 8)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE, 12)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN, 13)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE, 14)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA, 15)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK, 20)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE, 21)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND, 22)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING, 23)
DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM, 25, 24)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY, 28)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE, 29)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK, 30)
DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE, 31)

/* DRAMC_REG_SHU_HWSET_MR13 */
DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_MRSMA, 12, 0)
DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_OP, 23, 16)

/* DRAMC_REG_SHU_HWSET_VRCG */
DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 12, 0)
DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_OP, 23, 16)
DEFINE_BITFIELD(SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 31, 24)

/* DRAMC_REG_SHU_HWSET_MR2 */
DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_MRSMA, 12, 0)
DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_OP, 23, 16)

/* DDRPHY_REG_MISC_SHU_DVFSDLL */
DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL, 0)
DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL, 1)
DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_DLL_IDLE, 10, 4)
DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE, 22, 16)

/* DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL */
DEFINE_BIT(SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0)

/* DRAMC_REG_SHU_ACTIM1 */
DEFINE_BITFIELD(SHU_ACTIM1_TRPAB, 3, 0)
DEFINE_BITFIELD(SHU_ACTIM1_TMRWCKEL, 7, 4)
DEFINE_BITFIELD(SHU_ACTIM1_TRP, 11, 8)
DEFINE_BITFIELD(SHU_ACTIM1_TRAS, 21, 16)
DEFINE_BITFIELD(SHU_ACTIM1_TRC, 28, 24)

/* DRAMC_REG_SHU_ACTIM3 */
DEFINE_BITFIELD(SHU_ACTIM3_TRFCPB, 7, 0)
DEFINE_BITFIELD(SHU_ACTIM3_MANTMRR, 11, 8)
DEFINE_BITFIELD(SHU_ACTIM3_TR2MRR, 15, 12)
DEFINE_BITFIELD(SHU_ACTIM3_TRFC, 23, 16)
DEFINE_BITFIELD(SHU_ACTIM3_TWTR_L, 29, 24)

/* DRAMC_REG_SHU_ACTIM2 */
DEFINE_BITFIELD(SHU_ACTIM2_TXP, 3, 0)
DEFINE_BITFIELD(SHU_ACTIM2_TMRRI, 8, 4)
DEFINE_BITFIELD(SHU_ACTIM2_TRTP, 14, 12)
DEFINE_BITFIELD(SHU_ACTIM2_TR2W, 21, 16)
DEFINE_BITFIELD(SHU_ACTIM2_TFAW, 28, 24)

/* DRAMC_REG_SHU_ACTIM0 */
DEFINE_BITFIELD(SHU_ACTIM0_TWTR, 5, 0)
DEFINE_BITFIELD(SHU_ACTIM0_TWR, 15, 8)
DEFINE_BITFIELD(SHU_ACTIM0_TRRD, 18, 16)
DEFINE_BITFIELD(SHU_ACTIM0_TRCD, 27, 24)
DEFINE_BITFIELD(SHU_ACTIM0_CKELCKCNT, 31, 28)

/* DRAMC_REG_SHU_ACTIM5 */
DEFINE_BITFIELD(SHU_ACTIM5_TR2PD, 6, 0)
DEFINE_BITFIELD(SHU_ACTIM5_TWTPD, 14, 8)
DEFINE_BITFIELD(SHU_ACTIM5_TPBR2PBR, 23, 16)
DEFINE_BITFIELD(SHU_ACTIM5_TPBR2ACT, 29, 28)

/* DRAMC_REG_SHU_ACTIM6 */
DEFINE_BITFIELD(SHU_ACTIM6_TZQLAT2, 4, 0)
DEFINE_BITFIELD(SHU_ACTIM6_TMRD, 11, 8)
DEFINE_BITFIELD(SHU_ACTIM6_TMRW, 15, 12)
DEFINE_BITFIELD(SHU_ACTIM6_TW2MRW, 25, 20)
DEFINE_BITFIELD(SHU_ACTIM6_TR2MRW, 31, 26)

/* DRAMC_REG_SHU_ACTIM4 */
DEFINE_BITFIELD(SHU_ACTIM4_TXREFCNT, 9, 0)
DEFINE_BITFIELD(SHU_ACTIM4_TMRR2MRW, 15, 10)
DEFINE_BITFIELD(SHU_ACTIM4_TMRR2W, 21, 16)
DEFINE_BITFIELD(SHU_ACTIM4_TZQCS, 31, 24)

/* DRAMC_REG_SHU_CKECTRL */
DEFINE_BIT(SHU_CKECTRL_TPDE_05T, 0)
DEFINE_BIT(SHU_CKECTRL_TPDX_05T, 1)
DEFINE_BITFIELD(SHU_CKECTRL_TPDE, 14, 12)
DEFINE_BITFIELD(SHU_CKECTRL_TPDX, 18, 16)
DEFINE_BITFIELD(SHU_CKECTRL_TCKEPRD, 22, 20)
DEFINE_BITFIELD(SHU_CKECTRL_TCKESRX, 25, 24)

/* DRAMC_REG_SHU_ACTIM_XRT */
DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2R, 4, 0)
DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2W, 13, 8)
DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2R, 19, 16)
DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2W, 28, 24)

/* DRAMC_REG_SHU_AC_TIME_05T */
DEFINE_BIT(SHU_AC_TIME_05T_TRC_05T, 0)
DEFINE_BIT(SHU_AC_TIME_05T_TRFCPB_05T, 1)
DEFINE_BIT(SHU_AC_TIME_05T_TRFC_05T, 2)
DEFINE_BIT(SHU_AC_TIME_05T_TPBR2PBR_05T, 3)
DEFINE_BIT(SHU_AC_TIME_05T_TXP_05T, 4)
DEFINE_BIT(SHU_AC_TIME_05T_TRTP_05T, 5)
DEFINE_BIT(SHU_AC_TIME_05T_TRCD_05T, 6)
DEFINE_BIT(SHU_AC_TIME_05T_TRP_05T, 7)
DEFINE_BIT(SHU_AC_TIME_05T_TRPAB_05T, 8)
DEFINE_BIT(SHU_AC_TIME_05T_TRAS_05T, 9)
DEFINE_BIT(SHU_AC_TIME_05T_TWR_M05T, 10)
DEFINE_BIT(SHU_AC_TIME_05T_TRRD_05T, 12)
DEFINE_BIT(SHU_AC_TIME_05T_TFAW_05T, 13)
DEFINE_BIT(SHU_AC_TIME_05T_TCKEPRD_05T, 14)
DEFINE_BIT(SHU_AC_TIME_05T_TR2PD_05T, 15)
DEFINE_BIT(SHU_AC_TIME_05T_TWTPD_M05T, 16)
DEFINE_BIT(SHU_AC_TIME_05T_TMRRI_05T, 17)
DEFINE_BIT(SHU_AC_TIME_05T_TMRWCKEL_05T, 18)
DEFINE_BIT(SHU_AC_TIME_05T_BGTRRD_05T, 19)
DEFINE_BIT(SHU_AC_TIME_05T_BGTCCD_05T, 20)
DEFINE_BIT(SHU_AC_TIME_05T_BGTWTR_M05T, 21)
DEFINE_BIT(SHU_AC_TIME_05T_TR2W_05T, 22)
DEFINE_BIT(SHU_AC_TIME_05T_TWTR_M05T, 23)
DEFINE_BIT(SHU_AC_TIME_05T_XRTR2W_05T, 24)
DEFINE_BIT(SHU_AC_TIME_05T_TMRD_05T, 25)
DEFINE_BIT(SHU_AC_TIME_05T_TMRW_05T, 26)
DEFINE_BIT(SHU_AC_TIME_05T_TMRR2MRW_05T, 27)
DEFINE_BIT(SHU_AC_TIME_05T_TW2MRW_05T, 28)
DEFINE_BIT(SHU_AC_TIME_05T_TR2MRW_05T, 29)
DEFINE_BIT(SHU_AC_TIME_05T_TPBR2ACT_05T, 30)
DEFINE_BIT(SHU_AC_TIME_05T_XRTW2R_M05T, 31)

/* DRAMC_REG_SHU_AC_DERATING0 */
DEFINE_BIT(SHU_AC_DERATING0_ACDERATEEN, 0)
DEFINE_BITFIELD(SHU_AC_DERATING0_TRRD_DERATE, 18, 16)
DEFINE_BITFIELD(SHU_AC_DERATING0_TRCD_DERATE, 27, 24)

/* DRAMC_REG_SHU_AC_DERATING1 */
DEFINE_BITFIELD(SHU_AC_DERATING1_TRPAB_DERATE, 3, 0)
DEFINE_BITFIELD(SHU_AC_DERATING1_TRP_DERATE, 11, 8)
DEFINE_BITFIELD(SHU_AC_DERATING1_TRAS_DERATE, 21, 16)
DEFINE_BITFIELD(SHU_AC_DERATING1_TRC_DERATE, 28, 24)

/* DRAMC_REG_SHU_AC_DERATING_05T */
DEFINE_BIT(SHU_AC_DERATING_05T_TRC_05T_DERATE, 0)
DEFINE_BIT(SHU_AC_DERATING_05T_TRCD_05T_DERATE, 6)
DEFINE_BIT(SHU_AC_DERATING_05T_TRP_05T_DERATE, 7)
DEFINE_BIT(SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 8)
DEFINE_BIT(SHU_AC_DERATING_05T_TRAS_05T_DERATE, 9)
DEFINE_BIT(SHU_AC_DERATING_05T_TRRD_05T_DERATE, 12)

/* DRAMC_REG_REFCTRL3 */
DEFINE_BITFIELD(REFCTRL3_REF_DERATING_EN, 15, 0)

/* DDRPHY_REG_MISC_SHU_RK_DQSCTL */
DEFINE_BITFIELD(MISC_SHU_RK_DQSCTL_DQSINCTL, 3, 0)

/* DDRPHY_REG_MISC_SHU_ODTCTRL */
DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN, 0)
DEFINE_BIT(MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 1)
DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODT_LAT, 7, 4)
DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 15)
DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 25, 24)
DEFINE_BIT(MISC_SHU_ODTCTRL_FIXRODT, 27)
DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_OPT, 29)
DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE2, 30)
DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE, 31)

/* DDRPHY_REG_SHU_MISC_RANK_SEL_STB */
DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0)
DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 1)
DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 3, 2)
DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 4)
DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 5)
DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 7)
DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 11, 8)
DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 19, 16)
DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 23, 20)
DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 27, 24)
DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 31, 28)

/* DDRPHY_REG_MISC_SHU_RDAT */
DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT, 4, 0)
DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL, 12, 8)
DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL_PHY, 20, 16)

/* DRAMC_REG_SHU_TX_RANKCTL */
DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 3, 0)
DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL, 7, 4)
DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 11, 8)

/* DRAMC_REG_BYPASS_FSPOP */
DEFINE_BIT(BYPASS_FSPOP_BPFSP_OPT, 16)

/* DDRPHY_MD32_REG_LPIF_FSM_CFG_1 */
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 0)
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 1)
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 2)
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 3)
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW, 4)
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND, 5)
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL, 6)
DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND, 7)

/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0 */
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_EN, 3, 2)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_EN, 5, 4)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN, 7, 6)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN, 9, 8)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_VREF_EN, 11, 10)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN, 17, 16)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN, 21, 20)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW, 23, 22)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN, 25, 24)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW, 27, 26)

/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1 */
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL, 13, 12)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL, 15, 14)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_EN, 17, 16)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN, 21, 20)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL, 29, 22)

/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3 */
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN, 1, 0)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN, 3, 2)
DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN, 5, 4)

/* DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0 */
DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN, 1)
DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN, 2)
DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN, 3)
DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN, 4)
DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN, 5)
DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN, 10)
DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW, 11)

/* DDRPHY_REG_CLRPLL0 */
DEFINE_BIT(CLRPLL0_RG_RCLRPLL_EN, 31)

/* DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 */
DEFINE_BIT(LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN, 0)

/* DDRPHY_REG_MISC_DMA_DEBUG0 */
DEFINE_BIT(MISC_DMA_DEBUG0_SRAM_DONE, 16)
DEFINE_BIT(MISC_DMA_DEBUG0_APB_DONE, 17)
DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, 29)
DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, 30)

/* DDRPHY_MD32_REG_LPIF_STATUS_4 */
DEFINE_BITFIELD(LPIF_STATUS_4_SHU_EN_ACK, 15, 14)

/* DRAMC_REG_MRR_STATUS2 */
DEFINE_BITFIELD(MRR_STATUS2_DVFS_STATE, 31, 24)

/* DDRPHY_REG_SHU_MISC_RDSEL_TRACK */
DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 4, 0)
DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 6)
DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 7)
DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 19, 8)
DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 31, 20)

/* DDRPHY_REG_MISC_SHU_PHY_RX_CTRL */
DEFINE_BIT(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 8)
DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 11, 9)
DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 15, 14)
DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 18, 16)
DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 22, 20)
DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 26, 24)
DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 30, 28)

/* DDRPHY_REG_MISC_SHU_RANK_SEL_LAT */
DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 3, 0)
DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 7, 4)
DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 11, 8)

/* DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY */
DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 3, 0)
DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 7, 4)
DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 19, 16)
DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 23, 20)

/* DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY */
DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 6, 0)

/* DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY */
DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 3, 0)
DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 7, 4)
DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 19, 16)
DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 23, 20)

/* DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY */
DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 6, 0)

/* DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY */
DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 2, 0)
DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 6, 4)
DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 18, 16)
DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 22, 20)

/* DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY */
DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 2, 0)
DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 6, 4)
DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 18, 16)
DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 22, 20)

/* DRAMC_REG_SHU_RX_CG_SET0 */
DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0)
DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND3, 1)
DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 2)
DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND2, 3)
DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 4)
DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND1, 5)

/* DDRPHY_REG_MISC_SHU_RK_DQSCAL */
DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENLLMT, 6, 0)
DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 7)
DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENHLMT, 14, 8)
DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 15)

/* DDRPHY_REG_SHU_R0_B0_INI_UIPI */
DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 6, 0)
DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 15, 8)

/* DDRPHY_REG_SHU_R0_B1_INI_UIPI */
DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 6, 0)
DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 15, 8)

/* DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI */
DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 6, 0)
DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 15, 8)
DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI */
DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 6, 0)
DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 15, 8)
DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 31, 24)

/* DDRPHY_REG_SHU_R0_B0_DQ0 */
DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 2, 0)
DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 6, 4)
DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 13, 8)
DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 21, 16)
DEFINE_BITFIELD(SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 29, 24)
DEFINE_BIT(SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 30)
DEFINE_BIT(SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 31)

/* DDRPHY_REG_SHU_R0_B1_DQ0 */
DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 2, 0)
DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 6, 4)
DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 13, 8)
DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 21, 16)
DEFINE_BITFIELD(SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 29, 24)
DEFINE_BIT(SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 30)
DEFINE_BIT(SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 31)

/* DRAMC_REG_SHU_APHY_TX_PICG_CTRL */
DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 3, 0)
DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 6, 4)
DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 10, 8)
DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 15, 12)
DEFINE_BIT(SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 31)

/* DRAMC_REG_SHURK_APHY_TX_PICG_CTRL */
DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 2, 0)
DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 6, 4)

/* DRAMC_REG_SHU_NEW_XRW2W_CTRL */
DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 18, 16)
DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 26, 24)
DEFINE_BIT(SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 31)

/* DRAMC_REG_SHU_SELPH_DQS0 */
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS0, 2, 0)
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS1, 6, 4)
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS2, 10, 8)
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS3, 14, 12)
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 18, 16)
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 22, 20)
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 26, 24)
DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 30, 28)

/* DRAMC_REG_SHURK_SELPH_DQ0 */
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ0, 2, 0)
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ1, 6, 4)
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ2, 10, 8)
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ3, 14, 12)
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 18, 16)
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 22, 20)
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 26, 24)
DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 30, 28)

/* DRAMC_REG_SHURK_SELPH_DQ1 */
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM0, 2, 0)
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM1, 6, 4)
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM2, 10, 8)
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM3, 14, 12)
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 18, 16)
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 22, 20)
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 26, 24)
DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 30, 28)

/* DRAMC_REG_SHURK_SELPH_DQ2 */
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ0, 3, 0)
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ1, 7, 4)
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ2, 11, 8)
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ3, 15, 12)
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ0, 19, 16)
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ1, 23, 20)
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ2, 27, 24)
DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ3, 31, 28)

/* DRAMC_REG_SHURK_SELPH_DQ3 */
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM0, 3, 0)
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM1, 7, 4)
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM2, 11, 8)
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM3, 15, 12)
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM0, 19, 16)
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM1, 23, 20)
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM2, 27, 24)
DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM3, 31, 28)

/* DRAMC_REG_SHURK_DQS2DQ_CAL1 */
DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 10, 0)
DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 26, 16)

/* DRAMC_REG_SHURK_DQS2DQ_CAL2 */
DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 10, 0)
DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 26, 16)

/* DRAMC_REG_SHURK_DQS2DQ_CAL5 */
DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 10, 0)
DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 26, 16)

/* DRAMC_REG_SHURK_PI */
DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B1, 5, 0)
DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B0, 13, 8)
DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B1, 21, 16)
DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B0, 29, 24)

/* DDRPHY_REG_SHU_R0_B0_TXDLY0 */
DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 15, 8)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 23, 16)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B0_TXDLY1 */
DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 15, 8)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 23, 16)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B0_TXDLY3 */
DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 23, 16)
DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_TXDLY0 */
DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 15, 8)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 23, 16)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_TXDLY1 */
DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 15, 8)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 23, 16)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_TXDLY3 */
DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 23, 16)
DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 31, 24)

/* DRAMC_REG_SHU_SREF_CTRL */
DEFINE_BITFIELD(SHU_SREF_CTRL_CKEHCMD, 5, 4)
DEFINE_BITFIELD(SHU_SREF_CTRL_SREF_CK_DLY, 29, 28)

/* DRAMC_REG_SHU_HMR4_DVFS_CTRL0 */
DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 15, 8)
DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_REFRCNT, 27, 16)

/* DDRPHY_REG_SHU_B0_DQ5 */
DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0)
DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 6)
DEFINE_BITFIELD(SHU_B0_DQ5_RG_ARPI_FB_B0, 13, 8)
DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 18, 16)
DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 19)
DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 23, 20)
DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 31, 29)

/* DDRPHY_REG_SHU_B1_DQ5 */
DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 5, 0)
DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 6)
DEFINE_BITFIELD(SHU_B1_DQ5_RG_ARPI_FB_B1, 13, 8)
DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 18, 16)
DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 19)
DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 23, 20)
DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 31, 29)

/* DDRPHY_REG_SHU_R0_B0_RXDLY0 */
DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 15, 8)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 23, 16)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B0_RXDLY1 */
DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 15, 8)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 23, 16)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B0_RXDLY2 */
DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 15, 8)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 23, 16)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B0_RXDLY3 */
DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 15, 8)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 23, 16)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 31, 24)

/* DDRPHY_REG_SHU_R0_B0_RXDLY4 */
DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 7, 0)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 15, 8)

/* DDRPHY_REG_SHU_R0_B0_RXDLY5 */
DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 8, 0)
DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 24, 16)

/* DDRPHY_REG_SHU_R0_B1_RXDLY0 */
DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 15, 8)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 23, 16)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_RXDLY1 */
DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 15, 8)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 23, 16)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_RXDLY2 */
DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 15, 8)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 23, 16)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_RXDLY3 */
DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 15, 8)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 23, 16)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 31, 24)

/* DDRPHY_REG_SHU_R0_B1_RXDLY4 */
DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 7, 0)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 15, 8)

/* DDRPHY_REG_SHU_R0_B1_RXDLY5 */
DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 8, 0)
DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 24, 16)

/* DDRPHY_REG_B0_DQ4 */
DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 6, 0)
DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 14, 8)
DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 21, 16)
DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 29, 24)

/* DDRPHY_REG_B1_DQ4 */
DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 6, 0)
DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 14, 8)
DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 21, 16)
DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 29, 24)

/* DDRPHY_REG_SHU_R0_CA_CMD0 */
DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 2, 0)
DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 6, 4)
DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CS, 13, 8)
DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CMD, 21, 16)
DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CLK, 29, 24)
DEFINE_BIT(SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 30)
DEFINE_BIT(SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 31)

/* DRAMC_REG_SHU_SELPH_DQS1 */
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS0, 3, 0)
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS1, 7, 4)
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS2, 11, 8)
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS3, 15, 12)
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS0, 19, 16)
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS1, 23, 20)
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS2, 27, 24)
DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS3, 31, 28)

/* DDRPHY_REG_MISC_RX_AUTOK_CFG0 */
DEFINE_BIT(MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 3)

/* DDRPHY_REG_SHU_CA_CMD8 */
DEFINE_BIT(SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 20)
DEFINE_BIT(SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 21)
DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 26)
DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 27)
DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 28)
DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 29)
DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 30)
DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 31)

/* DRAMC_REG_MRR_BIT_MUX1 */
DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0)
DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8)
DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16)
DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24)

/* DRAMC_REG_MRR_BIT_MUX2 */
DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0)
DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8)
DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT6_SEL, 20, 16)
DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT7_SEL, 28, 24)

/* DRAMC_REG_MRR_BIT_MUX3 */
DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT8_SEL, 4, 0)
DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT9_SEL, 12, 8)
DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT10_SEL, 20, 16)
DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT11_SEL, 28, 24)

/* DRAMC_REG_MRR_BIT_MUX4 */
DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT12_SEL, 4, 0)
DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT13_SEL, 12, 8)
DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT14_SEL, 20, 16)
DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT15_SEL, 28, 24)

/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0 */
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, 3, 0)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, 7, 4)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, 11, 8)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, 15, 12)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, 19, 16)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, 23, 20)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, 27, 24)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, 31, 28)

/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1 */
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, 3, 0)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, 7, 4)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, 11, 8)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, 15, 12)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, 19, 16)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, 23, 20)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, 27, 24)
DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, 31, 28)

/* DRAMC_REG_SA_RESERVE */
DEFINE_BIT(SA_RESERVE_SINGLE_RANK, 0)
DEFINE_BITFIELD(SA_RESERVE_MODE_RK1, 27, 24)
DEFINE_BITFIELD(SA_RESERVE_MODE_RK0, 31, 28)

/* DRAMC_REG_SWCMD_CTRL0 */
DEFINE_BITFIELD(SWCMD_CTRL0_MRSOP, 7, 0)
DEFINE_BITFIELD(SWCMD_CTRL0_MRSMA, 20, 8)
DEFINE_BITFIELD(SWCMD_CTRL0_MRSRK, 25, 24)
DEFINE_BIT(SWCMD_CTRL0_SWTRIG_ZQ_RK, 30)

/* DRAMC_REG_DRAMC_IRQ_EN */
DEFINE_BIT(DRAMC_IRQ_EN_MR4INT_EN, 0)
DEFINE_BITFIELD(DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 31, 18)

/* DDRPHY_REG_CA_TX_MCK */
DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 25, 21)
DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 30, 26)
DEFINE_BIT(CA_TX_MCK_R_DMRESET_FRPHY_OPT, 31)

/* DDRPHY_REG_MISC_IMPCAL */
DEFINE_BIT(MISC_IMPCAL_DRVCGWREF, 2)
DEFINE_BIT(MISC_IMPCAL_DQDRVSWUPD, 3)
DEFINE_BIT(MISC_IMPCAL_IMPSRCEXT, 4)
DEFINE_BIT(MISC_IMPCAL_IMPBINARY, 5)
DEFINE_BIT(MISC_IMPCAL_DRV_ECO_OPT, 10)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT, 11)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_SM_ECO_OPT, 12)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_ECO_OPT, 13)
DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH1_DRV, 14)
DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH0_DRV, 15)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_DRVUPDOPT, 17)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 19)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_HWSAVE_EN, 20)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENN, 21)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENP, 22)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_EN, 23)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDN, 24)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDP, 25)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_NEW_OLD_SL, 26)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_SWVALUE_EN, 29)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_EN, 30)
DEFINE_BIT(MISC_IMPCAL_IMPCAL_HW, 31)

/* DDRPHY_REG_SHU_B0_DLL2 */
DEFINE_BITFIELD(SHU_B0_DLL2_RG_ARDQ_REV_B0, 31, 0)

/* DDRPHY_REG_SHU_B1_DLL2 */
DEFINE_BITFIELD(SHU_B1_DLL2_RG_ARDQ_REV_B1, 31, 0)

/* DDRPHY_REG_SHU_CA_DLL2 */
DEFINE_BITFIELD(SHU_CA_DLL2_RG_ARCMD_REV, 31, 0)

/* DRAMC_REG_DRAMC_DBG_SEL1 */
DEFINE_BITFIELD(DRAMC_DBG_SEL1_DEBUG_SEL_0, 15, 0)

/* DRAMC_REG_SWCMD_CTRL2 */
DEFINE_BITFIELD(SWCMD_CTRL2_RTSWCMD_AGE, 9, 0)

/* DRAMC_REG_RTMRW_CTRL0 */
DEFINE_BITFIELD(RTMRW_CTRL0_RTMRW_AGE, 24, 15)

/* DRAMC_REG_REF_BOUNCE1 */
DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT, 7, 0)
DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 12, 8)
DEFINE_BIT(REF_BOUNCE1_REFRATE_DEBOUNCE_OPT, 13)
DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_DIS, 31, 16)

/* DRAMC_REG_REFPEND2 */
DEFINE_BITFIELD(REFPEND2_MPENDREFCNT_TH8, 3, 0)

/* DRAMC_REG_RTSWCMD_CNT */
DEFINE_BITFIELD(RTSWCMD_CNT_RTSWCMD_CNT, 31, 0)

/* DDRPHY_REG_B0_DLL_ARPI4 */
DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 8)
DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 9)

/* DDRPHY_REG_B1_DLL_ARPI4 */
DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 8)
DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 9)

/* DDRPHY_REG_CA_DLL_ARPI4 */
DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 8)
DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 9)

/* DDRPHY_REG_MISC_DDR_RESERVE */
DEFINE_BITFIELD(MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 7, 0)
DEFINE_BIT(MISC_DDR_RESERVE_WDT_SM_CLR, 24)
DEFINE_BIT(MISC_DDR_RESERVE_WDT_LITE_EN, 25)

/* DDRPHY_REG_MISC_CTRL6 */
DEFINE_BIT(MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 0)
DEFINE_BIT(MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1)

/* DRAMC_REG_REF_BOUNCE2 */
DEFINE_BITFIELD(REF_BOUNCE2_PRE_MR4INT_TH, 4, 0)

/* DRAMC_REG_SHU_REF0 */
DEFINE_BITFIELD(SHU_REF0_MPENDREF_CNT, 2, 0)

/* DRAMC_REG_ZQ_SET1 */
DEFINE_BIT(ZQ_SET1_ZQCALDISB, 30)

/* DRAMC_REG_TX_RETRY_SET0 */
DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK, 0)
DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_EN, 2)
DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_SW_EN, 4)

/* DRAMC_REG_SPCMDRESP */
DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1)
DEFINE_BIT(SPCMDRESP_RDDQC_RESPONSE, 7)
DEFINE_BIT(SPCMDRESP_TX_RETRY_DONE_RESPONSE, 15)

/* DDRPHY_REG_SHU_B0_VREF */
DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 16)
DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, 22)

/* DDRPHY_REG_SHU_B1_VREF */
DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 16)
DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, 22)

/* DDRPHY_REG_SHU_B0_PHY_VREF_SEL */
DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B0, 6, 0)
DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B0, 14, 8)

/* DDRPHY_REG_SHU_B1_PHY_VREF_SEL */
DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B1, 6, 0)
DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B1, 14, 8)

/* DDRPHY_REG_SHU_MISC_DRVING1 */
DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVN2, 4, 0)
DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVP2, 9, 5)
DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN1, 14, 10)
DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP1, 19, 15)
DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN2, 24, 20)
DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP2, 29, 25)
DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, 30)
DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMPCAL_HW, 31)

/* DRAMC_REG_SHU_ZQ_SET0 */
DEFINE_BITFIELD(SHU_ZQ_SET0_ZQCSCNT, 15, 0)
DEFINE_BITFIELD(SHU_ZQ_SET0_TZQLAT, 31, 27)

/* DRAMC_REG_DCM_SUB_CTRL */
DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1)
DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 12)

/* DDRPHY_REG_B0_PHY3 */
DEFINE_BIT(B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0, 28)

/* DDRPHY_REG_B1_PHY3 */
DEFINE_BIT(B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1, 28)

/* DRAMC_REG_CBT_WLEV_CTRL5 */
DEFINE_BITFIELD(CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV, 11, 4)

/* DRAMC_REG_CBT_WLEV_CTRL0 */
DEFINE_BIT(CBT_WLEV_CTRL0_BYTEMODECBTEN, 2)
DEFINE_BIT(CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 3)
DEFINE_BIT(CBT_WLEV_CTRL0_DQSOEAOEN, 4)
DEFINE_BIT(CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 7)
DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL, 11, 8)
DEFINE_BITFIELD(CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT, 19, 12)
DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN, 29, 26)
DEFINE_BIT(CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 30)

/* DRAMC_REG_SHU_LP5_CMD */
DEFINE_BIT(SHU_LP5_CMD_LP5_CMD1TO2EN, 0)

/* DDRPHY_REG_SHU_R0_CA_TXDLY0 */
DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 7, 0)
DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 15, 8)
DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 23, 16)
DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 31, 24)

/* DDRPHY_REG_SHU_R0_CA_TXDLY1 */
DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 7, 0)
DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 15, 8)
DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 23, 16)
DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 31, 24)

/* DRAMC_REG_CBT_WLEV_CTRL4 */
DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B0, 7, 0)
DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B1, 15, 8)

/* DRAMC_REG_CBT_WLEV_CTRL3 */
DEFINE_BITFIELD(CBT_WLEV_CTRL3_DQSBX_G, 17, 14)

/* DRAMC_REG_SWCMD_EN */
DEFINE_BIT(SWCMD_EN_RDDQCEN, 5)
DEFINE_BIT(SWCMD_EN_MRWEN, 11)
DEFINE_BIT(SWCMD_EN_MRREN, 12)
DEFINE_BIT(SWCMD_EN_ZQCEN_SWTRIG, 16)
DEFINE_BIT(SWCMD_EN_ZQLATEN_SWTRIG, 17)
DEFINE_BIT(SWCMD_EN_WCK2DQI_START_SWTRIG, 18)

/* DRAMC_REG_SPCMDRESP3 */
DEFINE_BIT(SPCMDRESP3_ZQC_SWTRIG_RESPONSE, 1)
DEFINE_BIT(SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE, 2)
DEFINE_BIT(SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE, 3)

/* DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY */
DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0, 18, 16)
DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0, 22, 20)

/* DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY */
DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1, 18, 16)
DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1, 22, 20)

/* DRAMC_REG_RDDQCGOLDEN */
DEFINE_BITFIELD(RDDQCGOLDEN_MR20_GOLDEN, 7, 0)
DEFINE_BITFIELD(RDDQCGOLDEN_MR15_GOLDEN, 15, 8)
DEFINE_BITFIELD(RDDQCGOLDEN_MR40_GOLDEN, 23, 16)
DEFINE_BITFIELD(RDDQCGOLDEN_MR32_GOLDEN, 31, 24)

/* DDRPHY_REG_MISC_JMETER */
DEFINE_BIT(MISC_JMETER_JMTR_EN, 0)

/* DDRPHY_REG_MISC_DUTY_TOGGLE_CNT */
DEFINE_BITFIELD(MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT, 31, 0)

/* DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT */
DEFINE_BITFIELD(MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT, 31, 0)

/* DDRPHY_REG_DVFS_STATUS */
DEFINE_BITFIELD(DVFS_STATUS_OTHER_SHU_GP, 17, 16)

/* DDRPHY_REG_SHU_MISC_DRVING3 */
DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTN2, 4, 0)
DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTP2, 9, 5)
DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN, 14, 10)
DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP, 19, 15)
DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN2, 24, 20)
DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP2, 29, 25)

/* DDRPHY_REG_SHU_MISC_DRVING4 */
DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN1, 4, 0)
DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP1, 9, 5)
DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN2, 14, 10)
DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP2, 19, 15)
DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTN1, 24, 20)
DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTP1, 29, 25)

/* DDRPHY_REG_MISC_SHU_DRVING8 */
DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVN, 4, 0)
DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVP, 12, 8)

/* DDRPHY_REG_MISC_PHY_RGS_CMD */
DEFINE_BIT(MISC_PHY_RGS_CMD_RGS_RIMPCALOUT, 24)

/* DDRPHY_REG_SHU_CA_TXDUTY */
DEFINE_BITFIELD(SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, 13, 8)

/* DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY */
DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, 5, 0)
DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, 13, 8)
DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, 21, 16)
DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, 29, 24)

/* DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3 */
DEFINE_BITFIELD(TEST2_A3_TESTCNT, 3, 0)

/* DRAMC_REG_SHU_DQSOSC_SET0 */
DEFINE_BIT(SHU_DQSOSC_SET0_DQSOSCENDIS, 0)
DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSC_PRDCNT, 13, 4)
DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSCENCNT, 31, 16)

/* DRAMC_REG_SHURK_DQSOSC */
DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0, 15, 0)
DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16)

/* DRAMC_REG_SHU_DQSOSCR */
DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0)

/* DRAMC_REG_SHURK_DQSOSC_THRD */
DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_INC, 11, 0)
DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC, 27, 16)

/* DRAMC_REG_SHU_FREQ_RATIO_SET0 */
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, 7, 0)
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, 15, 8)
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, 23, 16)
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, 31, 24)

/* DRAMC_REG_SHU_FREQ_RATIO_SET1 */
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7, 7, 0)
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, 15, 8)
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, 23, 16)
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, 31, 24)

/* DRAMC_REG_SHU_FREQ_RATIO_SET2 */
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9, 23, 16)
DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8, 31, 24)

/* DDRPHY_REG_SHU_MISC_PRE_TDQSCK */
DEFINE_BIT(SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0)

/* DDRPHY_REG_MISC_PRE_TDQSCK1 */
DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22)
DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS, 25)
DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26)

/* DRAMC_REG_MISC_STATUSA */
DEFINE_BIT(MISC_STATUSA_REQQ_EMPTY, 2)
DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24)

/* DRAMC_REG_TEST2_A0 */
DEFINE_BITFIELD(TEST2_A0_TEST2_PAT1, 7, 0)
DEFINE_BITFIELD(TEST2_A0_TEST2_PAT0, 15, 8)
DEFINE_BIT(TEST2_A0_LOOP_NV_END, 16)
DEFINE_BIT(TEST2_A0_ERR_BREAK_EN, 17)
DEFINE_BIT(TEST2_A0_TA2_LOOP_EN, 18)
DEFINE_BITFIELD(TEST2_A0_LOOP_CNT_INDEX, 23, 20)

/* DRAMC_REG_TESTRPT */
DEFINE_BITFIELD(TESTRPT_TESTSTAT, 22, 20)

/* DRAMC_REG_MRR_STATUS */
DEFINE_BITFIELD(MRR_STATUS_MRR_SW_REG, 31, 16)

/* DRAMC_REG_SPCMDRESP */
DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0)

/* DRAMC_REG_MISC_STATUSA */
DEFINE_BITFIELD(MISC_STATUSA_REFRESH_RATE, 12, 8)

/* DDRPHY_REG_SHU_CA_CMD0 */
DEFINE_BIT(SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 31)

/* DDRPHY_REG_SHU_B0_DQ0 */
DEFINE_BIT(SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 31)

/* DDRPHY_REG_SHU_B1_DQ0 */
DEFINE_BIT(SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 31)

#endif /* __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ */
