/*
 * This file is part of the coreboot project.
 *
 * Copyright 2017-present Facebook, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

// This file is automatically generated.
// DO NOT EDIT BY HAND.

#include <bdk-devicetree.h>

const struct bdk_devicetree_key_value devtree[] = {
{"DDR-TEST-BOOT", "1"},
{"DDR-CONFIG-DQX-CTL", "0x4"},
{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},
{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS4", "0x1"},
{"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1", "0x1"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2", "0x2"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2", "0x4"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0", "0x1"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0", "0x5"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2", "0x5"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0", "0x2"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1", "0x2"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2", "0x1"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0", "0x6"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1", "0x6"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0", "0x22"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1", "0x1f"},
{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1", "0x7"},
{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2", "0x3"},
{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1", "0x3"},
{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2", "0x7"},
{"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1", "0x7"},
{"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2", "0x4080102"},
{"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1", "0x1010202"},
{"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX", "0x1"},
{"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX", "0x7"},
{"DDR-CONFIG-CUSTOM-MIN-RODT-CTL", "0x1"},
{"DDR-CONFIG-CUSTOM-MAX-RODT-CTL", "0x7"},
{"DDR-CONFIG-CUSTOM-CK-CTL", "0x4"},
{"DDR-CONFIG-CUSTOM-CMD-CTL", "0x4"},
{"DDR-CONFIG-CUSTOM-CTL-CTL", "0x4"},
{"DDR-CONFIG-CUSTOM-OFFSET-EN", "0x1"},
{"DDR-CONFIG-CUSTOM-OFFSET", "0x2"},
{"DDR-CONFIG-CUSTOM-DDR2T", "0x1"},
{"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT", "0x2"},
{"DDR-CONFIG-CUSTOM-FPRCH2", "0x2"},
{"PHY-ADDRESS.N0.BGX0.P0", "0xff000010"},
{"PHY-ADDRESS.N0.BGX0.P1", "0xff000011"},
{"PHY-ADDRESS.N0.BGX0.P2", "0xff000012"},
{"PHY-ADDRESS.N0.BGX0.P3", "0xff000013"},
{"PHY-ADDRESS.N0.BGX1.P0", "0xff002014"},
{"PHY-ADDRESS.N0.BGX1.P1", "0xff002014"},
{"PHY-ADDRESS.N0.BGX2.P0", "0xff000000"},
{"BGX-ENABLE.N0.BGX0.P0", "1"},
{"BGX-ENABLE.N0.BGX0.P1", "1"},
{"BGX-ENABLE.N0.BGX0.P2", "1"},
{"BGX-ENABLE.N0.BGX0.P3", "1"},
{"BGX-ENABLE.N0.BGX1.P0", "1"},
{"BGX-ENABLE.N0.BGX1.P1", "1"},
{"BGX-ENABLE.N0.BGX2.P0", "1"},
{"BDK-NUM-PACKET-BUFFERS", "0x1000"},
{"BDK-PACKET-BUFFER-SIZE", "0x400"},
{"BDK-SHOW-LINK-STATUS", "1"},
{"BDK-COREMASK", "0"},
{"MULTI-NODE", "0"},
{"QLM-AUTO-CONFIG", "0"},
{"QLM-DIP-AUTO-CONFIG", "1"},
{"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"},
{"USB-PWR-GPIO.N0.PORT0", "12"},
{"USB-PWR-GPIO-POLARITY.N0.PORT0", "0"},
{"USB-REFCLK-SRC.N0.PORT0", "0"},
{"GPIO-PIN-SELECT-GPIO15", "0x24f"},
{"GPIO-PIN-SELECT-GPIO16", "0x24e"},
{"GPIO-PIN-SELECT-GPIO17", "0x24b"},
{"GPIO-PIN-SELECT-GPIO18", "0x247"},
{"GPIO-PIN-SELECT-GPIO19", "0x24d"},
{"GPIO-PIN-SELECT-GPIO20", "0x24c"},
{"GPIO-PIN-SELECT-GPIO37", "0x24a"},
{"GPIO-PIN-SELECT-GPIO38", "0x246"},
{"GPIO-PIN-SELECT-GPIO7", "0xe1"},
{"GPIO-PIN-SELECT-GPIO24", "0xeb"},
{"GPIO-PIN-SELECT-GPIO27", "0xed"},
{"GPIO-PIN-SELECT-GPIO28", "0xe3"},
{"GPIO-PIN-SELECT-GPIO29", "0xe0"},
{"GPIO-PIN-SELECT-GPIO30", "0xe2"},
{"GPIO-PIN-SELECT-GPIO40", "0x112"},
{"GPIO-PIN-SELECT-GPIO41", "0x113"},
{"GPIO-PIN-SELECT-GPIO42", "0x114"},
{"GPIO-PIN-SELECT-GPIO43", "0x115"},
{"GPIO-PIN-SELECT-GPIO44", "0x116"},
{"GPIO-PIN-SELECT-GPIO45", "0x117"},
{"GPIO-PIN-SELECT-GPIO46", "0x118"},
{"GPIO-PIN-SELECT-GPIO47", "0x119"},
{"GPIO-POLARITY-GPIO7", "1"},
{"GPIO-POLARITY-GPIO27", "1"},
{"GPIO-POLARITY-GPIO28", "1"},
{"GPIO-POLARITY-GPIO30", "1"},
{0, 0},
};
