##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if CONFIG_USE_FAILOVER_IMAGE
	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FAILOVER_SIZE
	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FAILOVER_SIZE )
	default CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
else
    if CONFIG_USE_FALLBACK_IMAGE
	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
    else
	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
    end
end

##
## Compute where this copy of coreboot will start in the boot rom
##
default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
##

if CONFIG_USE_FAILOVER_IMAGE
	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
else
    if CONFIG_USE_FALLBACK_IMAGE
	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE + CONFIG_FAILOVER_SIZE)
    else
	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
    end
end

