44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/* -*- mode:c -*-
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*
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* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Minimal set of GPIOs needed for LFW loader
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*/
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/*
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* MEC1701H GPIO_0055/PWM2/SHD_CS0#/RSMRST#
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* MEC1701H QMSPI controller drives chip select, must be
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* configured to alternative function. See below.
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* GPIO_SHD_CS0 is used in board level spi_devices[] table
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*/
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GPIO(QMSPI_CS0, PIN(055), GPIO_ODR_HIGH)
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/* Alternate functions GPIO definition */
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/*
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* UART
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* GPIO_0104(UART0_TX) Func1
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* GPIO_0105(UART0_RX) Func1
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* Bank 2 bits[4:5]
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*/
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ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
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/* SPI pins */
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/*
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* MEC1701H SHD SPI is connected to QMSPI controller.
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* QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
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* to alternate function 2 and GPIO_ODR_HIGH.
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* GPIO_0055 Function 2, Bank 1 bit[13]
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*/
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ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
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/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
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ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
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/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
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/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
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ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)
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