129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USB Power delivery board configuration */
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#ifndef __CROS_EC_USB_PD_CONFIG_H
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#define __CROS_EC_USB_PD_CONFIG_H
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/* Timer selection for baseband PD communication */
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#define TIM_CLOCK_PD_TX_C0 17
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#define TIM_CLOCK_PD_RX_C0 1
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#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
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#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
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/* Timer channel */
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#define TIM_RX_CCR_C0 1
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#define TIM_TX_CCR_C0 1
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/* RX timer capture/compare register */
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#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
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#define TIM_RX_CCR_REG(p) TIM_CCR_C0
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/* TX and RX timer register */
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#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
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#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
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#define TIM_REG_TX(p) TIM_REG_TX_C0
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#define TIM_REG_RX(p) TIM_REG_RX_C0
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/* use the hardware accelerator for CRC */
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#define CONFIG_HW_CRC
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/* TX is using SPI1 on PB3-4 */
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#define SPI_REGS(p) STM32_SPI1_REGS
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static inline void spi_enable_clock(int port)
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{
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STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
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}
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/* SPI1_TX no remap needed */
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#define DMAC_SPI_TX(p) STM32_DMAC_CH3
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/* RX is using COMP1 triggering TIM1 CH1 */
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#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
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#define CMP2OUTSEL 0
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#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
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#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
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#define TIM_CCR_CS 1
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#define EXTI_COMP_MASK(p) BIT(21)
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#define IRQ_COMP STM32_IRQ_COMP
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/* triggers packet detection on comparator falling edge */
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#define EXTI_XTSR STM32_EXTI_FTSR
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/* TIM1_CH1 no remap needed */
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#define DMAC_TIM_RX(p) STM32_DMAC_CH2
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/* the pins used for communication need to be hi-speed */
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static inline void pd_set_pins_speed(int port)
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{
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/* 40 Mhz pin speed on TX_EN (PA15) */
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STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000;
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/* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0;
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}
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/* Reset SPI peripheral used for TX */
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static inline void pd_tx_spi_reset(int port)
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{
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/* Reset SPI1 */
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STM32_RCC_APB2RSTR |= BIT(12);
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STM32_RCC_APB2RSTR &= ~BIT(12);
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}
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/* Drive the CC line from the TX block */
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static inline void pd_tx_enable(int port, int polarity)
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{
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/* PB4 is SPI1_MISO */
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gpio_set_alternate_function(GPIO_B, 0x0010, 0);
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gpio_set_level(GPIO_PD_CC1_TX_EN, 1);
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}
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/* Put the TX driver in Hi-Z state */
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static inline void pd_tx_disable(int port, int polarity)
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{
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/* output low on SPI TX (PB4) to disable the FET */
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STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
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& ~(3 << (2*4)))
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| (1 << (2*4));
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/* put the low level reference in Hi-Z */
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gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
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}
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static inline void pd_select_polarity(int port, int polarity)
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{
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/*
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* use the right comparator : CC1 -> PA1 (COMP1 INP)
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* use VrefInt / 2 as INM (about 600mV)
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*/
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STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
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| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
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}
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/* Initialize pins used for TX and put them in Hi-Z */
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static inline void pd_tx_init(void)
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{
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gpio_config_module(MODULE_USB_PD, 1);
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}
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static inline void pd_set_host_mode(int port, int enable) {}
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static inline void pd_config_init(int port, uint8_t power_role)
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{
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/* Initialize TX pins and put them in Hi-Z */
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pd_tx_init();
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}
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static inline int pd_adc_read(int port, int cc)
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{
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/* only one CC line, assume other one is always low */
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return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0;
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}
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#endif /* __CROS_EC_USB_PD_CONFIG_H */
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