481 lines
13 KiB
C
481 lines
13 KiB
C
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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#define CONFIG_LTO
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/*
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* The default watchdog timeout is 1.6 seconds, but there are some legitimate
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* flash-intensive TPM operations that actually take close to that long to
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* complete. Make sure we don't trigger the watchdog accidentally if the timing
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* is just a little off.
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*/
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#undef CONFIG_WATCHDOG_PERIOD_MS
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#define CONFIG_WATCHDOG_PERIOD_MS 5000
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/* Features that we don't want */
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#undef CONFIG_CMD_LID_ANGLE
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#undef CONFIG_CMD_POWERINDEBUG
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#undef CONFIG_DMA_DEFAULT_HANDLERS
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#undef CONFIG_FMAP
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#undef CONFIG_HIBERNATE
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#undef CONFIG_LID_SWITCH
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#undef CONFIG_CMD_SYSINFO
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#undef CONFIG_CMD_SYSJUMP
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#undef CONFIG_CMD_SYSLOCK
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#ifndef CR50_DEV
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/* Disable stuff that should only be in debug builds */
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#undef CONFIG_CMD_CRASH
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#undef CONFIG_CMD_MD
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#undef CONFIG_CMD_RW
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#undef CONFIG_CMD_SLEEPMASK_SET
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#undef CONFIG_CMD_WAITMS
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#undef CONFIG_FLASH
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#endif
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/* Enable getting gpio flags to tell if open drain pins are asserted */
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#define CONFIG_GPIO_GET_EXTENDED
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/* Flash configuration */
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#undef CONFIG_FLASH_PSTATE
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#define CONFIG_WP_ALWAYS
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#define CONFIG_FLASH_READOUT_PROTECTION
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#define CONFIG_CMD_FLASH
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#define CONFIG_CRC8
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/* Non-volatile counter storage for U2F */
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#define CONFIG_FLASH_NVCOUNTER
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#define CONFIG_FLASH_NVCTR_SIZE CONFIG_FLASH_BANK_SIZE
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#define CONFIG_FLASH_NVCTR_BASE_A (CONFIG_PROGRAM_MEMORY_BASE + \
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CFG_TOP_A_OFF)
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#define CONFIG_FLASH_NVCTR_BASE_B (CONFIG_PROGRAM_MEMORY_BASE + \
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CFG_TOP_B_OFF)
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/* We're using TOP_A for partition 0, TOP_B for partition 1 */
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#define CONFIG_FLASH_NVMEM
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/* Offset to start of NvMem area from base of flash */
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#define CONFIG_FLASH_NVMEM_OFFSET_A (CFG_TOP_A_OFF + CONFIG_FLASH_NVCTR_SIZE)
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#define CONFIG_FLASH_NVMEM_OFFSET_B (CFG_TOP_B_OFF + CONFIG_FLASH_NVCTR_SIZE)
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/* Address of start of Nvmem area */
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#define CONFIG_FLASH_NVMEM_BASE_A \
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(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_NVMEM_OFFSET_A)
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#define CONFIG_FLASH_NVMEM_BASE_B \
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(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_NVMEM_OFFSET_B)
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#define CONFIG_FLASH_NEW_NVMEM_BASE_A \
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(CONFIG_FLASH_NVMEM_BASE_A + CONFIG_FLASH_BANK_SIZE)
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#define CONFIG_FLASH_NEW_NVMEM_BASE_B \
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(CONFIG_FLASH_NVMEM_BASE_B + CONFIG_FLASH_BANK_SIZE)
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/* Size partition in NvMem */
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#define NVMEM_PARTITION_SIZE (CFG_TOP_SIZE - CONFIG_FLASH_NVCTR_SIZE)
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#define NEW_NVMEM_PARTITION_SIZE (NVMEM_PARTITION_SIZE - CONFIG_FLASH_BANK_SIZE)
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#define NEW_NVMEM_TOTAL_PAGES \
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(2 * NEW_NVMEM_PARTITION_SIZE / CONFIG_FLASH_BANK_SIZE)
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/* Size in bytes of NvMem area */
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#define CONFIG_FLASH_LOG
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#define CONFIG_FLASH_NVMEM_SIZE (NVMEM_PARTITION_SIZE * NVMEM_NUM_PARTITIONS)
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/* Enable <key, value> variable support. */
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#define CONFIG_FLASH_NVMEM_VARS
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#define NVMEM_CR50_SIZE 272
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#define CONFIG_FLASH_NVMEM_VARS_USER_SIZE NVMEM_CR50_SIZE
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/* Go to sleep when nothing else is happening */
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#define CONFIG_LOW_POWER_IDLE
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/* Allow multiple concurrent memory allocations. */
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#define CONFIG_MALLOC
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/* Enable debug cable detection */
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#define CONFIG_RDD
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/* Also use the cr50 as a second factor authentication */
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#define CONFIG_U2F
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/* USB configuration */
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#define CONFIG_USB
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#define CONFIG_USB_CONSOLE
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#define CONFIG_USB_I2C
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#define CONFIG_USB_INHIBIT_INIT
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#define CONFIG_USB_SPI
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#define CONFIG_USB_SERIALNO
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#define DEFAULT_SERIALNO "0"
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#define CONFIG_STREAM_USART
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#define CONFIG_STREAM_USB
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#define CONFIG_STREAM_USART1
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#define CONFIG_STREAM_USART2
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/* Enable Case Closed Debugging */
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#define CONFIG_CASE_CLOSED_DEBUG_V1
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#define CONFIG_PHYSICAL_PRESENCE
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/* Loosen CCD open requirements. Only allowed in prePVT images */
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#define CONFIG_CCD_OPEN_PREPVT
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#ifdef CR50_DEV
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/* Enable unsafe dev features for CCD in dev builds */
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#define CONFIG_CASE_CLOSED_DEBUG_V1_UNSAFE
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#define CONFIG_CMD_FLASH_LOG
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#define CONFIG_PHYSICAL_PRESENCE_DEBUG_UNSAFE
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#endif
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#if defined(CR50_DEV) || defined(CR50_SQA)
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#define CR50_RELAXED
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#endif
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#define CONFIG_USB_PID 0x5014
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#define CONFIG_USB_SELF_POWERED
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#undef CONFIG_USB_MAXPOWER_MA
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#define CONFIG_USB_MAXPOWER_MA 0
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/* Need to be able to bitbang the EC UART for updates through CCD. */
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#define CONFIG_UART_BITBANG
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/* Enable SPI Master (SPI) module */
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#define CONFIG_SPI_MASTER
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#define CONFIG_SPI_MASTER_NO_CS_GPIOS
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#define CONFIG_SPI_MASTER_CONFIGURE_GPIOS
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#define CONFIG_SPI_FLASH_PORT 0
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/* Enable SPI Slave (SPS) module */
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#define CONFIG_SPS
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#define CONFIG_TPM_SPS
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#define CONFIG_RBOX
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#define CONFIG_RBOX_WAKEUP
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/* We don't need to send events to the AP */
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#undef CONFIG_HOSTCMD_EVENTS
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/* Make most commands restricted */
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#define CONFIG_CONSOLE_COMMAND_FLAGS
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#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
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#define CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT CMD_FLAG_RESTRICTED
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/* Include crypto stuff, both software and hardware. Enable optimizations. */
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#define CONFIG_DCRYPTO
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#define CONFIG_UPTO_SHA512
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#define CONFIG_DCRYPTO_RSA_SPEEDUP
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/* Implement custom udelay, due to usec hwtimer imprecision. */
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#define CONFIG_HW_SPECIFIC_UDELAY
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#ifndef __ASSEMBLER__
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#include "gpio_signal.h"
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/* USB string indexes */
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enum usb_strings {
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USB_STR_DESC = 0,
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USB_STR_VENDOR,
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USB_STR_PRODUCT,
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USB_STR_VERSION,
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USB_STR_CONSOLE_NAME,
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USB_STR_BLOB_NAME,
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USB_STR_HID_KEYBOARD_NAME,
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USB_STR_AP_NAME,
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USB_STR_EC_NAME,
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USB_STR_UPGRADE_NAME,
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USB_STR_SPI_NAME,
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USB_STR_SERIALNO,
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USB_STR_I2C_NAME,
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USB_STR_COUNT
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};
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/*
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* Device states
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*
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* Note that not all states are used by all devices.
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*/
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enum device_state {
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/* Initial state at boot */
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DEVICE_STATE_INIT = 0,
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/*
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* Detect was not asserted at boot, but we're not willing to give up on
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* the device right away so we're debouncing to see if it shows up.
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*/
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DEVICE_STATE_INIT_DEBOUNCING,
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/*
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* Device was detected at boot, but we can't enable transmit yet
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* because that would interfere with detection of another device.
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*/
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DEVICE_STATE_INIT_RX_ONLY,
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/* Disconnected or off, because detect is deasserted */
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DEVICE_STATE_DISCONNECTED,
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DEVICE_STATE_OFF,
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/* Device state is not knowable because we're driving detect */
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DEVICE_STATE_UNDETECTABLE,
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/* Connected or on, because detect is asserted */
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DEVICE_STATE_CONNECTED,
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DEVICE_STATE_ON,
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/*
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* Device was connected, but we saw detect deasserted and are
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* debouncing to see if it stays deasserted - at which point we'll
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* decide that it's disconnected.
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*/
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DEVICE_STATE_DEBOUNCING,
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/* Device state is unknown. Used only by legacy device_state code. */
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DEVICE_STATE_UNKNOWN,
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/* The state is being ignored. */
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DEVICE_STATE_IGNORED,
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/* Number of device states */
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DEVICE_STATE_COUNT
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};
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/**
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* Return the name of the device state as as string.
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*
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* @param state State to look up
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* @return Name of the state, or "?" if no match.
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*/
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const char *device_state_name(enum device_state state);
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/* NVMem variables. */
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enum nvmem_vars {
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NVMEM_VAR_CONSOLE_LOCKED = 0,
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NVMEM_VAR_TEST_VAR,
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NVMEM_VAR_U2F_SALT,
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NVMEM_VAR_CCD_CONFIG,
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NVMEM_VAR_G2F_SALT,
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NVMEM_VARS_COUNT
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};
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void board_configure_deep_sleep_wakepins(void);
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void ap_detect_asserted(enum gpio_signal signal);
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void ec_detect_asserted(enum gpio_signal signal);
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void servo_detect_asserted(enum gpio_signal signal);
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void tpm_rst_deasserted(enum gpio_signal signal);
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void tpm_rst_asserted(enum gpio_signal signal);
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void post_reboot_request(void);
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/* Special controls over EC and AP */
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void assert_sys_rst(void);
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void deassert_sys_rst(void);
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void assert_ec_rst(void);
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void deassert_ec_rst(void);
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int is_ec_rst_asserted(void);
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/* Ignore the servo state. */
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void servo_ignore(int enable);
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/**
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* Set up a deferred call to update CCD state.
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*
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* This will enable/disable UARTs, SPI, I2C, etc. as needed.
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*/
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void ccd_update_state(void);
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/**
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* Return the state of the BOARD_USE_PLT_RST board strap option.
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*
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* @return 0 if option is not set, !=0 if option set.
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*/
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int board_use_plt_rst(void);
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/**
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* Return the state of the BOARD_NEEDS_SYS_RST_PULL_UP board strap option.
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*
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* @return 0 if option is not set, !=0 if option set.
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*/
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int board_rst_pullup_needed(void);
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/**
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* Return the state of the BOARD_SLAVE_CONFIG_I2C board strap option.
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*
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* @return 0 if option is not set, !=0 if option set.
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*/
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int board_tpm_uses_i2c(void);
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/**
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* Return the state of the BOARD_SLAVE_CONFIG_SPI board strap option.
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*
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* @return 0 if option is not set, !=0 if option set.
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*/
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int board_tpm_uses_spi(void);
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/**
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* Return the state of the BOARD_CLOSED_SOURCE_SET1 board strap option.
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*
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* @return 0 if option is not set, !=0 if option set.
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*/
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int board_uses_closed_source_set1(void);
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/**
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* The board needs to wait until TPM_RST_L is asserted before deasserting
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* system reset signals.
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*
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* @return 0 if option is not set, !=0 if option set.
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*/
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int board_uses_closed_loop_reset(void);
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/**
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* The board has all necessary I2C pins connected for INA support.
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*
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* @return 0 if option is not set, !=0 if option set.
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*/
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int board_has_ina_support(void);
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/* The board allows vendor commands to enable/disable tpm. */
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int board_tpm_mode_change_allowed(void);
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int board_id_is_mismatched(void);
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/* Allow for deep sleep to be enabled on AP shutdown */
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int board_deep_sleep_allowed(void);
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void power_button_record(void);
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/**
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* Enable/disable power button release interrupt.
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*
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* @param enable Enable (!=0) or disable (==0)
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*/
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void power_button_release_enable_interrupt(int enable);
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/* Functions needed by CCD config */
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int board_battery_is_present(void);
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int board_fwmp_allows_unlock(void);
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int board_vboot_dev_mode_enabled(void);
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void board_reboot_ap(void);
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void board_reboot_ec(void);
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void board_closed_loop_reset(void);
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int board_wipe_tpm(int reset_required);
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int board_is_first_factory_boot(void);
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int usb_i2c_board_enable(void);
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void usb_i2c_board_disable(void);
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void print_ap_state(void);
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void print_ap_uart_state(void);
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void print_ec_state(void);
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void print_servo_state(void);
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int ap_is_on(void);
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int ap_uart_is_on(void);
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int ec_is_on(void);
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int ec_is_rx_allowed(void);
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int servo_is_connected(void);
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void set_ap_on(void);
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/* Returns True if chip is brought up in a factory test harness. */
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int chip_factory_mode(void);
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/*
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* Trigger generation of the ITE SYNC sequence on the way up after next
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* reboot.
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*/
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void board_start_ite_sync(void);
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#endif /* !__ASSEMBLER__ */
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/* USB interface indexes (use define rather than enum to expand them) */
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#define USB_IFACE_CONSOLE 0
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#define USB_IFACE_AP 1
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#define USB_IFACE_EC 2
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#define USB_IFACE_UPGRADE 3
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#define USB_IFACE_SPI 4
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#define USB_IFACE_I2C 5
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#define USB_IFACE_COUNT 6
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/* USB endpoint indexes (use define rather than enum to expand them) */
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#define USB_EP_CONTROL 0
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#define USB_EP_CONSOLE 1
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#define USB_EP_AP 2
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#define USB_EP_EC 3
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#define USB_EP_UPGRADE 4
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#define USB_EP_SPI 5
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#define USB_EP_I2C 6
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#define USB_EP_COUNT 7
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/* UART indexes (use define rather than enum to expand them) */
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#define UART_CR50 0
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#define UART_AP 1
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#define UART_EC 2
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#define UARTN UART_CR50
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#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_TPM))
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/* Nv Memory users */
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#ifndef __ASSEMBLER__
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enum nvmem_users {
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NVMEM_TPM = 0,
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NVMEM_CR50,
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NVMEM_NUM_USERS
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};
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#endif
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#define CONFIG_FLASH_NVMEM_VARS_USER_NUM NVMEM_CR50
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#define CONFIG_RW_B
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/* Firmware upgrade options. */
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#define CONFIG_NON_HC_FW_UPDATE
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#define CONFIG_USB_FW_UPDATE
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#define CONFIG_I2C
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#define CONFIG_I2C_MASTER
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#define CONFIG_I2C_SLAVE
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#define CONFIG_TPM_I2CS
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#define CONFIG_BOARD_ID_SUPPORT
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#define CONFIG_SN_BITS_SUPPORT
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#define CONFIG_EXTENDED_VERSION_INFO
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#define I2C_PORT_MASTER 0
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#define CONFIG_BASE32
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#define CONFIG_RMA_AUTH
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#define CONFIG_FACTORY_MODE
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#define CONFIG_RNG
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#define CONFIG_ENABLE_H1_ALERTS
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/* Enable hardware backed brute force resistance feature */
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#define CONFIG_PINWEAVER
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/*
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* Disabling p256 will result in RMA Auth falling back to the x25519 curve
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* which in turn would require extra 5328 bytes of flash space.
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*/
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#define CONFIG_RMA_AUTH_USE_P256
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#ifndef CONFIG_RMA_AUTH_USE_P256
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#define CONFIG_CURVE25519
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#endif
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#define CONFIG_CCD_ITE_PROGRAMMING
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/*
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* Increase sizes of USB over I2C read and write queues. Sizes are are such
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* that when appropriate overheads are included, total buffer sizes are powers
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* of 2 (2^9 in both cases below).
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*/
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#undef CONFIG_USB_I2C_MAX_WRITE_COUNT
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#undef CONFIG_USB_I2C_MAX_READ_COUNT
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#define CONFIG_USB_I2C_MAX_WRITE_COUNT 508
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#define CONFIG_USB_I2C_MAX_READ_COUNT 506
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/* The below time constants are way longer than should be required in practice:
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*
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* Time it takes to finish processing TPM command
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*/
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#define TPM_PROCESSING_TIME (1 * SECOND)
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/*
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* Time it takse TPM reset function to wipe out the NVMEM and reboot the
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* device.
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*/
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#define TPM_RESET_TIME (10 * SECOND)
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/* Total time deep sleep should not be allowed while wiping the TPM. */
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#define DISABLE_SLEEP_TIME_TPM_WIPE (TPM_PROCESSING_TIME + TPM_RESET_TIME)
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#endif /* __CROS_EC_BOARD_H */
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