328 lines
10 KiB
C
328 lines
10 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "adc.h"
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#include "chip/stm32/registers.h"
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#include "gpio.h"
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#include "ec_commands.h"
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/* USB Power delivery board configuration */
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#ifndef __CROS_EC_USB_PD_CONFIG_H
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#define __CROS_EC_USB_PD_CONFIG_H
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/* Timer selection for baseband PD communication */
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#define TIM_CLOCK_PD_TX_C0 16
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#define TIM_CLOCK_PD_RX_C0 1
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#define TIM_CLOCK_PD_TX_C1 15
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#define TIM_CLOCK_PD_RX_C1 3
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/* Timer channel */
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#define TIM_TX_CCR_C0 1
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#define TIM_RX_CCR_C0 1
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#define TIM_TX_CCR_C1 2
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#define TIM_RX_CCR_C1 1
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#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0)
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#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0)
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/* RX timer capture/compare register */
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#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
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#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1))
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#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0)
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/* TX and RX timer register */
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#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
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#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
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#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1))
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#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1))
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#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0)
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#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0)
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/* use the hardware accelerator for CRC */
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#define CONFIG_HW_CRC
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/* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */
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#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
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static inline void spi_enable_clock(int port)
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{
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if (port == 0)
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STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
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else
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STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
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}
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/* DMA for transmit uses DMA CH3 for C0 and DMA_CH5 for C1 */
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#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH5 : STM32_DMAC_CH3)
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/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/
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/* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */
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#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1
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/* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */
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#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
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#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
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#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
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#define TIM_CCR_CS 1
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/*
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* EXTI line 21 is connected to the CMP1 output,
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* EXTI line 22 is connected to the CMP2 output,
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* C0 uses CMP2, and C1 uses CMP1.
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*/
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#define EXTI_COMP_MASK(p) ((p) ? BIT(21) : BIT(22))
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#define IRQ_COMP STM32_IRQ_COMP
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/* triggers packet detection on comparator falling edge */
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#define EXTI_XTSR STM32_EXTI_FTSR
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/* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */
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#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH4 : STM32_DMAC_CH2)
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/* the pins used for communication need to be hi-speed */
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static inline void pd_set_pins_speed(int port)
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{
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if (port == 0) {
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/* 40 MHz pin speed on SPI PB3&4,
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* (USB_C0_TX_CLKIN & USB_C0_CC1_TX_DATA)
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*/
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0;
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/* 40 MHz pin speed on TIM16_CH1 (PB8),
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* (USB_C0_TX_CLKOUT)
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*/
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000;
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} else {
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/* 40 MHz pin speed on SPI PB13/14,
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* (USB_C1_TX_CLKIN & USB_C1_CCX_TX_DATA)
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*/
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000;
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/* 40 MHz pin speed on TIM15_CH2 (PB15) */
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000;
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}
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}
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/* Reset SPI peripheral used for TX */
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static inline void pd_tx_spi_reset(int port)
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{
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if (port == 0) {
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/* Reset SPI1 */
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STM32_RCC_APB2RSTR |= BIT(12);
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STM32_RCC_APB2RSTR &= ~BIT(12);
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} else {
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/* Reset SPI2 */
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STM32_RCC_APB1RSTR |= BIT(14);
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STM32_RCC_APB1RSTR &= ~BIT(14);
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}
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}
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/* Drive the CC line from the TX block */
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static inline void pd_tx_enable(int port, int polarity)
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{
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if (port == 0) {
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/* put SPI function on TX pin */
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if (polarity) {
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/* USB_C0_CC2_TX_DATA: PA6 is SPI1 MISO */
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gpio_set_alternate_function(GPIO_A, 0x0040, 0);
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/* MCU ADC PA4 pin output low */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*4))) /* PA4 disable ADC */
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| (1 << (2*4)); /* Set as GPO */
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gpio_set_level(GPIO_USB_C0_CC2_PD, 0);
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} else {
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/* USB_C0_CC1_TX_DATA: PB4 is SPI1 MISO */
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gpio_set_alternate_function(GPIO_B, 0x0010, 0);
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/* MCU ADC PA2 pin output low */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*2))) /* PA2 disable ADC */
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| (1 << (2*2)); /* Set as GPO */
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gpio_set_level(GPIO_USB_C0_CC1_PD, 0);
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}
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} else {
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/* put SPI function on TX pin */
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/* USB_C1_CCX_TX_DATA: PB14 is SPI1 MISO */
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gpio_set_alternate_function(GPIO_B, 0x4000, 0);
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/* MCU ADC pin output low */
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if (polarity) {
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*5))) /* PA5 disable ADC */
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| (1 << (2*5)); /* Set as GPO */
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gpio_set_level(GPIO_USB_C1_CC2_PD, 0);
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} else {
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*0))) /* PA0 disable ADC */
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| (1 << (2*0)); /* Set as GPO */
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gpio_set_level(GPIO_USB_C1_CC1_PD, 0);
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}
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/*
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* There is a pin muxer to select CC1 or CC2 TX_DATA,
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* Pin mux is controlled by USB_C1_CC2_TX_SEL pin,
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* USB_C1_CC1_TX_DATA will be selected, if polarity is 0,
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* USB_C1_CC2_TX_DATA will be selected, if polarity is 1 .
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*/
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gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity);
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}
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}
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/* Put the TX driver in Hi-Z state */
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static inline void pd_tx_disable(int port, int polarity)
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{
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if (port == 0) {
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if (polarity) {
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/* Set TX_DATA to Hi-Z, PA6 is SPI1 MISO */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*6)));
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/* set ADC PA4 pin to ADC function (Hi-Z) */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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| (3 << (2*4))); /* PA4 as ADC */
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} else {
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/* Set TX_DATA to Hi-Z, PB4 is SPI1 MISO */
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STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
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& ~(3 << (2*4)));
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/* set ADC PA2 pin to ADC function (Hi-Z) */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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| (3 << (2*2))); /* PA2 as ADC */
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}
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} else {
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/* Set TX_DATA (PB14) Hi-Z */
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STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
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& ~(3 << (2*14)));
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if (polarity) {
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/* set ADC PA5 pin to ADC function (Hi-Z) */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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| (3 << (2*5))); /* PA5 as ADC */
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} else {
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/* set ADC PA0 pin to ADC function (Hi-Z) */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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| (3 << (2*0))); /* PA0 as ADC */
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}
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}
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}
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/* we know the plug polarity, do the right configuration */
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static inline void pd_select_polarity(int port, int polarity)
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{
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uint32_t val = STM32_COMP_CSR;
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/* Use window mode so that COMP1 and COMP2 share non-inverting input */
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val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
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if (port == 0) {
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/* C0 use the right comparator inverted input for COMP2 */
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STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
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(polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */
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: STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
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} else {
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/* C1 use the right comparator inverted input for COMP1 */
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STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
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(polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */
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: STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
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}
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}
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/* Initialize pins used for TX and put them in Hi-Z */
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static inline void pd_tx_init(void)
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{
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gpio_config_module(MODULE_USB_PD, 1);
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}
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static inline void pd_set_host_mode(int port, int enable)
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{
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if (port == 0) {
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if (enable) {
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/* Pull up for host mode */
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gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_OUTPUT);
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gpio_set_level(GPIO_USB_C0_HOST_HIGH, 1);
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/* High-Z is used for host mode. */
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gpio_set_level(GPIO_USB_C0_CC1_ODL, 1);
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gpio_set_level(GPIO_USB_C0_CC2_ODL, 1);
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/* Set TX Hi-Z */
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gpio_set_flags(GPIO_USB_C0_CC1_TX_DATA, GPIO_INPUT);
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gpio_set_flags(GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
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} else {
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/* Set HOST_HIGH to High-Z for device mode. */
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gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_INPUT);
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/* Pull low for device mode. */
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gpio_set_level(GPIO_USB_C0_CC1_ODL, 0);
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gpio_set_level(GPIO_USB_C0_CC2_ODL, 0);
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}
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} else {
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if (enable) {
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/* Pull up for host mode */
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gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_OUTPUT);
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gpio_set_level(GPIO_USB_C1_HOST_HIGH, 1);
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/* High-Z is used for host mode. */
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gpio_set_level(GPIO_USB_C1_CC1_ODL, 1);
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gpio_set_level(GPIO_USB_C1_CC2_ODL, 1);
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/* Set TX Hi-Z */
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gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
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} else {
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/* Set HOST_HIGH to High-Z for device mode. */
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gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_INPUT);
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/* Pull low for device mode. */
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gpio_set_level(GPIO_USB_C1_CC1_ODL, 0);
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gpio_set_level(GPIO_USB_C1_CC2_ODL, 0);
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}
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}
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}
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/**
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* Initialize various GPIOs and interfaces to safe state at start of pd_task.
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*
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* These include:
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* VBUS, charge path based on power role.
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* Physical layer CC transmit.
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* VCONNs disabled.
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*
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* @param port USB-C port number
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* @param power_role Power role of device
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*/
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static inline void pd_config_init(int port, uint8_t power_role)
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{
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/*
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* Set CC pull resistors, and charge_en and vbus_en GPIOs to match
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* the initial role.
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*/
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pd_set_host_mode(port, power_role);
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/* Initialize TX pins and put them in Hi-Z */
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pd_tx_init();
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if (port == 0) {
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gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0);
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gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0);
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} else {
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gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN, 0);
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gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN, 0);
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}
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}
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static inline int pd_adc_read(int port, int cc)
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{
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if (port == 0)
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return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD);
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else
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return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD);
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}
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static inline void pd_set_vconn(int port, int polarity, int enable)
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{
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/* Set VCONN on the opposite CC line from the polarity */
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if (port == 0) {
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gpio_set_level(polarity ? GPIO_USB_C0_CC1_VCONN1_EN :
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GPIO_USB_C0_CC2_VCONN1_EN, enable);
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/* Set TX_DATA pin to Hi-Z */
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gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA :
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GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
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} else {
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gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN :
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GPIO_USB_C1_CC2_VCONN1_EN, enable);
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/* Set TX_DATA pin to Hi-Z */
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gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
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}
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}
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#endif /* __CROS_EC_USB_PD_CONFIG_H */
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