249 lines
9.9 KiB
C
249 lines
9.9 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USB Power delivery port management */
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#ifndef __CROS_EC_USB_PD_TCPM_TCPCI_H
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#define __CROS_EC_USB_PD_TCPM_TCPCI_H
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#include "config.h"
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#include "tcpm.h"
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#include "usb_mux.h"
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#include "usb_pd_tcpm.h"
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#define TCPC_REG_VENDOR_ID 0x0
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#define TCPC_REG_PRODUCT_ID 0x2
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#define TCPC_REG_BCD_DEV 0x4
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#define TCPC_REG_TC_REV 0x6
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#define TCPC_REG_PD_REV 0x8
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#define TCPC_REG_PD_INT_REV 0xa
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#define TCPC_REG_ALERT 0x10
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#define TCPC_REG_ALERT_MASK_ALL 0xffff
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#define TCPC_REG_ALERT_VENDOR_DEF BIT(15)
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#define TCPC_REG_ALERT_ALERT_EXT BIT(14)
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#define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
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#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10)
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#define TCPC_REG_ALERT_FAULT BIT(9)
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#define TCPC_REG_ALERT_V_ALARM_LO BIT(8)
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#define TCPC_REG_ALERT_V_ALARM_HI BIT(7)
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#define TCPC_REG_ALERT_TX_SUCCESS BIT(6)
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#define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
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#define TCPC_REG_ALERT_TX_FAILED BIT(4)
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#define TCPC_REG_ALERT_RX_HARD_RST BIT(3)
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#define TCPC_REG_ALERT_RX_STATUS BIT(2)
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#define TCPC_REG_ALERT_POWER_STATUS BIT(1)
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#define TCPC_REG_ALERT_CC_STATUS BIT(0)
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#define TCPC_REG_ALERT_TX_COMPLETE (TCPC_REG_ALERT_TX_SUCCESS | \
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TCPC_REG_ALERT_TX_DISCARDED | \
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TCPC_REG_ALERT_TX_FAILED)
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#define TCPC_REG_ALERT_MASK 0x12
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#define TCPC_REG_POWER_STATUS_MASK 0x14
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#define TCPC_REG_FAULT_STATUS_MASK 0x15
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#define TCPC_REG_EXTENDED_STATUS_MASK 0x16
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#define TCPC_REG_ALERT_EXTENDED_MASK 0x17
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#define TCPC_REG_CONFIG_STD_OUTPUT 0x18
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#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2)
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#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2)
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#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2)
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#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2)
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#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
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#define TCPC_REG_TCPC_CTRL 0x19
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#define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity)
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#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1)
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/*
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* In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when
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* a connection is found.
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*/
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#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT (BIT(6))
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#define TCPC_REG_ROLE_CTRL 0x1a
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#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6)
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#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5)|BIT(4))
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#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3)|BIT(2))
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#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1)|BIT(0))
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#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \
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((drp) << 6 | (rp) << 4 | (cc2) << 2 | (cc1))
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#define TCPC_REG_ROLE_CTRL_DRP(reg) \
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(((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
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#define TCPC_REG_ROLE_CTRL_RP(reg) \
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(((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
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#define TCPC_REG_ROLE_CTRL_CC2(reg) \
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(((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
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#define TCPC_REG_ROLE_CTRL_CC1(reg) \
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((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)
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#define TCPC_REG_FAULT_CTRL 0x1b
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#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1)
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#define TCPC_REG_POWER_CTRL 0x1c
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#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7)
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#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6)
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#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4)
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#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2)
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#define TCPC_REG_POWER_CTRL_SET(vconn) (vconn)
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#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1)
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#define TCPC_REG_CC_STATUS 0x1d
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#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5)
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#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4)
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#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3)|BIT(2))
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#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1)|BIT(0))
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#define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \
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((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3))
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#define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \
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((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5)
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#define TCPC_REG_CC_STATUS_TERM(reg) \
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(((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4)
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#define TCPC_REG_CC_STATUS_CC2(reg) \
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(((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
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#define TCPC_REG_CC_STATUS_CC1(reg) \
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((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)
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#define TCPC_REG_POWER_STATUS 0x1e
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#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff
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#define TCPC_REG_POWER_STATUS_UNINIT BIT(6)
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#define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
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#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3)
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#define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2)
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#define TCPC_REG_FAULT_STATUS 0x1f
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#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7)
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#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6)
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#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5)
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#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4)
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#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3)
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#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2)
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#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1)
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#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0)
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#define TCPC_REG_ALERT_EXT 0x21
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#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2)
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#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1)
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#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0)
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#define TCPC_REG_COMMAND 0x23
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#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33
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#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44
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#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55
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#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66
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#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77
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#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99
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#define TCPC_REG_COMMAND_I2CIDLE 0xFF
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#define TCPC_REG_DEV_CAP_1 0x24
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#define TCPC_REG_DEV_CAP_2 0x26
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#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9)
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#define TCPC_REG_STD_INPUT_CAP 0x28
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#define TCPC_REG_STD_OUTPUT_CAP 0x29
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#define TCPC_REG_CONFIG_EXT_1 0x2A
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#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1)
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#define TCPC_REG_MSG_HDR_INFO 0x2e
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#define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \
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((drole) << 3 | (PD_REV20 << 1) | (prole))
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#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3)
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#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1)
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#define TCPC_REG_RX_DETECT 0x2f
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#define TCPC_REG_RX_DETECT_SOP_HRST_MASK 0x21
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#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK 0x27
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/* TCPCI Rev 1.0 receive registers */
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#define TCPC_REG_RX_BYTE_CNT 0x30
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#define TCPC_REG_RX_BUF_FRAME_TYPE 0x31
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#define TCPC_REG_RX_HDR 0x32
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#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */
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/*
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* In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers:
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* READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can
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* only be accessed by reading at a common register address 30h.
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*/
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#define TCPC_REG_RX_BUFFER 0x30
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#define TCPC_REG_TRANSMIT 0x50
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#define TCPC_REG_TRANSMIT_SET_WITH_RETRY(type) \
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(PD_RETRY_COUNT << 4 | (type))
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#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type)
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#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4)
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#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg) & 0x7)
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/* TCPCI Rev 1.0 transmit registers */
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#define TCPC_REG_TX_BYTE_CNT 0x51
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#define TCPC_REG_TX_HDR 0x52
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#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */
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/*
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* In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the
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* portion of the SOP* USB PD message payload (including the header and/or the
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* data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x
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* is “hidden” and can only be accessed by writing to register address 51h
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*/
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#define TCPC_REG_TX_BUFFER 0x51
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#define TCPC_REG_VBUS_VOLTAGE 0x70
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#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72
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#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74
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#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76
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#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78
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extern const struct tcpm_drv tcpci_tcpm_drv;
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extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver;
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void tcpci_set_cached_rp(int port, int rp);
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int tcpci_get_cached_rp(int port);
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void tcpci_set_cached_pull(int port, enum tcpc_cc_pull pull);
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enum tcpc_cc_pull tcpci_get_cached_pull(int port);
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void tcpci_tcpc_alert(int port);
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int tcpci_tcpm_init(int port);
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int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
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enum tcpc_cc_voltage_status *cc2);
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int tcpci_tcpm_get_vbus_level(int port);
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int tcpci_tcpm_select_rp_value(int port, int rp);
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int tcpci_tcpm_set_cc(int port, int pull);
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int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity);
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int tcpci_tcpm_set_vconn(int port, int enable);
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int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role);
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int tcpci_tcpm_set_rx_enable(int port, int enable);
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int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head);
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int tcpci_tcpm_transmit(int port, enum tcpm_transmit_type type,
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uint16_t header, const uint32_t *data);
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int tcpci_tcpm_release(int port);
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#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
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int tcpci_set_role_ctrl(int port, int toggle, int rp, int pull);
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int tcpci_tcpc_drp_toggle(int port);
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int tcpci_tcpc_set_connection(int port, enum tcpc_cc_pull pull,
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int connect);
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#endif
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#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
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int tcpci_enter_low_power_mode(int port);
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#endif
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#ifdef CONFIG_USB_PD_DISCHARGE_TCPC
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void tcpci_tcpc_discharge_vbus(int port, int enable);
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#endif
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void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable);
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int tcpci_tcpm_mux_init(const struct usb_mux *me);
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int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state);
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int tcpci_tcpm_mux_get(const struct usb_mux *me, mux_state_t *mux_state);
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int tcpci_get_chip_info(int port, int live,
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struct ec_response_pd_chip_info_v1 **chip_info);
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#ifdef CONFIG_USBC_PPC
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int tcpci_tcpm_set_snk_ctrl(int port, int enable);
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int tcpci_tcpm_set_src_ctrl(int port, int enable);
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#endif
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void tcpci_tcpc_fast_role_swap_enable(int port, int enable);
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#endif /* __CROS_EC_USB_PD_TCPM_TCPCI_H */
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