542 lines
14 KiB
C
542 lines
14 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* I2C port module for ISH */
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#include "common.h"
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#include "console.h"
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#include "config_chip.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "i2c.h"
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#include "registers.h"
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#include "ish_i2c.h"
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#include "task.h"
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#include "timer.h"
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#include "hwtimer.h"
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#include "util.h"
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#define CPUTS(outstr) cputs(CC_I2C, outstr)
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#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
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#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
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/*25MHz, 50MHz, 100MHz, 120MHz, 40MHz, 20MHz, 37MHz*/
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static uint16_t default_hcnt_scl_100[] = {
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4000, 4420, 4920, 4400, 4000, 4000, 4300
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};
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static uint16_t default_lcnt_scl_100[] = {
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4720, 5180, 4990, 5333, 4700, 5200, 4950
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};
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static uint16_t default_hcnt_scl_400[] = {
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600, 820, 1120, 800, 600, 600, 450
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};
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static uint16_t default_lcnt_scl_400[] = {
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1320, 1380, 1300, 1550, 1300, 1200, 1250
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};
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static uint16_t default_hcnt_scl_1000[] = {
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260, 260, 260, 305, 260, 260, 260
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};
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static uint16_t default_lcnt_scl_1000[] = {
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500, 500, 500, 525, 500, 500, 500
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};
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static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 };
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static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 };
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static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
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I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120
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};
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static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = {
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{
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.bus = 0,
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.base = (uint32_t *) ISH_I2C0_BASE,
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.speed = I2C_SPEED_400KHZ,
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.int_pin = ISH_I2C0_IRQ,
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},
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{
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.bus = 1,
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.base = (uint32_t *) ISH_I2C1_BASE,
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.speed = I2C_SPEED_400KHZ,
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.int_pin = ISH_I2C1_IRQ,
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},
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{
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.bus = 2,
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.base = (uint32_t *) ISH_I2C2_BASE,
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.speed = I2C_SPEED_400KHZ,
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.int_pin = ISH_I2C2_IRQ,
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},
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};
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static struct i2c_bus_info board_config[ISH_I2C_PORT_COUNT] = {
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{
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.bus_id = 0,
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.std_speed.sda_hold = DEFAULT_SDA_HOLD_STD,
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.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
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.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
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.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
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},
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{
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.bus_id = 1,
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.std_speed.sda_hold = DEFAULT_SDA_HOLD_STD,
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.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
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.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
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.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
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},
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{
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.bus_id = 2,
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.std_speed.sda_hold = DEFAULT_SDA_HOLD_STD,
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.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
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.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
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.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
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},
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};
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static inline void i2c_mmio_write(uint32_t *base, uint8_t offset,
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uint32_t data)
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{
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REG32((uint32_t) ((uint8_t *)base + offset)) = data;
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}
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static inline uint32_t i2c_mmio_read(uint32_t *base, uint8_t offset)
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{
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return REG32((uint32_t) ((uint8_t *)base + offset));
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}
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static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg,
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uint8_t offset)
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{
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uint32_t ret = i2c_mmio_read(addr, reg) >> offset;
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return ret & 0xff;
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}
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static void i2c_intr_switch(uint32_t *base, int mode)
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{
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switch (mode) {
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case ENABLE_WRITE_INT:
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i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_WRITE_MASK_VAL);
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break;
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case ENABLE_READ_INT:
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i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_READ_MASK_VAL);
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break;
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case DISABLE_INT:
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i2c_mmio_write(base, IC_INTR_MASK, 0);
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/* clear interrupts: TX_ABORT
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* Because the DW_apb_i2c's TX FIFO is forced into a
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* flushed/reset state whenever a TX_ABRT event occurs, it
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* is necessary for software to release the DW_apb_i2c from
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* this state by reading the IC_CLR_TX_ABRT register before
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* attempting to write into the TX FIFO
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*/
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i2c_mmio_read(base, IC_CLR_TX_ABRT);
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/* STOP_DET */
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i2c_mmio_read(base, IC_CLR_STOP_DET);
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break;
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default:
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break;
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}
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}
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static void i2c_init_transaction(struct i2c_context *ctx,
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uint16_t slave_addr, uint8_t flags)
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{
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uint32_t con_value;
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uint32_t *base = ctx->base;
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struct i2c_bus_info *bus_info = &board_config[ctx->bus];
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uint32_t clk_in_val = clk_in[bus_freq[ctx->bus]];
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/* disable interrupts */
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i2c_intr_switch(base, DISABLE_INT);
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i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
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i2c_mmio_write(base, IC_TAR, (slave_addr << IC_TAR_OFFSET) |
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TAR_SPECIAL_VAL | IC_10BITADDR_MASTER_VAL);
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/* set Clock SCL Count */
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switch (ctx->speed) {
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case I2C_SPEED_100KHZ:
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i2c_mmio_write(base, IC_SS_SCL_HCNT,
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NS_2_COUNTERS(bus_info->std_speed.hcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_SS_SCL_LCNT,
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NS_2_COUNTERS(bus_info->std_speed.lcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_SDA_HOLD,
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NS_2_COUNTERS(bus_info->std_speed.sda_hold,
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clk_in_val));
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break;
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case I2C_SPEED_400KHZ:
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i2c_mmio_write(base, IC_FS_SCL_HCNT,
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NS_2_COUNTERS(bus_info->fast_speed.hcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_FS_SCL_LCNT,
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NS_2_COUNTERS(bus_info->fast_speed.lcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_SDA_HOLD,
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NS_2_COUNTERS(bus_info->fast_speed.sda_hold,
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clk_in_val));
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break;
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case I2C_SPEED_1MHZ:
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i2c_mmio_write(base, IC_FS_SCL_HCNT,
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NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_FS_SCL_LCNT,
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NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_SDA_HOLD,
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NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold,
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clk_in_val));
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break;
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case I2C_SPEED_3M4HZ:
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i2c_mmio_write(base, IC_HS_SCL_HCNT,
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NS_2_COUNTERS(bus_info->high_speed.hcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_HS_SCL_LCNT,
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NS_2_COUNTERS(bus_info->high_speed.lcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_SDA_HOLD,
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NS_2_COUNTERS(bus_info->high_speed.sda_hold,
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clk_in_val));
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i2c_mmio_write(base, IC_FS_SCL_HCNT,
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NS_2_COUNTERS(bus_info->fast_speed.hcnt,
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clk_in_val));
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i2c_mmio_write(base, IC_FS_SCL_LCNT,
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NS_2_COUNTERS(bus_info->fast_speed.lcnt,
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clk_in_val));
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break;
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default:
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break;
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}
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/* in SPT HW we need to sync between I2C clock and data signals */
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con_value = i2c_mmio_read(base, IC_CON);
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if (flags != 0)
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con_value |= IC_RESTART_EN_VAL;
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else
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con_value &= ~IC_RESTART_EN_VAL;
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i2c_mmio_write(base, IC_CON, con_value);
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i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]);
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i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]);
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i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_ENABLE);
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}
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static void i2c_write_buffer(uint32_t *base, uint8_t len,
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const uint8_t *buffer, ssize_t *cur_index,
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ssize_t total_len)
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{
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int i;
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uint16_t out;
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for (i = 0; i < len; i++) {
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++(*cur_index);
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out = (buffer[i] << DATA_CMD_DAT_OFFSET) | DATA_CMD_WRITE_VAL;
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/* if Write ONLY and Last byte */
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if (*cur_index == total_len) {
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out |= DATA_CMD_STOP_VAL;
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}
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i2c_mmio_write(base, IC_DATA_CMD, out);
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}
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}
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static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data,
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unsigned restart_flag)
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{
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/* this routine just set RX FIFO's control bit(s),
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* READ command or RESTART */
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int i;
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uint32_t data_cmd;
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for (i = 0; i < len; i++) {
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data_cmd = DATA_CMD_READ_VAL;
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if ((i == 0) && restart_flag)
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/* if restart for first byte */
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data_cmd |= DATA_CMD_RESTART_VAL;
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/* if last byte & less than FIFO size
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* or only one byte to read */
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if (i == (len - 1) && !more_data)
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data_cmd |= DATA_CMD_STOP_VAL;
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i2c_mmio_write(base, IC_DATA_CMD, data_cmd);
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}
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}
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int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
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const uint8_t *out, int out_size,
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uint8_t *in, int in_size, int flags)
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{
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int i;
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ssize_t total_len;
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uint64_t expire_ts;
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struct i2c_context *ctx;
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ssize_t curr_index = 0;
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uint16_t addr = I2C_GET_ADDR(slave_addr_flags);
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int begin_indx;
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uint8_t repeat_start = 0;
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if (out_size == 0 && in_size == 0)
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return EC_SUCCESS;
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if (port < 0 || port >= ISH_I2C_PORT_COUNT)
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return EC_ERROR_INVAL;
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/* Check for reserved I2C addresses, pg. 74 in DW_apb_i2c.pdf
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* Address cannot be any of the reserved address locations:
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* 0x00 to 0x07 or 0x78 to 0x7f.
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*/
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if (addr <= 0x07 || (addr >= 0x78 && addr <= 0x7F))
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return EC_ERROR_INVAL;
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/* assume that if both out_size and in_size are not zero,
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* then, it is 'repeated Start' condition. */
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if (in_size != 0 && out_size != 0)
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repeat_start = 1;
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ctx = &i2c_ctxs[port];
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ctx->error_flag = 0;
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ctx->wait_task_id = task_get_current();
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total_len = in_size + out_size;
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i2c_init_transaction(ctx, addr, repeat_start);
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/* Write W data */
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if (out_size)
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i2c_write_buffer(ctx->base, out_size, out,
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&curr_index, total_len);
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/* Wait here until Tx is completed so that FIFO becomes empty.
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* This is optimized for smaller Tx data size.
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* If need to write big data ( > ISH_I2C_FIFO_SIZE ),
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* it is better to use Tx FIFO threshold interrupt(as in Rx) for
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* better CPU usuage.
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* */
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expire_ts = __hw_clock_source_read() + I2C_TX_FLUSH_TIMEOUT_USEC;
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if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) {
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while ((i2c_mmio_read(ctx->base, IC_STATUS) &
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BIT(IC_STATUS_TFE)) == 0) {
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if (__hw_clock_source_read() >= expire_ts) {
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ctx->error_flag = 1;
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break;
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}
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CPU_RELAX();
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}
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}
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begin_indx = 0;
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while (in_size) {
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int rd_size; /* read size for on i2c transaction */
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/*
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* check if in_size > ISH_I2C_FIFO_SIZE, then try to read
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* FIFO_SIZE each time.
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*/
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if (in_size > ISH_I2C_FIFO_SIZE) {
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rd_size = ISH_I2C_FIFO_SIZE;
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in_size -= ISH_I2C_FIFO_SIZE;
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} else {
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rd_size = in_size;
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in_size = 0;
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}
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/* Set rx_threshold */
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i2c_mmio_write(ctx->base, IC_RX_TL, rd_size - 1);
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i2c_intr_switch(ctx->base, ENABLE_READ_INT);
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/*
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* RESTART only once for entire i2c transaction.
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* assume that if both out_size and in_size are not zero,
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* then, it is 'repeated Start' condition.
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* set R commands bit, start to read
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*/
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i2c_write_read_commands(ctx->base, rd_size, in_size,
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(begin_indx == 0) && (repeat_start != 0));
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/* need timeout in case no ACK from slave */
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task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2*MSEC);
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if (ctx->interrupts & M_TX_ABRT) {
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ctx->error_flag = 1;
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break; /* when bus abort, no more reading !*/
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}
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/* read data */
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for (i = begin_indx; i < begin_indx + rd_size; i++)
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in[i] = i2c_read_byte(ctx->base,
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IC_DATA_CMD, 0);
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begin_indx += rd_size;
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} /* while (in_size) */
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ctx->reason = 0;
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ctx->interrupts = 0;
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/* do not disable device before master is idle */
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expire_ts = __hw_clock_source_read() + I2C_TSC_TIMEOUT;
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while ((i2c_mmio_read(ctx->base, IC_STATUS) &
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(BIT(IC_STATUS_MASTER_ACTIVITY) | BIT(IC_STATUS_TFE))) !=
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BIT(IC_STATUS_TFE)) {
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if (__hw_clock_source_read() >= expire_ts) {
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ctx->error_flag = 1;
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break;
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}
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}
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i2c_intr_switch(ctx->base, DISABLE_INT);
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i2c_mmio_write(ctx->base, IC_ENABLE, IC_ENABLE_DISABLE);
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if (ctx->error_flag)
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return EC_ERROR_INVAL;
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return EC_SUCCESS;
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}
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static void i2c_interrupt_handler(struct i2c_context *ctx)
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{
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uint32_t raw_intr;
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if (IS_ENABLED(INTR_DEBUG))
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raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base,
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IC_RAW_INTR_STAT);
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/* check interrupts */
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ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT);
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ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE);
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if (IS_ENABLED(INTR_DEBUG))
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CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, "
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"RAW_INTR_STAT = 0x%04x",
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ctx->interrupts, ctx->reason, raw_intr);
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/* disable interrupts */
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i2c_intr_switch(ctx->base, DISABLE_INT);
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task_set_event(ctx->wait_task_id, TASK_EVENT_I2C_IDLE, 0);
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}
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static void i2c_isr_bus0(void)
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{
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i2c_interrupt_handler(&i2c_ctxs[0]);
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}
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DECLARE_IRQ(ISH_I2C0_IRQ, i2c_isr_bus0);
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static void i2c_isr_bus1(void)
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{
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i2c_interrupt_handler(&i2c_ctxs[1]);
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}
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DECLARE_IRQ(ISH_I2C1_IRQ, i2c_isr_bus1);
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static void i2c_isr_bus2(void)
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{
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i2c_interrupt_handler(&i2c_ctxs[2]);
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}
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DECLARE_IRQ(ISH_I2C2_IRQ, i2c_isr_bus2);
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static void i2c_config_speed(struct i2c_context *ctx, int kbps)
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{
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if (kbps > 1000)
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ctx->speed = I2C_SPEED_3M4HZ;
|
|
else if (kbps > 400)
|
|
ctx->speed = I2C_SPEED_1MHZ;
|
|
else if (kbps > 100)
|
|
ctx->speed = I2C_SPEED_400KHZ;
|
|
else
|
|
ctx->speed = I2C_SPEED_100KHZ;
|
|
|
|
}
|
|
|
|
static void i2c_init_hardware(struct i2c_context *ctx)
|
|
{
|
|
static const uint8_t speed_val_arr[] = {
|
|
[I2C_SPEED_100KHZ] = STD_SPEED_VAL,
|
|
[I2C_SPEED_400KHZ] = FAST_SPEED_VAL,
|
|
[I2C_SPEED_1MHZ] = FAST_SPEED_VAL,
|
|
[I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL,
|
|
};
|
|
|
|
uint32_t *base = ctx->base;
|
|
|
|
/* disable interrupts */
|
|
i2c_intr_switch(base, DISABLE_INT);
|
|
i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
|
|
i2c_mmio_write(base, IC_CON, (MASTER_MODE_VAL
|
|
| speed_val_arr[ctx->speed]
|
|
| IC_RESTART_EN_VAL
|
|
| IC_SLAVE_DISABLE_VAL));
|
|
|
|
i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]);
|
|
i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]);
|
|
|
|
/* get RX_FIFO and TX_FIFO depth */
|
|
ctx->max_rx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
|
|
RX_BUFFER_DEPTH_OFFSET) + 1;
|
|
ctx->max_tx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
|
|
TX_BUFFER_DEPTH_OFFSET) + 1;
|
|
}
|
|
|
|
static void i2c_initial_board_config(struct i2c_context *ctx)
|
|
{
|
|
uint8_t freq = bus_freq[ctx->bus];
|
|
struct i2c_bus_info *bus_info = &board_config[ctx->bus];
|
|
|
|
bus_info->std_speed.hcnt = default_hcnt_scl_100[freq];
|
|
bus_info->std_speed.lcnt = default_lcnt_scl_100[freq];
|
|
|
|
bus_info->fast_speed.hcnt = default_hcnt_scl_400[freq];
|
|
bus_info->fast_speed.lcnt = default_lcnt_scl_400[freq];
|
|
|
|
bus_info->fast_plus_speed.hcnt = default_hcnt_scl_1000[freq];
|
|
bus_info->fast_plus_speed.lcnt = default_lcnt_scl_1000[freq];
|
|
|
|
bus_info->high_speed.hcnt = default_hcnt_scl_hs[freq];
|
|
bus_info->high_speed.lcnt = default_lcnt_scl_hs[freq];
|
|
}
|
|
|
|
static void i2c_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < i2c_ports_used; i++) {
|
|
int port = i2c_ports[i].port;
|
|
i2c_initial_board_config(&i2c_ctxs[port]);
|
|
/* Config speed from i2c_ports[] defined in board.c */
|
|
i2c_config_speed(&i2c_ctxs[port], i2c_ports[i].kbps);
|
|
i2c_init_hardware(&i2c_ctxs[port]);
|
|
|
|
task_enable_irq((&i2c_ctxs[port])->int_pin);
|
|
}
|
|
|
|
CPRINTS("Done i2c_init");
|
|
}
|
|
DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_INIT_I2C);
|