73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CHIP_CONFIG_H
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#define __CROS_EC_CHIP_CONFIG_H
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/* 16.000 Mhz internal oscillator frequency (PIOSC) */
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#define INTERNAL_CLOCK 16000000
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/* Memory mapping */
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#define CONFIG_FLASH_BASE 0x00000000
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#define CONFIG_FLASH_SIZE 0x00040000
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#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* Protect bank size */
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#define CONFIG_RAM_BASE 0x20000000
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#define CONFIG_RAM_SIZE 0x00008000
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/* Size of one firmware image in flash */
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#define CONFIG_FW_IMAGE_SIZE (80 * 1024)
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#define CONFIG_FW_RO_OFF 0
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#define CONFIG_FW_A_OFF CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_B_OFF (2 * CONFIG_FW_IMAGE_SIZE)
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/* We'll put the vboot stuff at the top of each image, since the vector table
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* has to go at the start. 4K should be enough for what we need. 2K isn't. */
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#define CONFIG_VBOOT_REGION_SIZE 0x1000
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#define CONFIG_VBOOT_ROOTKEY_SIZE 0x800
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#define CONFIG_VBOOT_REGION_OFF (CONFIG_FW_IMAGE_SIZE \
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- CONFIG_VBOOT_REGION_SIZE)
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/* Specifics for each image */
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#define CONFIG_FW_RO_SIZE CONFIG_VBOOT_REGION_OFF
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#define CONFIG_FW_A_SIZE CONFIG_VBOOT_REGION_OFF
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#define CONFIG_FW_B_SIZE CONFIG_VBOOT_REGION_OFF
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#define CONFIG_VBOOT_ROOTKEY_OFF (CONFIG_FW_RO_OFF \
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+ CONFIG_VBOOT_REGION_OFF)
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#define CONFIG_FMAP_OFF (CONFIG_VBOOT_ROOTKEY_OFF \
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+ CONFIG_VBOOT_ROOTKEY_SIZE)
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#define CONFIG_VBLOCK_A_OFF (CONFIG_FW_A_OFF + CONFIG_FW_A_SIZE)
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#define CONFIG_VBLOCK_B_OFF (CONFIG_FW_B_OFF + CONFIG_FW_B_SIZE)
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#define CONFIG_VBLOCK_A_SIZE CONFIG_VBOOT_REGION_SIZE
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#define CONFIG_VBLOCK_B_SIZE CONFIG_VBOOT_REGION_SIZE
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 132
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/* Debug UART parameters for panic message */
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#define CONFIG_UART_ADDRESS 0x4000c000
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#define CONFIG_UART_DR_OFFSET 0x00
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#define CONFIG_UART_SR_OFFSET 0x18
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#define CONFIG_UART_SR_TXEMPTY 0x80
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/* System stack size */
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#define CONFIG_STACK_SIZE 4096
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/* build with assertions and debug messages */
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#define CONFIG_DEBUG
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/* Optional features present on this chip */
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#define CONFIG_ADC
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#define CONFIG_EEPROM
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#define CONFIG_FLASH
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#define CONFIG_VBOOT
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#define CONFIG_FPU
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#define CONFIG_I2C
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#define CONFIG_LPC
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#define CONFIG_PWM
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/* Compile for running from RAM instead of flash */
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/* #define COMPILE_FOR_RAM */
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#endif /* __CROS_EC_CHIP_CONFIG_H */
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