114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/* Copyright 2020 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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#include <devicetree.h>
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/*
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* This file translates Kconfig options to platform/ec options.
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*
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* Options which are from Zephyr platform/ec module (Kconfig) start
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* with CONFIG_PLATFORM_EC_, and can be found in the Kconfig file.
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*
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* Options which are for the platform/ec configuration can be found in
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* common/config.h.
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*/
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#define CONFIG_ZEPHYR
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#define CHROMIUM_EC
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/* Chipset and power configuration */
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#ifdef CONFIG_AP_X86_INTEL_TGL
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#define CONFIG_CHIPSET_TIGERLAKE
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#endif
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/* eSPI configuration */
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#ifdef CONFIG_PLATFORM_EC_ESPI
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#ifdef CONFIG_PLATFORM_EC_HOSTCMD
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#define CONFIG_HOSTCMD_ESPI
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#endif
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/* eSPI signals */
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#ifdef CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3
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#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
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#endif
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#ifdef CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4
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#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
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#endif
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#endif /* CONFIG_PLATFORM_EC_ESPI */
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#ifdef CONFIG_PLATFORM_EC_I2C
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/* Also see shim/include/i2c/i2c.h which defines the ports enum */
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#define CONFIG_I2C
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#endif
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#undef CONFIG_KEYBOARD_PROTOCOL_8042
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#ifdef CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042
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#define CONFIG_KEYBOARD_PROTOCOL_8042
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#endif /* CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042 */
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#undef CONFIG_CMD_KEYBOARD
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#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_KEYBOARD_8042
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#define CONFIG_CMD_KEYBOARD
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#endif
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#undef CONFIG_KEYBOARD_COL2_INVERTED
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#ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
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#define CONFIG_KEYBOARD_COL2_INVERTED
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#endif /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */
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#ifdef CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
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#define CONFIG_CHIPSET_CPU_PROCHOT_ACTIVE_LOW
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#endif
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#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY
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#define CONFIG_CHIPSET_X86_RSMRST_DELAY
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#endif
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#ifdef CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE
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#define CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
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#endif
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#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP3300_RAIL_FIRST
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#define CONFIG_CHIPSET_PP3300_RAIL_FIRST
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#endif
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#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET
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#define CONFIG_BOARD_HAS_RTC_RESET
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#endif
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#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL
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#define CONFIG_POWER_PP5000_CONTROL
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#endif
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#ifdef CONFIG_PLATFORM_EC_TIMER
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#define CONFIG_HWTIMER_64BIT
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#define CONFIG_HW_SPECIFIC_UDELAY
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#undef CONFIG_WATCHDOG
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#undef CONFIG_CMD_GETTIME
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#ifdef CONFIG_PLATFORM_EC_TIMER_CMD_GETTIME
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#define CONFIG_CMD_GETTIME
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#endif /* CONFIG_PLATFORM_EC_TIMER_CMD_GETTIME */
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#undef CONFIG_CMD_TIMERINFO
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#ifdef CONFIG_PLATFORM_EC_TIMER_CMD_TIMERINFO
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#define CONFIG_CMD_TIMERINFO
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#endif /* CONFIG_PLATFORM_EC_TIMER_CMD_TIMERINFO */
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#undef CONFIG_CMD_WAITMS
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#ifdef CONFIG_PLATFORM_EC_TIMER_CMD_WAITMS
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#define CONFIG_CMD_WAITMS
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#endif /* CONFIG_PLATFORM_EC_TIMER_CMD_TIMERINFO */
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#endif /* CONFIG_PLATFORM_EC_TIMER */
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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