343 lines
8.7 KiB
C
343 lines
8.7 KiB
C
/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Icelake chipset power control module for Chrome EC */
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#include "board_config.h"
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#include "chipset.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "power.h"
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#include "power/intel_x86.h"
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#include "power_button.h"
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#include "task.h"
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#include "timer.h"
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/* Console output macros */
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#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
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#ifdef CONFIG_BRINGUP
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#define GPIO_SET_LEVEL(signal, value) \
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gpio_set_level_verbose(CC_CHIPSET, signal, value)
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#else
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#define GPIO_SET_LEVEL(signal, value) \
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gpio_set_level(signal, value)
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#endif
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/* The wait time is ~150 msec, allow for safety margin. */
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#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC)
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static int forcing_shutdown; /* Forced shutdown in progress? */
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/* Power signals list. Must match order of enum power_signal. */
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const struct power_signal_info power_signal_list[] = {
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[X86_SLP_S0_DEASSERTED] = {
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.gpio = GPIO_PCH_SLP_S0_L,
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.flags = POWER_SIGNAL_ACTIVE_HIGH |
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POWER_SIGNAL_DISABLE_AT_BOOT,
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.name = "SLP_S0_DEASSERTED",
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},
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[X86_SLP_S3_DEASSERTED] = {
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.gpio = SLP_S3_SIGNAL_L,
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.flags = POWER_SIGNAL_ACTIVE_HIGH,
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.name = "SLP_S3_DEASSERTED",
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},
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[X86_SLP_S4_DEASSERTED] = {
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.gpio = SLP_S4_SIGNAL_L,
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.flags = POWER_SIGNAL_ACTIVE_HIGH,
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.name = "SLP_S4_DEASSERTED",
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},
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[X86_SLP_SUS_DEASSERTED] = {
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.gpio = GPIO_SLP_SUS_L,
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.flags = POWER_SIGNAL_ACTIVE_HIGH,
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.name = "SLP_SUS_DEASSERTED",
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},
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[X86_RSMRST_L_PGOOD] = {
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.gpio = GPIO_PG_EC_RSMRST_ODL,
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.flags = POWER_SIGNAL_ACTIVE_HIGH,
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.name = "RSMRST_L_PGOOD",
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},
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[X86_DSW_DPWROK] = {
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.gpio = GPIO_PG_EC_DSW_PWROK,
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.flags = POWER_SIGNAL_ACTIVE_HIGH,
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.name = "DSW_DPWROK",
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},
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[X86_ALL_SYS_PGOOD] = {
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.gpio = GPIO_PG_EC_ALL_SYS_PWRGD,
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.flags = POWER_SIGNAL_ACTIVE_HIGH,
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.name = "ALL_SYS_PWRGD",
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},
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};
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BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
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__overridable int intel_x86_get_pg_ec_dsw_pwrok(void)
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{
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return gpio_get_level(GPIO_PG_EC_DSW_PWROK);
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}
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__overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void)
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{
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return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD);
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}
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void chipset_force_shutdown(enum chipset_shutdown_reason reason)
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{
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int timeout_ms = 50;
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CPRINTS("%s() %d", __func__, reason);
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report_ap_reset(reason);
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/* Turn off RMSRST_L to meet tPCH12 */
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board_before_rsmrst(0);
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GPIO_SET_LEVEL(GPIO_PCH_RSMRST_L, 0);
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board_after_rsmrst(0);
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/* Turn off DSW_PWROK to meet tPCH14 */
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GPIO_SET_LEVEL(GPIO_PCH_DSW_PWROK, 0);
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/* Turn off DSW load switch. */
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GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 0);
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/*
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* For JSL, we need to wait 60ms before turning off PP5000_U to allow
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* VCCIN_AUX time to discharge.
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*/
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if (IS_ENABLED(CONFIG_CHIPSET_JASPERLAKE))
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msleep(60);
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/* Turn off PP5000 rail */
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if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL))
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power_5v_enable(task_get_current(), 0);
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else
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GPIO_SET_LEVEL(GPIO_EN_PP5000, 0);
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/*
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* TODO(b/111810925): Replace this wait with
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* power_wait_signals_timeout()
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*/
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/* Now wait for DSW_PWROK and RSMRST_ODL to go away. */
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while (intel_x86_get_pg_ec_dsw_pwrok() &&
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gpio_get_level(GPIO_PG_EC_RSMRST_ODL) && (timeout_ms > 0)) {
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msleep(1);
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timeout_ms--;
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};
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if (!timeout_ms)
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CPRINTS("DSW_PWROK or RSMRST_ODL didn't go low! Assuming G3.");
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}
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void chipset_handle_espi_reset_assert(void)
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{
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/*
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* If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
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* it means that there is an unexpected power loss (global reset
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* event). In this case, check if shutdown was being forced by pressing
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* power button. If yes, release power button.
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*/
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if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
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forcing_shutdown) {
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power_button_pch_release();
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forcing_shutdown = 0;
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}
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}
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enum power_state chipset_force_g3(void)
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{
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chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
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return POWER_G3;
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}
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static void enable_pp5000_rail(void)
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{
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if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL))
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power_5v_enable(task_get_current(), 1);
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else
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GPIO_SET_LEVEL(GPIO_EN_PP5000, 1);
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}
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static void dsw_pwrok_pass_thru(void)
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{
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int dswpwrok_in = intel_x86_get_pg_ec_dsw_pwrok();
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/* Pass-through DSW_PWROK to ICL. */
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if (dswpwrok_in != gpio_get_level(GPIO_PCH_DSW_PWROK)) {
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if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
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&& dswpwrok_in) {
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/*
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* Once DSW_PWROK is high, reconfigure SLP_S3_L back to
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* an input after a short delay.
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*/
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msleep(1);
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CPRINTS("Release SLP_S3_L");
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gpio_reset(SLP_S3_SIGNAL_L);
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power_signal_enable_interrupt(SLP_S3_SIGNAL_L);
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}
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CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
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/*
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* A minimum 10 msec delay is required between PP3300_A being
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* stable and the DSW_PWROK signal being passed to the PCH.
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*/
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msleep(10);
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GPIO_SET_LEVEL(GPIO_PCH_DSW_PWROK, dswpwrok_in);
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}
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}
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/*
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* Return 0 if PWROK signal is deasserted, non-zero if asserted
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*/
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static int pwrok_signal_get(const struct intel_x86_pwrok_signal *signal)
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{
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int level = gpio_get_level(signal->gpio);
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if (signal->active_low)
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level = !level;
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return level;
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}
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/*
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* Set the PWROK signal state
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*
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* ¶m level 0 deasserts the signal, other values assert the signal
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*/
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static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal,
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int level)
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{
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GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level);
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}
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/*
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* Pass through the state of the ALL_SYS_PWRGD input to all the PWROK outputs
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* defined by the board.
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*/
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static void all_sys_pwrgd_pass_thru(void)
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{
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int all_sys_pwrgd_in = intel_x86_get_pg_ec_all_sys_pwrgd();
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const struct intel_x86_pwrok_signal *pwrok_signal;
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int signal_count;
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int i;
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if (all_sys_pwrgd_in) {
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pwrok_signal = pwrok_signal_assert_list;
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signal_count = pwrok_signal_assert_count;
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} else {
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pwrok_signal = pwrok_signal_deassert_list;
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signal_count = pwrok_signal_deassert_count;
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}
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/*
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* Loop through all PWROK signals defined by the board and set
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* to match the current ALL_SYS_PWRGD input.
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*/
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for (i = 0; i < signal_count; i++, pwrok_signal++) {
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if ((!all_sys_pwrgd_in && !pwrok_signal_get(pwrok_signal))
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|| (all_sys_pwrgd_in && pwrok_signal_get(pwrok_signal)))
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continue;
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if (pwrok_signal->delay_ms > 0)
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msleep(pwrok_signal->delay_ms);
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pwrok_signal_set(pwrok_signal, all_sys_pwrgd_in);
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}
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}
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enum power_state power_handle_state(enum power_state state)
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{
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#ifdef CONFIG_CHIPSET_JASPERLAKE
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int timeout_ms = 10;
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#endif /* CONFIG_CHIPSET_JASPERLAKE */
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dsw_pwrok_pass_thru();
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all_sys_pwrgd_pass_thru();
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common_intel_x86_handle_rsmrst(state);
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switch (state) {
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case POWER_G3S5:
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if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) {
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/*
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* Prevent glitches on the SLP_S3_L and PCH_PWROK
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* signals while when the PP3300_A rail is turned on.
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* Drive SLP_S3_L from the EC until DSW_PWROK is high.
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*/
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CPRINTS("Drive SLP_S3_L low during PP3300_A rampup");
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power_signal_disable_interrupt(SLP_S3_SIGNAL_L);
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gpio_set_flags(SLP_S3_SIGNAL_L, GPIO_ODR_LOW);
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}
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/* Default behavior - turn on PP5000 rail first */
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if (!IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST))
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enable_pp5000_rail();
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/*
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* TODO(b/111121615): Should modify this to wait until the
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* common power state machine indicates that it's ok to try an
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* boot the AP prior to turning on the 3300_A rail. This could
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* be done using chipset_pre_init_callback()
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*/
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/* Turn on the PP3300_DSW rail. */
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GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 1);
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if (power_wait_signals(IN_PGOOD_ALL_CORE))
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break;
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/* Pass thru DSWPWROK again since we changed it. */
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dsw_pwrok_pass_thru();
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/* Turn on PP5000 after PP3300 and DSW PWROK when enabled */
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if (IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST))
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enable_pp5000_rail();
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/*
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* Now wait for SLP_SUS_L to go high based on tPCH32. If this
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* signal doesn't go high within 250 msec then go back to G3.
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*/
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if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
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IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) {
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CPRINTS("SLP_SUS_L didn't go high! Going back to G3.");
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return POWER_S5G3;
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}
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break;
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case POWER_S5:
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if (forcing_shutdown) {
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power_button_pch_release();
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forcing_shutdown = 0;
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}
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/* If SLP_SUS_L is asserted, we're no longer in S5. */
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if (!power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
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return POWER_S5G3;
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break;
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#ifdef CONFIG_CHIPSET_JASPERLAKE
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case POWER_S3S0:
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GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 1);
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/* Now wait for ALL_SYS_PWRGD. */
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while (!intel_x86_get_pg_ec_all_sys_pwrgd() &&
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(timeout_ms > 0)) {
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msleep(1);
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timeout_ms--;
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};
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if (!timeout_ms)
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CPRINTS("ALL_SYS_PWRGD not received.");
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break;
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case POWER_S0S3:
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GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 0);
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break;
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#endif /* CONFIG_CHIPSET_JASPERLAKE */
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default:
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break;
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}
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return common_intel_x86_power_handle_state(state);
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}
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