140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Cannonlake chipset power control module for Chrome EC */
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#include "chipset.h"
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#include "console.h"
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#include "gpio.h"
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#include "power.h"
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#include "power/cannonlake.h"
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#include "power/intel_x86.h"
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#include "power_button.h"
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#include "task.h"
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#include "timer.h"
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/* Console output macros */
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#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
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static int forcing_shutdown; /* Forced shutdown in progress? */
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void chipset_force_shutdown(enum chipset_shutdown_reason reason)
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{
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CPRINTS("%s(%d)", __func__, reason);
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/*
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* Force off. Sending a reset command to the PMIC will power off
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* the EC, so simulate a long power button press instead. This
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* condition will reset once the state machine transitions to G3.
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* Consider reducing the latency here by changing the power off
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* hold time on the PMIC.
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*/
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if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
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report_ap_reset(reason);
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forcing_shutdown = 1;
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power_button_pch_press();
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}
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}
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void chipset_handle_espi_reset_assert(void)
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{
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/*
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* If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
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* it means that there is an unexpected power loss (global reset
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* event). In this case, check if shutdown was being forced by pressing
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* power button. If yes, release power button.
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*/
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if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
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forcing_shutdown) {
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power_button_pch_release();
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forcing_shutdown = 0;
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}
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}
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enum power_state chipset_force_g3(void)
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{
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int timeout = 50;
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chipset_force_shutdown(CHIPSET_SHUTDOWN_G3);
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/* Turn off DSW load switch. */
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gpio_set_level(GPIO_EN_PP3300_DSW, 0);
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/* Now wait for DSW_PWROK to go away. */
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while (gpio_get_level(GPIO_PMIC_DPWROK) && (timeout > 0)) {
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msleep(1);
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timeout--;
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};
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if (!timeout)
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CPRINTS("DSW_PWROK didn't go low! Assuming G3.");
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return POWER_G3;
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}
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enum power_state power_handle_state(enum power_state state)
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{
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enum power_state new_state;
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int dswpwrok_in = gpio_get_level(GPIO_PMIC_DPWROK);
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static int dswpwrok_out = -1;
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/* Pass-through DSW_PWROK to CNL. */
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if (dswpwrok_in != dswpwrok_out) {
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CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
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gpio_set_level(GPIO_PCH_DSW_PWROK, dswpwrok_in);
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dswpwrok_out = dswpwrok_in;
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}
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common_intel_x86_handle_rsmrst(state);
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if (state == POWER_S5 && forcing_shutdown) {
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power_button_pch_release();
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forcing_shutdown = 0;
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}
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switch (state) {
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case POWER_G3:
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/* If SLP_SUS_L is deasserted, we're no longer in G3. */
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if (power_has_signals(IN_PCH_SLP_SUS_DEASSERTED))
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return POWER_S5;
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break;
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case POWER_G3S5:
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/* Turn on the PP3300_DSW rail. */
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gpio_set_level(GPIO_EN_PP3300_DSW, 1);
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if (power_wait_signals(IN_PGOOD_ALL_CORE))
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break;
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/* Pass thru DSWPWROK again since we changed it. */
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dswpwrok_in = gpio_get_level(GPIO_PMIC_DPWROK);
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gpio_set_level(GPIO_PCH_DSW_PWROK, dswpwrok_in);
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CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
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dswpwrok_out = dswpwrok_in;
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/* Enable the 5V rail. */
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#ifdef CONFIG_POWER_PP5000_CONTROL
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power_5v_enable(task_get_current(), 1);
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#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
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gpio_set_level(GPIO_EN_PP5000, 1);
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#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
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break;
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case POWER_S5G3:
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/* Turn off the 5V rail. */
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#ifdef CONFIG_POWER_PP5000_CONTROL
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power_5v_enable(task_get_current(), 0);
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#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */
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gpio_set_level(GPIO_EN_PP5000, 0);
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#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
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break;
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default:
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break;
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};
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new_state = common_intel_x86_power_handle_state(state);
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return new_state;
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}
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