There is an option in the task_set_event function which force
the calling task to wait for an event. However, the option is never
used thus remove it.
This also will help in the Zephyr migration process.
BUG=b:172360521
BRANCH=none
TEST=make buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
This CL adds routines required to support USB-PD messaging to the UCPD
driver. UCPD is performs TCPC type functions, but is not a TCPC. UCPD
does utilize the common TCPCI APIs as entry points called from the
port's PD task. In addition, UCPD has its own task to manage more
easily transmit requests from TCPM layer and GoodCRC messages which
must be intiated in the UCPD driver itself.
BUG=b:167601672
BRANCH=None
TEST=verfied type-c attaches properly on quiche
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I0c02bee4badc479125832a6b5a6fa156e998c201
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2247117
Tested-by: Scott Collyer <scollyer@chromium.org>
Auto-Submit: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Exposes PMU-related functions so that we can call the functions to study
some part of cache performance.
BRANCH=none
BUG=b:172988651
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I27182e3d2af52d8761f45359f3627d70c5acf28c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567517
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Waking from PSL hibernate is power-on for EC but not for H1, so
we should not add the 2 second delay for CONFIG_BOARD_RESET_AFTER_POWER_ON
in this case.
BUG=b:173180800
BRANCH=zork
TEST=no 2 second delay on wake from hibernate
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: Ib0c8f2ca7f197626b20a11e21ace44a5046db18b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2576439
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
As most of the peripherals were not implemented to support switching to
16-MHz HSI (e.g. high speed serial port requires a clock input > 24
Mhz), implement a simpler clock scheme than the dynamic between HSI and
PLL used other platforms:
- the PLL is disabled only when entering the low-power idle and the PLL
locking time is added to wake-up time.
- when the host is running (not suspended) we stay in a high power mode
(~20mW).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, on bloonchipper, check we can still capture fingerprint.
read the MCU power consumption: pp3300_dx_mcu_mw is 2.367 mW.
BRANCH=fpmcu-bloonchipper
Change-Id: Ic1fe015b2501bdea9779a2f63fab296f8812c315
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2555162
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Implement a low power idle mode using the STM32F4 STOP mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, on bloonchipper, check we can still capture fingerprint.
read the MCU power consumption.
BRANCH=fpmcu-bloonchipper
Change-Id: I11249e9b68c989033263e34e1cde3f19ffe7c54c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537631
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
On STM32F4, when converting micro-seconds to the RTC sub-second counter
value, the current computation in the us_to_rtcss() routine has a large
rounding error which can even led to generate a negative value.
When such a negative value is output and then programmed in the
(unsigned) RTC_ALRMASSR register used to set the alarm precise
sub-second timestamp, it might put a wrong value in the past.
As a consequence when the RTC alarm is used a wake-up mechanism for the
low power idle, it might never fired and trigger a watchdog reboot.
An example of bad values on a STM32F412 with the RTC driven by the
32-kHz LSI:
- RTC_PREDIV_A = 1
- RTC_FREQ = (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1) = 16000 /* Hz */
- RTC_PREDIV_S = (RTC_FREQ - 1) = 15999
- US_PER_RTC_TICK = 1000000 / RTC_FREQ = 62 /* rounded from 62.5 */
When converting 996000 us,
us_to_rtcss(996000) = RTC_PREDIV_S - (us / US_PER_RTC_TICK)
= 15999 - (996000 / 62)
= -65
returned as a uint32_t as 0xfffffffb.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, with the STOP mode enabled, we no longer see watchdog
reboot due to the RTC alarm being set in the past and never firing.
TEST=manual, verify that the output of the 'gettime' console command is not
drifting compared to the wall clock when the low power idle using the
RTC time is used.
BRANCH=fpmcu-bloonchipper
Change-Id: I53869539828bed9a5900d29407b5feba140b8217
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563684
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Allow to transition between the PLL to run at full speed
and the bare HSI (internal RC oscillator at 16Mhz) to save power.
On HSI, as our sysclk frequency is low, we run all peripheral clocks
undivided at the same frequency.
Keep the configuration for other platforms running from the HSE
(external crystal)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, verify the timers are working by checking the output of the
'gettime' console command against the wall clock.
TEST=manual, verify the UART console works as expected.
TEST=measure MCU power on bloonchipper in various modes through the INA:
PLL 19.20 mW HSI 4.73 mW STOP 2.10 mW
BRANCH=fpmcu-bloonchipper
Change-Id: I1185e04c9a7819fec05dd643b7026116b146f3b8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527049
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Add support for changing for the timer source clock frequency on
STM32F4 by re-computing the timer pre-scaler value in the
HOOK_FREQ_CHANGE callback.
Preparatory work to implement power management switching between PLL and
HSI as sysclk.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, verify the output of the 'gettime' console command against
the wall clock.
BRANCH=fpmcu-bloonchipper
Change-Id: Ia7dc24d3b1dbff816b1cebbc87492e678b987dfd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527048
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This CL implements a feature report defined in [1] that describes the
keyboard's top row layout.
[1] http://doc/1NTxSGv3WA2Vn4dlPLOcvKBvPytWOF0UAcIYQaFctTug
BUG=b:171156337
TEST=Verify feature report content using test code in CL:2530156.
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I28a93f1b926d58602eb66d1b090e89384cb09f77
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2522641
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
This CL increased clock's Tlow to 1.51 us (1.3 us minimum) and
reduced Thigh to 1.087 us (0.6 us minimum).
BUG=b:163384683
BRANCH=none
TEST=i2c clock meet timing at 400kHz.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Id62b2370018ba2d41e0dbc715a4c40629260d66b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557281
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Mike Goodey <mgoodey@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Moves __RAM_CODE_SECTION_NAME from registers.h to config_chip.h. Or
switch.S cannot see the macro.
BRANCH=none
BUG=none
TEST=1. make BOARD=asurada
2. grep __switch_task build/asurada/RW/ec.RW.smap
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I1ef272c2e2181a88e4f53dc3024330a1a26c0688
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2549342
Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
This sets a default value of 0 for NPCX_UART_MODULE2 and
NPCX9_PWM1_SEL so that board files don't need to set these.
BRANCH=none
BUG=b:173575131
TEST=buildall
Change-Id: Ief84ed558bb5431f13fb01b963db3bd97fc8d659
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546639
Reviewed-by: CH Lin <chlin56@nuvoton.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit "it83xx: pull more functions into __ram_code section"
(https://crrev.com/c/2535899) breaks Asurada SCP. It moves
some essential code to .ram_code section but only IT8XXX2
family includes .ram_code in linker script.
Moves the context switch code to ram_code only if it supports.
BRANCH=none
BUG=none
TEST=make BOARD=asurada_scp && make BOARD=asurada
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I8602f7ef0103282feeddbfe1757f7cf7fb5512dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546722
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Because we have space in the section, so we pulled more functions
into the section. If a function is cached in __ram_code section
(static cache), we can save latency of fetching code of the function
from flash. (Fetching 64 bytes code from flash takes about 4us latency)
BUG=none
BRANCH=none
TEST=buildall.
Asurada and Drawcia are both able to boot to kernel.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I8b413bd577c4e5b73a5c67018d17955da1ed0c55
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2535899
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This CL extends CONFIG_I2C_XFER_LARGE_READ to also support large
(greater than 255 bytes) write.
Related config name is also updated to reflect the behavior change,
BUG=b:169651794
TEST=flash fw successfully on Zed.
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Icb889013da01f48708cd0227207561b8186bac63
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537412
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
This CL fixes an issue with a rebase merge, UCPD_IFRGAP_HBIT_CNT had
been changed to UCPD_IFRGAP_CNT in a previous CL. This CL removes
HBIT.
BUG=b:167601672
BRANCH=None
TEST=make BOARD=quiche
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ideff65872d744bc7e3b3cdfa8c5af37f4725be36
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2522649
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
This CL implements vivald function row config for hammer keyboard.
If CONFIG_USB_HID_KEYBOARD_VIVALDI defined, STM32 HID keyboard now returns
an extra 32-bit data represents the status of action keys. Additionally,
if board_vivaldi_keybd_config returns a non-null pointer, driver will
convert function keys to action key according to the given config.
BUG=b:171156337
TEST=verify keycode is correct in `evtest`
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Ide3289fd2c1bb8859a74e97134e6113441cfb967
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508848
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
This change accomplishes 2 things:
1. It refactors the zephyr/shim directory to structure around
chip specific compilation. In this example, we're focusing
on npcx7m6fb which is used in volteer but others can be
added easily.
2. It shims the common/i2c_master.c by providing an alternate
implementation of i2c_xfer_unlocked that calls down to the
Zephyr API i2c_write_read instead of the chip specific
i2c_xfer_no_retry or chip_i2c_xfer_with_notify.
The shim layer is made possible by the addition of
zephyr/shim/include/i2c/i2c.h which adds a functions that
needs to be implemented per chip (npcx7 family in this case)
and allows us to map the current port int which is defined
in chip/${CHIP}/registers.h (chip/npcx/registers-npcx7.h in
our case). This function (i2c_get_device_for_port) maps the
platform/ec port int to a const struct device * which is
needed in the Zephyr I2C APIs.
BRANCH=none
BUG=b:171302975
TEST=clean_build.sh projects/experimental/volteer/ and make BOARD=eve
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I210f4758337bf384d0d6f103eef8b89126887d11
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2504285
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Simon Glass <sjg@chromium.org>
Rename local i2c variables and related comments to the new
controller/peripheral naming scheme.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ibb6a2bdfe47824be6412d999e6c4eb0303e6b421
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518658
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
The new I2C_STRIP_FLAGS macro was added to avoid conflict with
Zephyr's macro. This CL performs the migration to that new API.
BRANCH=none
BUG=b:172067439
TEST=make runtests -j and built for various boards: eve, volteer,
arcada_ish, atlas, hatch, kohaku, nocturne, samus, and scarlet
Change-Id: I0583b647435db96ec268f186252b367bdc4118a6
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511097
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Rename atomic_read_clear to atomic_clear to be consistent with the rest
of the atomic functions, which return the previous value of the
variable.
BUG=b:169151160
BRANCH=none
TEST=buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: I2588971bd7687879a28ec637cf5f6c3d27d393f4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505143
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Make the unused pins as GPIO and disable any alt-function.
BRANCH=None
BUG=b:169595541
TEST=make buildall -j
Change-Id: I6b7c16dd68654b38c8a12654207438315fe86c2c
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508862
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
The FPSENSOR task only runs in RW, not RO, so
IS_ENABLED(HAS_TASK_FPSENSOR) is false in RO. As a result, we were
returning the wrong protocol information for bloonchipper boards with
UART when running in RO.
BRANCH=none
BUG=b:171370392
TEST=none
TEST=Using dragonclaw v0.2 and servo_micro:
./test/run_device_tests.py -t fpsensor_uart_ro
./test/run_device_tests.py -t fpsensor_uart_rw
./test/run_device_tests.py -t fpsensor_spi_ro
./test/run_device_tests.py -t fpsensor_spi_rw
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Iccf801ef453a5dc6d8a21df11af41c60818781b5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508861
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Yicheng Li <yichengli@chromium.org>
In task_wait_event_mask(), if task woke up by an event which isn't
what we want (events |= __wait_evt(time_remaining_us, TASK_ID_IDLE)),
and timeout occurs (time_remaining_us = deadline - get_time().val).
EC will post timeout event to task even if the event we want
((eg.TASK_EVENT_ADC_DONE)) has been set.
We fix this symptom with checking data valid bit of ADC's register.
So we won't miss ADC read.
BUG=b:171731189
BRANCH=none
TEST=No ADC read error on RunInStressCountdown
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I56b301a0f58b64833ae17e2b6e789c879e48cc5c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2501091
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Rx valid length interrupt has been set as default, so the
configuration of IT83XX_SPI_RX_VALID_INT can be removed.
BUG=none
BRANCH=none
TEST=Boot to kernel on HAYATO and no error on
the transaction of host command with EC.
Change-Id: I92ab78b3e821f566053c816f51bf609394f3b199
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2497366
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
This CL applies A version's configurations to B version.
They have the same HW except for new added function
(eg. SPI emulate eMMC "Alternative Boot Mode") on B version.
We can add new chip config option for B version in other CL
if needed.
BUG=none
BRANCH=none
TEST=Building asurada's EC image with selecting BX chip variant.
Flashing the image into reworked asurada (change EC to IT81202BX)
and boot to kernel.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I796a622df21842998ad8f808bfa189b924710649
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2501802
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
It is done as a part of porting to Zephyr.
Since the implementation of atomic functions is done for all architectures
use atomic_* instead of deprecated_atomic_*.
Sometimes there was a compilation error "discards 'volatile' qualifier"
due to dropping "volatile" in the argument of the functions, thus
some pointers casts need to be made. It shouldn't cause any issues,
because we are sure about generated asm (store operation will be
performed).
BUG=b:169151160
BRANCH=none
TEST=buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: I98f590c323c3af52035e62825e8acfa358e0805a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2478949
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
According to Power Consumption Investigation Guide, by Nuvoton, setting
the disconnected/unused pins as input with an internal pull-up gets
better power number. Do it automically for all GPIOs defined through
the UNUSED() macro.
BRANCH=None
BUG=b:169595541
TEST=make buildall -j
Change-Id: I929c139e73d8253c79e0b9a3445217a300dc98cb
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2488214
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Our HW design is that Vcc on->off transition will disable port80.
Once we reset espi module, then Vcc has on -> off transition and
this cause port80 disabled. I re-enable port80 after espi reset.
BUG=b:163100497
BRANCH=none
TEST=On drawcia, check port80 values and SPCTRL1 register (= 0xc2)
after "reboot" and "power on" reset
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I2c6b0542cf08bee324e38886d1ce5909cd0b3776
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2479442
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
This change makes EC handle get status command from AP while erasing.
BUG=b:168869304
BRANCH=none
TEST=Software sync works on Asurada.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I261ce1a82c89b4f8917e8156aa142e2ea327c368
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2465605
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Support keyboard_raw_is_input_low() for enable CONFIG_KEYBOARD_FACTORY_TEST.
BUG=b:170699805
BRANCH=none
TEST=The function works as expected.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I30ff914bdaf3fe47949227fa0a5cee327408913e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2463037
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
These pins could be used as GPIO input, and they can
be configured as GPIO output as well. So we made this
patch to support it.
BRANCH=none
BUG=b:170699805
TEST=On board it8xxx2_evb
1.GPIO only: set/get level properly at GPIO mode.
2.GPIO and alternate mix: KSI input low and KSO GPIO level
not change
On board reef_it8320
1.keyboard scan function still work fine.
Change-Id: I2098812649f2e3ee9a8718d0d75e541ce3f14338
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182128
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
There is the hardware accelerator for SHA computation inside npcx9. This
CL wraps the Nuvoton SHA library APIs (which are in the ROM) to Chromium
EC's SHA256_* APIs to speed up the SHA256 computation.
With the help of the hardware accelerator, the hash computation runs
several times faster than the software method (see b:155771688 for more
detailed evaluation data.) Also, we can gain ~840 bytes of code size.
BRANCH=none
BUG=b:165777478
BUG=b:155771688
TEST=pass "make buildall"
TEST=flash the same RW image; #define/#undef CONFIG_SHA256_HW_ACCELERATE
; verify the RW hash value is the same in the console message.
TEST=with the following test CL, move test patterns in test/sha256.c
to board/npcx9_evb/test_sha256.c; pass all test patterns.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I45ca609889bd73573d67d15f3e561614201e60f6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2455021
Tested-by: CH Lin <chlin56@nuvoton.com>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
If requested erase size is too large at one time on KGD flash,
we need to reload watchdog to prevent the reset.
BUG=b:168869304
BRANCH=none
TEST=ectool flasherase 0x80000 0x80000
Change-Id: I9a34b8132e17e4ee0a90874d6341ac1e4a3b60c1
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2438072
Reviewed-by: Jett Rink <jettrink@chromium.org>
Mutexes shouldn't be used in interrupt context. An ASSERT was added in
mutex_lock to verify this commit
e695620911.
There are cases where bkpdata_write can be called from an interrupt
context, such as this stack trace that occurs when adding entropy from
RO on dartmonkey/icetower (stack captured with Segger J-Trace):
> rollbackaddent 1234
panic_assert_fail panic_output.c:132
mutex_lock task.c:889
bkpdata_write bkpdata.c:35
bkpdata_write bkpdata.c:24
bkpdata_write_reset_flags bkpdata.c:86
chip_save_reset_flags system.c:366
system_reset system.c:366
panic_reboot panic_output.c:114
report_panic panic.c:339
exception_panic panic.c:350
Validation of the fix was checked with the "rollback_region1" unit test,
which failed before the change and works after.
BRANCH=none
BUG=b:170147314
TEST=./test/run_device_tests.py -b dartmonkey -t rollback_region1
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ie5509ec024e94b48c786199ccbb81ce93fafe547
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2462545
Reviewed-by: Edward Hill <ecgh@chromium.org>
Dawid Niedzwiecki