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Merge remote-tracking branch cros/main into firmware-nissa-15217.B-main 

Generated by: util/update_release_branch.py -r --zephyr --board nissa firmware-
nissa-15217.B-main

Relevant changes:

git log --oneline a94143bef3..716b18de2f -- zephyr/program/nissa
util/getversion.sh

83d98fe832 anraggar: limit sensor odr at 125Hz
fe6615dac0 anraggar:  Swap I2C A and C
1019744907 anraggar: Change lid sensor from forced mode to interrupt mode

BUG=b:333834135 b:333285756 b:333285756 b:333834135
TEST=`make -j buildall`

Force-Relevant-Builds: all
Change-Id: Ia3d473c68b640882ce647f419c8a0d5dd9048adc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/5457039
Commit-Queue: Ivan Chen <yulunchen@google.com>
Auto-Submit: Shou-Chieh Hsu <shouchieh@chromium.org>
Tested-by: Shou-Chieh Hsu <shouchieh@chromium.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
This commit is contained in:
Shou-Chieh Hsu 2024-04-16 09:59:46 +00:00 committed by Chromeos LUCI
parent a94143bef3 716b18de2f
commit ec6e311c9a
29 changed files with 685 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitlab-ci.yml
View File

@ -40,6 +40,7 @@ before_script:
- export MODULES_DIR="$CI_PROJECT_DIR/modules"
- export ZEPHYR_BASE="${CI_PROJECT_DIR}/zephyr/main"
- export REPO_BASE="${CI_PROJECT_DIR}/repo"
- export DEPOT_TOOLS_UPDATE=0
- git config --global --add safe.directory '*'
# Get Zephyr repo and modules
- checkout_at_date() {

15
power/mt8186.c
View File

@ -228,6 +228,7 @@ static void mt8186_exit_off(void)
is_exiting_off = true;
chipset_exit_hard_off();
}
DECLARE_DEFERRED(mt8186_exit_off);
static void reset_flag_deferred(void)
{
@ -353,9 +354,16 @@ enum power_state power_chipset_init(void)
*/
battery_wait_for_stable();
if (exit_hard_off && init_state == POWER_G3)
if (exit_hard_off && init_state == POWER_G3) {
/* Auto-power on */
#if CONFIG_PLATFORM_EC_PP3700_DISCHARGE_TIME_MS
hook_call_deferred(&mt8186_exit_off_data,
CONFIG_PLATFORM_EC_PP3700_DISCHARGE_TIME_MS *
MSEC);
#else
mt8186_exit_off();
#endif
}
if (init_state != POWER_G3 && !exit_hard_off) {
/* Force shutdown from S5 if the PMIC is already up. */
@ -535,8 +543,11 @@ enum power_state power_handle_state(enum power_state state)
PMIC_AP_RESET_TIMEOUT))
CPRINTS("PMIC reset AP timeout. Forcing PMIC off");
gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(en_pp4200_s5), 0);
#ifdef CONFIG_PLATFORM_EC_PP3700_DISCHARGE_TIME_MS
crec_msleep(CONFIG_PLATFORM_EC_PP3700_DISCHARGE_TIME_MS);
#endif /* CONFIG_PLATFORM_EC_PP3700_DISCHARGE_TIME_MS */
power_signal_disable_interrupt(GPIO_PMIC_EC_RESETB);
#endif
#endif /* DT_NODE_EXISTS(DT_NODELABEL(en_pp4200_s5)) */
return POWER_G3;
default:
CPRINTS("Unexpected power state %d", state);

70
test/fpsensor_crypto.cc
View File

@ -831,10 +831,80 @@ test_static ec_error_list test_aes_128_gcm_decrypt_in_place()
return EC_SUCCESS;
}
test_static ec_error_list test_aes_128_gcm_encrypt_invalid_nonce_size()
{
constexpr std::array<uint8_t, SBP_ENC_KEY_LEN> key{};
std::array<uint8_t, 16> text{};
std::array<uint8_t, FP_CONTEXT_TAG_BYTES> tag{};
/* Use an invalid nonce size. */
constexpr std::array<uint8_t, FP_CONTEXT_NONCE_BYTES - 1> nonce{};
ec_error_list ret = aes_128_gcm_encrypt(
key.data(), key.size(), text.data(), text.data(), text.size(),
nonce.data(), nonce.size(), tag.data(), tag.size());
TEST_EQ(ret, EC_ERROR_INVAL, "%d");
return EC_SUCCESS;
}
test_static ec_error_list test_aes_128_gcm_decrypt_invalid_nonce_size()
{
constexpr std::array<uint8_t, SBP_ENC_KEY_LEN> key{};
std::array<uint8_t, 16> text{};
constexpr std::array<uint8_t, FP_CONTEXT_TAG_BYTES> tag{};
/* Use an invalid nonce size. */
constexpr std::array<uint8_t, FP_CONTEXT_NONCE_BYTES - 1> nonce{};
ec_error_list ret = aes_128_gcm_decrypt(
key.data(), key.size(), text.data(), text.data(), text.size(),
nonce.data(), nonce.size(), tag.data(), tag.size());
TEST_EQ(ret, EC_ERROR_INVAL, "%d");
return EC_SUCCESS;
}
test_static ec_error_list test_aes_128_gcm_encrypt_invalid_key_size()
{
std::array<uint8_t, 16> text{};
std::array<uint8_t, FP_CONTEXT_TAG_BYTES> tag{};
constexpr std::array<uint8_t, FP_CONTEXT_NONCE_BYTES> nonce{};
/* Use an invalid key size. Key must be exactly 128 bits. */
constexpr std::array<uint8_t, SBP_ENC_KEY_LEN - 1> key{};
ec_error_list ret = aes_128_gcm_encrypt(
key.data(), key.size(), text.data(), text.data(), text.size(),
nonce.data(), nonce.size(), tag.data(), tag.size());
TEST_EQ(ret, EC_ERROR_UNKNOWN, "%d");
return EC_SUCCESS;
}
test_static ec_error_list test_aes_128_gcm_decrypt_invalid_key_size()
{
std::array<uint8_t, 16> text{};
constexpr std::array<uint8_t, FP_CONTEXT_TAG_BYTES> tag{};
constexpr std::array<uint8_t, FP_CONTEXT_NONCE_BYTES> nonce{};
/* Use an invalid key size. Key must be exactly 128 bits. */
constexpr std::array<uint8_t, SBP_ENC_KEY_LEN - 1> key{};
ec_error_list ret = aes_128_gcm_decrypt(
key.data(), key.size(), text.data(), text.data(), text.size(),
nonce.data(), nonce.size(), tag.data(), tag.size());
TEST_EQ(ret, EC_ERROR_UNKNOWN, "%d");
return EC_SUCCESS;
}
void run_test(int argc, const char **argv)
{
RUN_TEST(test_aes_128_gcm_encrypt_in_place);
RUN_TEST(test_aes_128_gcm_decrypt_in_place);
RUN_TEST(test_aes_128_gcm_encrypt_invalid_nonce_size);
RUN_TEST(test_aes_128_gcm_decrypt_invalid_nonce_size);
RUN_TEST(test_aes_128_gcm_encrypt_invalid_key_size);
RUN_TEST(test_aes_128_gcm_decrypt_invalid_key_size);
RUN_TEST(test_hkdf_expand);
RUN_TEST(test_derive_encryption_key_failure_seed_not_set);
RUN_TEST(test_derive_positive_match_secret_fail_seed_not_set);

22
test/run_device_tests.py
View File

@ -1102,17 +1102,6 @@ def flash_and_run_test(
)
return False
if test.toggle_power:
power_cycle(board_config)
else:
# In some cases flash_ec leaves the board off, so just ensure it is on
power(board_config, power_on=True)
hw_write_protect(test.enable_hw_write_protect)
# run the test
logging.info('Running test: "%s"', test.config_name)
with ExitStack() as stack:
if args.remote and args.console_port:
console_socket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
@ -1125,6 +1114,17 @@ def flash_and_run_test(
console_file = open(get_console(board_config), "wb+", buffering=0)
console = stack.enter_context(console_file)
if test.toggle_power:
power_cycle(board_config)
else:
# In some cases flash_ec leaves the board off, so just ensure it is on
power(board_config, power_on=True)
hw_write_protect(test.enable_hw_write_protect)
# run the test
logging.info('Running test: "%s"', test.config_name)
return run_test(
test,
board_config,

29
util/flash_fp_mcu
View File

@ -420,8 +420,7 @@ flash_fp_mcu_npcx() {
cmd_flash_monitor+=" --opr=wr --addr=0x200c3020"
#TODO(b/294944527): Make sure this file is available in image
cmd_flash_monitor+=" \
--file /usr/local/usr/share/ec-devutils/npcx9/npcx_monitor.bin"
cmd_flash_monitor+=" --file /opt/google/biod/fw/npcx_monitor.bin"
# Reset sequence to enter bootloader mode
gpio 0 "${gpio_nrst}"
@ -1041,16 +1040,26 @@ config_guybrush() {
config_skyrim() {
readonly TRANSPORT="UART"
readonly DEVICE="/dev/ttyS1"
readonly GPIO_CHIP="gpiochip768"
# FPMCU RST_ODL is on AGPIO 12 = 768 + 12 = 780
readonly GPIO_NRST=780
# FPMCU BOOT0 is on AGPIO 130 = 768 + 130 = 898
readonly GPIO_BOOT0=898
# FPMCU PWR_EN is on AGPIO 4 = 768 + 4 = 772
readonly GPIO_PWREN=772
local gpiochip_dev_path="platform/AMD0030:00/gpio"
local gpiobase
if ! gpiobase=$(get_sysfs_gpiochip_base "${gpiochip_dev_path}"); then
echo "Unable to find gpio chip base"
return "${EXIT_PRECONDITION}"
fi
readonly GPIO_CHIP="gpiochip${gpiobase}"
# FPMCU RST_ODL is on AGPIO 12
local gpionrst=12
readonly GPIO_NRST=$(( gpionrst + gpiobase ))
# FPMCU BOOT0 is on AGPIO 130
local gpioboot=130
readonly GPIO_BOOT0=$(( gpioboot + gpiobase ))
# FPMCU PWR_EN is on AGPIO 4
local gpiopwren=4
readonly GPIO_PWREN=$(( gpiopwren + gpiobase ))
}
config_myst() {

1
util/renode/bloonchipper-druid.resc Symbolic link
View File

@ -0,0 +1 @@
bloonchipper.resc

1
util/renode/buccaneer.resc Symbolic link
View File

@ -0,0 +1 @@
helipilot.resc

3
util/renode_ec_launch.py
View File

@ -75,6 +75,9 @@ def launch(opts: argparse.Namespace) -> int:
os.chdir(ec_dir)
renode_execute: List[str] = []
# We set the machine name to the exact board name, since we might be
# using a derivative board, like buccaneer which is based on helipilot.
renode_execute.append(f'$name="{board}";')
renode_execute.append(f'$bin="{bin_file}";')
renode_execute.append(f'$elf_ro="{elf_ro_file}";')
renode_execute.append(f'$elf_rw="{elf_rw_file}";')

13
zephyr/Kconfig.powerseq
View File

@ -226,6 +226,19 @@ config PLATFORM_EC_POWERSEQ_MT8188
Use the MT8188 code for power sequencing. Re-use MT8186 common
code.
if PLATFORM_EC_POWERSEQ_MT8188
config PLATFORM_EC_PP3700_DISCHARGE_TIME_MS
int "Time(in millisecond) required for power-cycling PP3700_S5"
default 0
help
Timeout value (in milliseconds) for EC to wait for PP3700_S5 to
fully discharge.
This implies that whenever AP shutdown, AP has to stay in the
shutdown state for at least PP3700_DISCHARGE_TIME_MS.
endif # PLATFORM_EC_POWERSEQ_MT8188
config PLATFORM_EC_POWERSEQ_SC7180
bool "SC7180 power sequencing"
depends on AP_ARM_QUALCOMM_SC7180

2
zephyr/program/brox/BUILD.py
View File

@ -80,8 +80,6 @@ greenbayupoc = register_brox_project(
here / "program.conf",
# Parent project's config
here / "greenbayupoc" / "project.conf",
# Common sensor configs
here / "motionsense.conf",
],
)

204
zephyr/program/brox/greenbayupoc/generated.dtsi Normal file
View File

@ -0,0 +1,204 @@
/* Copyright 2024 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* This file is auto-generated - do not edit!
*/
/ {
named-adc-channels {
compatible = "named-adc-channels";
adc_charger_amon: charger_amon {
enum-name = "ADC_AMON_BMON";
io-channels = <&adc0 1>;
};
adc_temp_sensor_1: temp_sensor_1 {
enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
io-channels = <&adc0 4>;
};
adc_temp_sensor_2: temp_sensor_2 {
enum-name = "ADC_TEMP_SENSOR_FAN";
io-channels = <&adc0 5>;
};
};
named-gpios {
compatible = "named-gpios";
gpio_acok_ec_od: acok_ec_od {
gpios = <&gpiob 0 GPIO_INPUT>;
};
gpio_all_sys_pg: all_sys_pg {
gpios = <&gpiob 3 GPIO_INPUT>;
};
gpio_amp_mute_l: amp_mute_l {
gpios = <&gpioj 6 GPIO_OUTPUT>;
};
gpio_bat_disconnect_ec_odl: bat_disconnect_ec_odl {
gpios = <&gpioc 0 GPIO_ODR_LOW>;
};
gpio_ccd_mode_odl: ccd_mode_odl {
gpios = <&gpioe 6 GPIO_ODR_LOW>;
};
gpio_ec_gpj7: ec_gpj7 {
gpios = <&gpioj 7 GPIO_INPUT>;
};
gpio_ec_gpj0: ec_gpj0 {
gpios = <&gpioj 0 GPIO_INPUT>;
};
gpio_ec_batt_pres_odl: ec_batt_pres_odl {
gpios = <&gpioi 7 GPIO_INPUT>;
enum-name = "GPIO_BATT_PRES_ODL";
};
gpio_ec_dsw_pwrok: ec_dsw_pwrok {
gpios = <&gpiod 3 GPIO_OUTPUT>;
};
gpio_ec_en_edp_bl: ec_en_edp_bl {
gpios = <&gpioh 0 GPIO_OUTPUT>;
enum-name = "GPIO_ENABLE_BACKLIGHT";
};
gpio_ec_en_pp3300_wlan: ec_en_pp3300_wlan {
gpios = <&gpioi 3 GPIO_OUTPUT>;
};
gpio_ec_gpg2: ec_gpg2 {
gpios = <&gpiog 2 GPIO_INPUT>;
};
gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
gpios = <&gpioe 3 GPIO_OUTPUT>;
enum-name = "GPIO_PACKET_MODE_EN";
};
gpio_ec_i2c_pmc_pd_int_odl: ec_i2c_pmc_pd_int_odl {
gpios = <&gpioj 1 GPIO_INPUT>;
};
gpio_ec_pch_pwrok: ec_pch_pwrok {
gpios = <&gpiob 5 GPIO_OUTPUT>;
};
gpio_ec_pch_pwr_btn_odl: ec_pch_pwr_btn_odl {
gpios = <&gpiob 2 GPIO_ODR_LOW>;
enum-name = "GPIO_PCH_PWRBTN_L";
};
gpio_ec_pch_sys_pwrok: ec_pch_sys_pwrok {
gpios = <&gpiod 5 GPIO_OUTPUT>;
};
gpio_ec_prochot_odl: ec_prochot_odl {
gpios = <&gpioi 0 GPIO_ODR_LOW>;
};
gpio_ec_rsmrst_l: ec_rsmrst_l {
gpios = <&gpioi 6 GPIO_OUTPUT>;
};
gpio_ec_slp_s3_l: ec_slp_s3_l {
gpios = <&gpioc 6 GPIO_INPUT>;
};
gpio_ec_slp_s4_l: ec_slp_s4_l {
gpios = <&gpioc 4 GPIO_INPUT>;
};
gpio_ec_slp_sus_l: ec_slp_sus_l {
gpios = <&gpioe 5 GPIO_INPUT>;
};
gpio_ec_gpd4: ec_gpd4 {
gpios = <&gpiod 4 GPIO_INPUT>;
};
gpio_ec_gpd7: ec_gpd7 {
gpios = <&gpiod 7 GPIO_INPUT>;
};
gpio_ec_wp_odl: ec_wp_odl {
gpios = <&gpioj 3 GPIO_INPUT>;
};
gpio_en_pp5000_usba: en_pp5000_usba {
gpios = <&gpiof 4 GPIO_OUTPUT>;
};
gpio_en_s5_rails: en_s5_rails {
gpios = <&gpiof 2 GPIO_OUTPUT>;
};
gpio_en_slp_z: en_slp_z {
gpios = <&gpioa 0 GPIO_OUTPUT>;
};
gpio_en_z1_rails_r: en_z1_rails_r {
gpios = <&gpiob 4 GPIO_OUTPUT>;
};
gpio_gsc_ec_flash_sel: gsc_ec_flash_sel {
gpios = <&gpiog 6 GPIO_INPUT>;
};
gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
gpios = <&gpioe 4 GPIO_INPUT>;
enum-name = "GPIO_POWER_BUTTON_L";
};
gpio_imvp9_vrrdy_od: imvp9_vrrdy_od {
gpios = <&gpioh 3 GPIO_INPUT>;
};
gpio_ish_i2c_ec_scl: ish_i2c_ec_scl {
gpios = <&gpioc 7 GPIO_INPUT>;
};
gpio_ish_i2c_ec_sda: ish_i2c_ec_sda {
gpios = <&gpiof 7 GPIO_INPUT>;
};
gpio_lid_open: lid_open {
gpios = <&gpiob 1 GPIO_INPUT>;
enum-name = "GPIO_LID_OPEN";
};
gpio_sen_mode1_ec_pch_wake_odl: sen_mode1_ec_pch_wake_odl {
gpios = <&gpiob 6 GPIO_ODR_LOW>;
};
gpio_sys_rst_r_odl: sys_rst_r_odl {
gpios = <&gpiog 0 GPIO_ODR_LOW>;
};
gpio_sys_slp_s0ix_l: sys_slp_s0ix_l {
gpios = <&gpioj 5 GPIO_INPUT>;
};
gpio_notebook_mode_r: notebook_mode_r {
gpios = <&gpiod 0 GPIO_INPUT>;
};
gpio_ec_gpd1: ec_gpd1 {
gpios = <&gpiod 1 GPIO_INPUT>;
};
gpio_usb_pd_int_odl: usb_pd_int_odl {
gpios = <&gpiof 5 GPIO_INPUT>;
};
gpio_vccst_pwrgd_od: vccst_pwrgd_od {
gpios = <&gpioh 4 GPIO_ODR_LOW>;
};
};
named-i2c-ports {
compatible = "named-i2c-ports";
i2c_ec_i2c_pd_prog: ec_i2c_pd_prog {
i2c-port = <&i2c1>;
enum-names = "I2C_PORT_PD";
};
i2c_i2c_ec_pmc_pd: i2c_ec_pmc_pd {
i2c-port = <&i2c3ALT>;
enum-names = "I2C_PORT_PMC_PD";
};
i2c_ec_i2c_charger: ec_i2c_charger {
i2c-port = <&i2c4>;
enum-names = "I2C_PORT_BATTERY";
};
i2c_ec_i2c_sensor: ec_i2c_sensor {
i2c-port = <&i2c5>;
enum-names = "I2C_PORT_SENSOR";
};
};
};
&adc0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c3ALT {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};

132
zephyr/program/brox/greenbayupoc/gpio.dtsi Normal file
View File

@ -0,0 +1,132 @@
/* Copyright 2023 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/*
* Arbitrage instructions:
* 1. Determine latest Brox schematic version "arb list -project brox"
* 2. Copy the arbitrage console command from cell A1 of the Brox EC pinout
* and make the following modfication
* a. Add "--force --output=zephyr/program/brox/generated.dtsi"
* before the "project:version" argument
* b. Replace "project:version" with "brox:<latest schematic>"
* c. Execute the arbitrage command
* 3. Check the terminal for errors. "Net not found" and "No matchin GPIO"
* errors are expected. Update the comment below to match.
* 4. Make changes to the manual GPIO overrides as needed.
*/
/*
* Updated for schematic version 0.10.
*
* The command "arb export-ec-devicetree-csv" generates the following
* errors. Reference b/308208621
*
* # EC GPIO Config Error Report
* ## Net not found on chip:
* The following nets provided in the spreadsheet cannot be found or is not
* connected to the EC in the schematic. This may be due to a naming mismatch so
* please check the schematic or list of nets mapped to GPIO's in the reference
* below for potential naming mismatches.
*
* row: 11, net: SPI_EC_DI_BIOS_DO_NC
* row: 12, net: SPI_EC_CS_BIOS_L_NC
* row: 13, net: EC_PCH_RTCRST_NC
* row: 15, net: EC_PCH_PECI_NC
* row: 19, net: EN_PP5000_FAN
* row: 23, net: SPI_EC_CLK_NC
* row: 24, net: SPI_EC_DO_BIOS_DI_NC
* row: 25, net: EC_EN_IMVP91_NC
* row: 52, net: EC_PCH_INT_ODL
* row: 56, net: EC_KB_BL_EN
* row: 58, net: EC_ESPI_ALERT_L_NC
* row: 81, net: PCBEEP_EC_NC
* row: 101, net: ADP_DET_NC
*
* Signals with the "_NC" suffix are no-connects and handled by the
* unused-gpios node.
*
* For all other signals, the GPIO entry is manually added to named-gpios.
*/
/ {
named-gpios {
compatible = "named-gpios";
gpio_pg_vccin_aux_od: pg_vccin_aux_od {
gpios = <&gpiof 3 GPIO_INPUT>;
};
gpio_en_pp5000_fan: en_pp5000_fan {
gpios = <&gpioj 4 GPIO_INPUT>;
};
gpio_ec_pch_int_odl: ec_pch_int_odl {
gpios = <&gpiog 1 GPIO_ODR_LOW>;
enum-name = "GPIO_EC_INT_L";
};
gpio_ec_kso_02_inv: ec_kso_02_inv {
gpios = <&gpioksol 2 GPIO_OUTPUT_HIGH>;
};
/* The legacy system code requires GPIO_ENTERING_RW symbol */
gpio_ec_entering_rw: ec_entering_rw {
enum-name = "GPIO_ENTERING_RW";
};
/* EC_PCH_RTCRST_NC */
gpio_ec_pch_rtsrst: ec_pch_rtcrst {
gpios = <&gpioh 5 GPIO_OUTPUT_LOW>;
};
};
unused-pins {
compatible = "unused-gpios";
unused-gpios =
/* SPI_EC_DI_BIOS_DO */
<&gpiog 5 0>,
/* SPI_EC_CS_BIOS_L */
<&gpiog 3 0>,
/* EC_PCH_PECI */
<&gpiof 6 0>,
/* SPI_EC_CLK */
<&gpiog 7 0>,
/* SPI_EC_DO_BIOS_DI */
<&gpiog 4 0>,
/* EC_EN_IMVP91_NC */
<&gpioh 6 0>,
/* EC_ESPI_ALERT_L_NC */
<&gpiom 6 0>,
/* PCBEEP_EC */
<&gpioa 7 0>,
/* EC_EN_KB_BL */
<&gpioi 2 0>;
};
};
/* The eSPI shim requires this GPIO nodelabel */
gpio_ec_pch_wake_odl: &gpio_sen_mode1_ec_pch_wake_odl {
};
&gpio_ccd_mode_odl {
gpios = <&gpioe 6 GPIO_INPUT>;
};
&gpio_amp_mute_l {
gpios = <&gpioj 6 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
};
/* Default PROCHOT high so it's not asserted
* TODO: b/214509787 - zephyr: subsys/ap_pwrseq: support chipset interface APIs
*/
&gpio_ec_prochot_odl {
gpios = <&gpioi 0 GPIO_ODR_HIGH>;
};
&gpio_ec_wp_odl {
gpios = <&gpioj 3 (GPIO_INPUT | GPIO_ACTIVE_LOW) >;
};
&gpio_acok_ec_od {
enum-name = "GPIO_AC_PRESENT";
};

34
zephyr/program/brox/greenbayupoc/interrupts.dtsi Normal file
View File

@ -0,0 +1,34 @@
/* Copyright 2023 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/ {
gpio_interrupts: gpio-interrupts {
compatible = "cros-ec,gpio-interrupts";
int_ac_present: ac_present {
irq-pin = <&gpio_acok_ec_od>;
flags = <GPIO_INT_EDGE_BOTH>;
handler = "extpower_interrupt";
};
int_power_button: power_button {
irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
flags = <GPIO_INT_EDGE_BOTH>;
handler = "power_button_interrupt";
};
int_lid_open: lid_open {
irq-pin = <&gpio_lid_open>;
flags = <GPIO_INT_EDGE_BOTH>;
handler = "lid_interrupt";
};
};
hibernate-wake-pins {
compatible = "cros-ec,hibernate-wake-pins";
wakeup-irqs = <&int_ac_present
&int_power_button
&int_lid_open>;
};
};

3
zephyr/program/brox/greenbayupoc/project.conf
View File

@ -6,3 +6,6 @@
CONFIG_BOARD_GREENBAYUPOC=y
CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n
CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=n

11
zephyr/program/brox/greenbayupoc/project.overlay
View File

@ -18,14 +18,13 @@ i2c3ALT: &i2c3 {
#include "../binman.dtsi"
#include "../brox.dtsi"
#include "../fan.dtsi"
#include "../generated.dtsi"
#include "../gpio.dtsi"
#include "generated.dtsi"
#include "gpio.dtsi"
#include "../i2c.dtsi"
#include "../interrupts.dtsi"
#include "interrupts.dtsi"
#include "../led_pins.dtsi"
#include "../led_policy.dtsi"
#include "../keyboard.dtsi"
#include "../motionsense.dtsi"
#include "../power_signals.dtsi"
#include "../power_signals_gpios.dtsi"
#include "../pwm.dtsi"
@ -33,9 +32,9 @@ i2c3ALT: &i2c3 {
#include "../usb_typec.dtsi"
#include "../usba.dtsi"
/* Brox project DTS includes*/
/* Greenbayupoc project DTS includes*/
/* Brox overrides follow... */
/* Greenbayupoc overrides follow... */
/{
batteries {

7
zephyr/program/nissa/anraggar/generated.dtsi
View File

@ -39,6 +39,9 @@
named-gpios {
compatible = "named-gpios";
gpio_acc_int_l: acc_int_l {
gpios = <&gpioc 0 GPIO_INPUT>;
};
gpio_all_sys_pwrgd: all_sys_pwrgd {
gpios = <&gpiob 7 GPIO_INPUT>;
};
@ -230,7 +233,7 @@
compatible = "named-i2c-ports";
i2c_ec_i2c_eeprom: ec_i2c_eeprom {
i2c-port = <&i2c0>;
i2c-port = <&i2c2>;
enum-names = "I2C_PORT_EEPROM";
};
i2c_ec_i2c_batt: ec_i2c_batt {
@ -238,7 +241,7 @@
enum-names = "I2C_PORT_BATTERY";
};
i2c_ec_i2c_sensor: ec_i2c_sensor {
i2c-port = <&i2c2>;
i2c-port = <&i2c0>;
enum-names = "I2C_PORT_SENSOR";
};
i2c_ec_i2c_usb_c1: ec_i2c_usb_c1 {

7
zephyr/program/nissa/anraggar/motionsense.dtsi
View File

@ -13,6 +13,8 @@
*/
bmi3xx-int = &base_accel;
lsm6dsm-int = &base_accel;
bma4xx-int = &lid_accel;
lis2dw12-int = &lid_accel;
};
/*
@ -222,6 +224,7 @@
port = <&i2c_ec_i2c_sensor>;
rot-standard-ref = <&base_rot_lsm6dsm>;
drv-data = <&lsm6dsm_gyro_data>;
default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
alternate-for = <&base_gyro>;
alternate-ssfc-indicator = <&base_sensor_lsm6dsm>;
};
@ -234,8 +237,6 @@
* list of GPIO interrupts that have to
* be enabled at initial stage
*/
sensor-irqs = <&int_imu>;
/* list of sensors in force mode */
accel-force-mode-sensors = <&lid_accel>;
sensor-irqs = <&int_imu &int_lid_imu>;
};
};

17
zephyr/program/nissa/anraggar/overlay.dtsi
View File

@ -71,6 +71,11 @@
flags = <GPIO_INT_EDGE_FALLING>;
handler = "motion_interrupt";
};
int_lid_imu: lid_imu {
irq-pin = <&gpio_acc_int_l>;
flags = <GPIO_INT_EDGE_FALLING>;
handler = "lid_accel_interrupt";
};
int_ac_present: ac_present {
irq-pin = <&gpio_ec_acok_od>;
flags = <GPIO_INT_EDGE_BOTH>;
@ -241,7 +246,7 @@
};
};
&i2c0 {
&i2c2 {
label = "I2C_EEPROM";
clock-frequency = <I2C_BITRATE_FAST>;
@ -256,6 +261,10 @@
pinctrl-0 = <&i2c0_clk_gpb3_default
&i2c0_data_gpb4_default>;
pinctrl-names = "default";
scl-gpios = <&gpiob 3 0>;
sda-gpios = <&gpiob 4 0>;
channel-switch-sel = <I2C_CHA_LOCATE>;
status = "okay";
};
&i2c1 {
@ -266,12 +275,16 @@
pinctrl-names = "default";
};
&i2c2 {
&i2c0 {
label = "I2C_SENSOR";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c2_clk_gpf6_default
&i2c2_data_gpf7_default>;
pinctrl-names = "default";
scl-gpios = <&gpiof 6 0>;
sda-gpios = <&gpiof 7 0>;
channel-switch-sel = <I2C_CHC_LOCATE>;
status = "okay";
};
&i2c4 {

2
zephyr/program/nissa/anraggar/project.conf
View File

@ -45,7 +45,7 @@ CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y
CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=125000
CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y

55
zephyr/program/nissa/anraggar/src/board.c
View File

@ -10,8 +10,11 @@
*/
#include "accelgyro.h"
#include "battery.h"
#include "chipset.h"
#include "common.h"
#include "cros_cbi.h"
#include "driver/accel_bma4xx.h"
#include "driver/accel_lis2dw12_public.h"
#include "driver/accelgyro_bmi323.h"
#include "driver/accelgyro_lsm6dsm.h"
#include "gpio/gpio_int.h"
@ -25,8 +28,6 @@
LOG_MODULE_REGISTER(board_init, LOG_LEVEL_ERR);
static bool board_is_clamshell;
static void board_setup_init(void)
{
int ret;
@ -38,17 +39,54 @@ static void board_setup_init(void)
return;
}
if (val == CLAMSHELL) {
board_is_clamshell = true;
motion_sensor_count = 0;
gmr_tablet_switch_disable();
gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l),
GPIO_INPUT | GPIO_PULL_UP);
gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_imu));
gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_acc_int_l),
GPIO_INPUT | GPIO_PULL_UP);
}
}
DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_PRE_DEFAULT);
static void motionsense_suspend(void)
{
int ret;
uint32_t val;
ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
if (ret != 0) {
LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
return;
}
if (val != CLAMSHELL) {
gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_imu));
}
}
DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, motionsense_suspend, HOOK_PRIO_DEFAULT);
static void motionsense_resume(void)
{
int ret;
uint32_t val;
ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
if (ret != 0) {
LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
return;
}
if (val != CLAMSHELL) {
gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_imu));
}
}
DECLARE_HOOK(HOOK_CHIPSET_RESUME, motionsense_resume, HOOK_PRIO_DEFAULT);
static bool base_use_alt_sensor;
static bool lid_use_alt_sensor;
void motion_interrupt(enum gpio_signal signal)
{
@ -59,10 +97,21 @@ void motion_interrupt(enum gpio_signal signal)
}
}
void lid_accel_interrupt(enum gpio_signal signal)
{
if (lid_use_alt_sensor) {
lis2dw12_interrupt(signal);
} else {
bma4xx_interrupt(signal);
}
}
static void alt_sensor_init(void)
{
base_use_alt_sensor = cros_cbi_ssfc_check_match(
CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_lsm6dsm)));
lid_use_alt_sensor = cros_cbi_ssfc_check_match(
CBI_SSFC_VALUE_ID(DT_NODELABEL(lid_sensor_lis2dw12)));
motion_sensors_check_ssfc();
}

3
zephyr/program/rauru/CMakeLists.txt
View File

@ -7,7 +7,8 @@ find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
target_sources(app PRIVATE ${PLATFORM_EC_PROGRAM_DIR}/rauru/src/usbc.c
${PLATFORM_EC_PROGRAM_DIR}/rauru/src/hibernate.c)
${PLATFORM_EC_PROGRAM_DIR}/rauru/src/hibernate.c
${PLATFORM_EC_PROGRAM_DIR}/rauru/src/hooks.c)
target_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_DP_MODE app PRIVATE
${PLATFORM_EC_PROGRAM_DIR}/rauru/src/dp_alt_mode.c)
target_sources_ifdef(CONFIG_RAURU_BOARD_HAS_HDMI_SUPPORT app PRIVATE

2
zephyr/program/rauru/generated.dtsi
View File

@ -111,9 +111,11 @@
};
gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
gpios = <&gpioe 3 (GPIO_INPUT)>;
enum-name = "GPIO_VOLUME_DOWN_L";
};
gpio_ec_volup_btn_odl: ec_volup_btn_odl {
gpios = <&gpioe 4 (GPIO_INPUT)>;
enum-name = "GPIO_VOLUME_UP_L";
};
gpio_en_hdmi_pwr: en_hdmi_pwr {
gpios = <&gpioi 5 (GPIO_OUTPUT | GPIO_ACTIVE_HIGH)>;

15
zephyr/program/rauru/interrupts.dtsi
View File

@ -17,6 +17,16 @@
flags = <GPIO_INT_EDGE_BOTH>;
handler = "power_button_interrupt";
};
int_volume_up: volume-up {
irq-pin = <&gpio_ec_volup_btn_odl>;
flags = <GPIO_INT_EDGE_BOTH>;
handler = "button_interrupt";
};
int_volume_down: volume-down {
irq-pin = <&gpio_ec_voldn_btn_odl>;
flags = <GPIO_INT_EDGE_BOTH>;
handler = "button_interrupt";
};
int_lid_open: lid-open {
irq-pin = <&gpio_lid_open_3v3>;
flags = <GPIO_INT_EDGE_BOTH>;
@ -72,5 +82,10 @@
flags = <GPIO_INT_EDGE_FALLING>;
handler = "tcs3400_interrupt";
};
int_ap_xhci_init_done: ap-xhci-init-done {
irq-pin = <&gpio_ap_xhci_init_done>;
flags = <GPIO_INT_EDGE_BOTH>;
handler = "xhci_interrupt";
};
};
};

2
zephyr/program/rauru/program.conf
View File

@ -27,7 +27,9 @@ CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
# Buttons
CONFIG_PLATFORM_EC_BUTTON=y
CONFIG_PLATFORM_EC_POWER_BUTTON=y
CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
# Lid Switch
CONFIG_PLATFORM_EC_LID_SWITCH=y

1
zephyr/program/rauru/rauru/project.conf
View File

@ -7,3 +7,4 @@ CONFIG_BOARD_RAURU=y
CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
CONFIG_PLATFORM_EC_PP3700_DISCHARGE_TIME_MS=3500

1
zephyr/program/rauru/rauru/project.overlay
View File

@ -9,6 +9,7 @@
#include "../arbitrage.dtsi"
#include "../common.dtsi"
#include "../usbc.dtsi"
#include "../usba.dtsi"
#include "../generated.dtsi"
#include "../interrupts.dtsi"
#include "../motionsense.dtsi"

63
zephyr/program/rauru/src/hooks.c Normal file
View File

@ -0,0 +1,63 @@
/* Copyright 2024 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "gpio.h"
#include "gpio/gpio_int.h"
#include "gpio_signal.h"
#include "hooks.h"
#include "usb_charge.h"
#include "usb_pd.h"
#include "usb_tc_sm.h"
#include <zephyr/drivers/gpio.h>
static void rauru_common_init(void)
{
gpio_enable_dt_interrupt(
GPIO_INT_FROM_NODELABEL(int_ap_xhci_init_done));
}
DECLARE_HOOK(HOOK_INIT, rauru_common_init, HOOK_PRIO_PRE_DEFAULT);
/* USB-A */
void xhci_interrupt(enum gpio_signal signal)
{
const int xhci_stat = gpio_get_level(signal);
#ifdef USB_PORT_ENABLE_COUNT
enum usb_charge_mode mode = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
gpio_ap_xhci_init_done)) ?
USB_CHARGE_MODE_ENABLED :
USB_CHARGE_MODE_DISABLED;
for (int i = 0; i < USB_PORT_ENABLE_COUNT; i++) {
usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
}
#endif
for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
/*
* Enable DRP toggle after XHCI inited. This is used to follow
* USB 3.2 spec 10.3.1.1.
*/
if (xhci_stat) {
pd_set_dual_role(i, PD_DRP_TOGGLE_ON);
} else if (tc_is_attached_src(i)) {
/*
* This is a AP reset S0->S0 transition.
* We should set the role back to sink.
*/
pd_set_dual_role(i, PD_DRP_FORCE_SINK);
}
}
}
__override enum pd_dual_role_states pd_get_drp_state_in_s0(void)
{
if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done))) {
return PD_DRP_TOGGLE_ON;
} else {
return PD_DRP_FORCE_SINK;
}
}

11
zephyr/program/rauru/usba.dtsi Normal file
View File

@ -0,0 +1,11 @@
/* Copyright 2024 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/{
usba-port-enable-list {
compatible = "cros-ec,usba-port-enable-pins";
enable-pins = <&gpio_en_pp5000_usba_vbus>;
};
};

2
zephyr/test/krabby/prj.conf
View File

@ -31,12 +31,12 @@ CONFIG_PLATFORM_EC_SWITCH=n
CONFIG_PLATFORM_EC_USBC=y
CONFIG_PLATFORM_EC_USB_CHARGER=y
CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y
CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=y
CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y
CONFIG_PLATFORM_EC_USB_POWER_DELIVERY=y
CONFIG_PLATFORM_EC_VBOOT_HASH=n
CONFIG_PLATFORM_EC_PP3700_DISCHARGE_TIME_MS=100
CONFIG_PLATFORM_EC_USBC_PPC=y