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board: clear out disabled boards left for building utils 

These boards were removed from buildall as they ran out of flash
space, but we kept the board directory around so that we could
continue to build the ec-utils ebuild, which used to require the board
directory to build tools like ectool (this was fixed in CL:2283999).

Since we've detangled the host utils ebuilds, these directories can
now be removed.

BUG=chromium:1035536
BRANCH=none
TEST=buildall

Change-Id: I736b323f9e977d74ca31788ed320befa2289a9dc
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2326304
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This commit is contained in:
Jack Rosenthal 2020-07-29 09:31:41 -06:00 committed by Commit Bot
parent dd3bc8ec47
commit bcc2c00d56
36 changed files with 1 additions and 3874 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile.rules
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@ -17,7 +17,7 @@ build-srcs := $(foreach u,$(build-util-bin),$(sort $($(u)-objs:%.o=util/%.c) $(w
host-srcs := $(foreach u,$(host-util-bin),$(sort $($(u)-objs:%.o=util/%.c) $(wildcard util/$(u).c)))
# Don't do a build test on the following boards:
skip_boards = OWNERS chell chell_pd cr50 glados glados_pd gru host kevin
skip_boards = OWNERS cr50 host
boards := $(filter-out $(skip_boards),$(notdir $(wildcard board/* private*/board/*)))
# Create output directories if necessary

81
board/chell/battery.c
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@ -1,81 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "charge_state.h"
#include "console.h"
#include "ec_commands.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define SB_SHUTDOWN_DATA 0x0010
/* Battery info for proto */
static const struct battery_info info = {
.voltage_max = 13050, /* mV */
.voltage_normal = 11400,
.voltage_min = 9000,
.precharge_current = 392, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 60,
.charging_min_c = 0,
.charging_max_c = 60,
.discharging_min_c = 0,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
int rv;
/* Ship mode command must be sent twice to take effect */
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
if (rv != EC_SUCCESS)
return EC_RES_ERROR;
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
}
int charger_profile_override(struct charge_state_data *curr)
{
const struct battery_info *batt_info;
/* battery temp in 0.1 deg C */
int bat_temp_c = curr->batt.temperature - 2731;
batt_info = battery_get_info();
/* Don't charge if outside of allowable temperature range */
if (bat_temp_c >= batt_info->charging_max_c * 10 ||
bat_temp_c < batt_info->charging_min_c * 10) {
curr->requested_current = 0;
curr->requested_voltage = 0;
curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
curr->state = ST_IDLE;
}
return 0;
}
/* Customs options controllable by host command. */
#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
enum ec_status charger_profile_override_get_param(uint32_t param,
uint32_t *value)
{
return EC_RES_INVALID_PARAM;
}
enum ec_status charger_profile_override_set_param(uint32_t param,
uint32_t value)
{
return EC_RES_INVALID_PARAM;
}

469
board/chell/board.c
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@ -1,469 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Chell board-specific configuration */
#include "adc_chip.h"
#include "bd99992gw.h"
#include "charge_manager.h"
#include "charge_state.h"
#include "charger.h"
#include "chipset.h"
#include "console.h"
#include "extpower.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "i2c.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "pi3usb9281.h"
#include "power.h"
#include "power_button.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "spi.h"
#include "switch.h"
#include "system.h"
#include "task.h"
#include "tcpci.h"
#include "temp_sensor.h"
#include "timer.h"
#include "uart.h"
#include "usb_charge.h"
#include "usb_mux.h"
#include "usb_mux/ps8740.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "util.h"
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
#define I2C_ADDR_BD99992_FLAGS 0x30
/* Exchange status with PD MCU. */
static void pd_mcu_interrupt(enum gpio_signal signal)
{
#ifdef HAS_TASK_PDCMD
/* Exchange status with PD MCU to determine interrupt cause */
host_command_pd_send_status(0);
#endif
}
void vbus0_evt(enum gpio_signal signal)
{
/* VBUS present GPIO is inverted */
usb_charger_vbus_change(0, !gpio_get_level(signal));
task_wake(TASK_ID_PD_C0);
}
void vbus1_evt(enum gpio_signal signal)
{
/* VBUS present GPIO is inverted */
usb_charger_vbus_change(1, !gpio_get_level(signal));
task_wake(TASK_ID_PD_C1);
}
void usb0_evt(enum gpio_signal signal)
{
task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
}
void usb1_evt(enum gpio_signal signal)
{
task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
}
#include "gpio_list.h"
/* ADC channels */
const struct adc_t adc_channels[] = {
/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
[ADC_VBUS] = {"VBUS", 30000, 1024, 0, 1},
/* Adapter current output or battery discharging current */
[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
/* System current consumption */
[ADC_PSYS] = {"PSYS", 1, 1, 0, 4},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
/* Use alternate 100kHz clock source, keep active in low-power idle */
{2, PWM_CONFIG_ALT_CLOCK | PWM_CONFIG_DSLEEP},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
const struct i2c_port_t i2c_ports[] = {
{"pmic", MEC1322_I2C0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
{"muxes", MEC1322_I2C0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
{"pd_mcu", MEC1322_I2C1, 500, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
{"batt", MEC1322_I2C3, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
{
.bus_type = EC_BUS_TYPE_I2C,
.i2c_info = {
.port = I2C_PORT_TCPC,
.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
},
.drv = &tcpci_tcpm_drv,
},
{
.bus_type = EC_BUS_TYPE_I2C,
.i2c_info = {
.port = I2C_PORT_TCPC,
.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1,
},
.drv = &tcpci_tcpm_drv,
},
};
/* SPI devices */
const struct spi_device_t spi_devices[] = {
{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
const enum gpio_signal hibernate_wake_pins[] = {
GPIO_AC_PRESENT,
GPIO_LID_OPEN,
GPIO_POWER_BUTTON_L,
};
const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
#ifdef CONFIG_KEYBOARD_FACTORY_TEST
/*
* We have total 28 pins for keyboard connecter, {-1, -1} mean
* the N/A pin that don't consider it and reserve index 0 area
* that we don't have pin 0.
*/
const int keyboard_factory_scan_pins[][2] = {
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
{12, 6}, {4, 3}, {4, 2}, {0, 2}, {14, 2},
{4, 0}, {0, 0}, {-1, -1}, {3, 2}, {10, 3},
{10, 0}, {12, 5}, {-1, -1}, {10, 2}, {-1, -1},
{0, 1}, {10, 4}, {-1, -1}, {-1, -1}, {0, 4},
{10, 7}, {10, 6}, {0, 3}, {0, 5},
};
const int keyboard_factory_scan_pins_used =
ARRAY_SIZE(keyboard_factory_scan_pins);
#endif
struct pi3usb9281_config pi3usb9281_chips[] = {
{
.i2c_port = I2C_PORT_USB_CHARGER_1,
.mux_lock = NULL,
},
{
.i2c_port = I2C_PORT_USB_CHARGER_2,
.mux_lock = NULL,
},
};
BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
static int ps8740_tune_mux(int port)
{
/* Apply same USB EQ settings to both Type-C mux */
ps8740_tune_usb_eq(port,
PS8740_USB_EQ_TX_6_5_DB,
PS8740_USB_EQ_RX_14_3_DB);
return EC_SUCCESS;
}
struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
{
.usb_port = 0,
.i2c_port = I2C_PORT_USB_MUX,
.i2c_addr_flags = 0x1A,
.driver = &ps8740_usb_mux_driver,
.board_init = &ps8740_tune_mux,
},
{
.usb_port = 1,
.i2c_port = I2C_PORT_USB_MUX,
.i2c_addr_flags = 0x10,
.driver = &ps8740_usb_mux_driver,
.board_init = &ps8740_tune_mux,
}
};
/**
* Reset PD MCU
*/
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_PD_RST_L, 0);
usleep(100);
gpio_set_level(GPIO_PD_RST_L, 1);
}
const struct temp_sensor_t temp_sensors[] = {
{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0, 4},
/* These BD99992GW temp sensors are only readable in S0 */
{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM0, 4},
{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM1, 4},
{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM2, 4},
{"Wifi", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM3, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
static void board_pmic_init(void)
{
/* DISCHGCNT3 - enable 100 ohm discharge on V1.00A */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3e, 0x04);
/*
* No need to re-init below settings since they are present on all MP
* ROs and PMIC settings are sticky across sysjump
*/
if (system_jumped_late())
return;
/* Set CSDECAYEN / VCCIO decays to 0V at assertion of SLP_S0# */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x4a);
/*
* Set V100ACNT / V1.00A Control Register:
* Nominal output = 1.0V.
*/
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x1a);
/*
* Set V085ACNT / V0.85A Control Register:
* Lower power mode = 0.7V.
* Nominal output = 1.0V.
*/
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
/* VRMODECTRL - enable low-power mode for VCCIO and V0.85A */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3b, 0x18);
}
DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_DEFAULT);
/* Initialize board. */
static void board_init(void)
{
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
/* Enable pericom BC1.2 interrupts */
gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
/* Provide AC status to the PCH */
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
/* Proto board workarounds */
if (system_get_board_version() == 0) {
/* Disable interrupt for SLP_S0 */
gpio_set_flags(GPIO_PCH_SLP_S0_L,
GPIO_INPUT | GPIO_PULL_DOWN);
/* Add internal pullup on PLATFORM_EC_PROCHOT */
gpio_set_flags(GPIO_PLATFORM_EC_PROCHOT,
GPIO_INPUT | GPIO_PULL_UP);
}
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/**
* Buffer the AC present GPIO to the PCH.
*/
static void board_extpower(void)
{
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
/**
* Set active charge port -- only one port can be active at a time.
*
* @param charge_port Charge port to enable.
*
* Returns EC_SUCCESS if charge port is accepted and made active,
* EC_ERROR_* otherwise.
*/
int board_set_active_charge_port(int charge_port)
{
/* charge port is a realy physical port */
int is_real_port = (charge_port >= 0 &&
charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
/* check if we are source vbus on that port */
int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
GPIO_USB_C1_5V_EN);
if (is_real_port && source) {
CPRINTS("Skip enable p%d", charge_port);
return EC_ERROR_INVAL;
}
CPRINTS("New chg p%d", charge_port);
if (charge_port == CHARGE_PORT_NONE) {
/* Disable both ports */
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
} else {
/* Make sure non-charging port is disabled */
gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L :
GPIO_USB_C1_CHARGE_EN_L, 1);
/* Enable charging port */
gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L :
GPIO_USB_C0_CHARGE_EN_L, 0);
}
return EC_SUCCESS;
}
/**
* Set the charge limit based upon desired maximum.
*
* @param port Port number.
* @param supplier Charge supplier type.
* @param charge_ma Desired charge limit (mA).
* @param charge_mv Negotiated charge voltage (mV).
*/
void board_set_charge_limit(int port, int supplier, int charge_ma,
int max_ma, int charge_mv)
{
charge_set_input_current_limit(MAX(charge_ma,
CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
}
/* Called on AP S5 -> S3 transition */
static void board_chipset_startup(void)
{
gpio_set_level(GPIO_USB1_ENABLE, 1);
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
}
DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
/* Called on AP S3 -> S5 transition */
static void board_chipset_shutdown(void)
{
gpio_set_level(GPIO_USB1_ENABLE, 0);
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
/* Called on AP S3 -> S0 transition */
static void board_chipset_resume(void)
{
gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 1);
gpio_set_level(GPIO_PP1800_DX_DMIC_EN, 1);
}
DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
/* Called on AP S0 -> S3 transition */
static void board_chipset_suspend(void)
{
gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 0);
gpio_set_level(GPIO_PP1800_DX_DMIC_EN, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
void board_hibernate(void)
{
CPRINTS("Triggering PMIC shutdown.");
uart_flush_output();
/* Trigger PMIC shutdown. */
if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
/*
* If we can't tell the PMIC to shutdown, instead reset
* and don't start the AP. Hopefully we'll be able to
* communicate with the PMIC next time.
*/
CPRINTS("PMIC i2c failed.");
system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
}
/* Await shutdown. */
while (1)
;
}
/* Make the pmic re-sequence the power rails under these conditions. */
#define PMIC_RESET_FLAGS \
(EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD)
static void board_handle_reboot(void)
{
int flags;
if (system_jumped_late())
return;
/* Interrogate current reset flags from previous reboot. */
flags = system_get_reset_flags();
if (!(flags & PMIC_RESET_FLAGS))
return;
/* Preserve AP off request. */
if (flags & EC_RESET_FLAG_AP_OFF)
chip_save_reset_flags(EC_RESET_FLAG_AP_OFF);
ccprintf("Restarting system with PMIC.\n");
/* Flush console */
cflush();
/* Bring down all rails but RTC rail (including EC power). */
gpio_set_level(GPIO_PMIC_LDO_EN, 1);
while (1)
; /* wait here */
}
DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
/*
* Various voltage rails will be enabled / disabled by the PMIC when
* GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
* by approximately 25ms in order to allow V1.00A to sufficiently discharge
* first.
*
* Therefore, after GPIO_PMIC_SLP_SUS_L goes high, ignore the state of
* the V12_EN pin: Keep V0.85A enabled.
*
* When GPIO_PMIC_SLP_SUS_L goes low, delay 25ms, and make V12_EN function
* as normal - this should result in V0.85A discharging immediately after the
* i2c write completes.
*/
void chipset_set_pmic_slp_sus_l(int level)
{
static int previous_level;
int val;
gpio_set_level(GPIO_PMIC_SLP_SUS_L, level);
if (previous_level != level) {
/* Rising edge: Force V0.85A enable. Falling: Pin control. */
val = level ? 0x80 : 0;
if (!level)
msleep(25);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
0x43, val);
previous_level = level;
}
}

218
board/chell/board.h
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@ -1,218 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Chell board configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/*
* Allow dangerous commands.
* TODO: Remove this config before production.
*/
#define CONFIG_SYSTEM_UNLOCKED
/* Optional features */
#define CONFIG_ADC
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_HAS_RTC_RESET
#define CONFIG_BOARD_VERSION_GPIO
#define CONFIG_CHARGE_MANAGER
#define CONFIG_CHARGE_RAMP_HW
#define CONFIG_CHARGER
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_ISL9237
#define CONFIG_CHARGER_ILIM_PIN_DISABLED
#define CONFIG_CHARGER_INPUT_CURRENT 512
#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
#define CONFIG_CHARGER_PROFILE_OVERRIDE
#define CONFIG_CHARGER_SENSE_RESISTOR 10
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
#undef CONFIG_CMD_BATTFAKE
#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
#define CONFIG_CHIPSET_SKYLAKE
#define CONFIG_CHIPSET_RESET_HOOK
#define CONFIG_CLOCK_CRYSTAL
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_HOSTCMD_PD
#define CONFIG_HOSTCMD_PD_PANIC
#define CONFIG_I2C
#define CONFIG_I2C_MASTER
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_KEYBOARD_COL2_INVERTED
#define CONFIG_KEYBOARD_FACTORY_TEST
#define CONFIG_LED_COMMON
#define CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LTO
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
#define CONFIG_POWER_S0IX
#define CONFIG_PWM
#define CONFIG_PWM_KBLIGHT
/* All data won't fit in data RAM. So, moving boundary slightly. */
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE (104 * 1024)
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* We're space constrained on Chell, so reduce the UART TX buffer size. */
#undef CONFIG_UART_TX_BUF_SIZE
#define CONFIG_UART_TX_BUF_SIZE 512
#define CONFIG_USB_CHARGER
#define CONFIG_USB_MUX_PS8740
#define CONFIG_USB_POWER_DELIVERY
#define CONFIG_USB_PD_TCPMV1
#define CONFIG_USB_PD_ALT_MODE
#define CONFIG_USB_PD_ALT_MODE_DFP
#define CONFIG_USB_PD_COMM_LOCKED
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_LOGGING
#define CONFIG_USB_PD_PORT_MAX_COUNT 2
#define CONFIG_USB_PD_TCPM_TCPCI
#define CONFIG_USB_PD_TRY_SRC
#define CONFIG_USB_PD_VBUS_DETECT_GPIO
#define CONFIG_BC12_DETECT_PI3USB9281
#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
#define CONFIG_USBC_SS_MUX
#define CONFIG_USBC_SS_MUX_DFP_ONLY
#define CONFIG_USBC_VCONN
#define CONFIG_USBC_VCONN_SWAP
#define CONFIG_VBOOT_HASH
#define CONFIG_SPI_FLASH_PORT 1
#define CONFIG_SPI_FLASH
#define CONFIG_FLASH_SIZE 524288
#define CONFIG_SPI_FLASH_W25X40
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_BD99992GW
#define CONFIG_THERMISTOR_NCP15WB
#define CONFIG_DPTF
/*
* Enable 1 slot of secure temporary storage to support
* suspend/resume with read/write memory training.
*/
#define CONFIG_VSTORE
#define CONFIG_VSTORE_SLOT_COUNT 1
#define CONFIG_WATCHDOG_HELP
#define CONFIG_WIRELESS
#define CONFIG_WIRELESS_SUSPEND \
(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN_EN
/* LED signals */
#define GPIO_BAT_LED_RED GPIO_CHARGE_LED_1
#define GPIO_BAT_LED_GREEN GPIO_CHARGE_LED_2
/* I2C ports */
#define I2C_PORT_PMIC MEC1322_I2C0_0
#define I2C_PORT_USB_CHARGER_1 MEC1322_I2C0_1
#define I2C_PORT_USB_MUX MEC1322_I2C0_1
#define I2C_PORT_USB_CHARGER_2 MEC1322_I2C0_0
#define I2C_PORT_PD_MCU MEC1322_I2C1
#define I2C_PORT_TCPC MEC1322_I2C1
#define I2C_PORT_BATTERY MEC1322_I2C3
#define I2C_PORT_CHARGER MEC1322_I2C3
/* Thermal sensors read through PMIC ADC interface */
#define I2C_PORT_THERMAL I2C_PORT_PMIC
/* Modules we want to exclude */
#undef CONFIG_CMD_ACCELSPOOF
#undef CONFIG_CMD_BATTFAKE
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_HASH
#undef CONFIG_CMD_HCDEBUG
#undef CONFIG_CMD_I2C_SCAN
#undef CONFIG_CMD_MD
#undef CONFIG_CMD_MMAPINFO
#undef CONFIG_CMD_POWERINDEBUG
#undef CONFIG_CMD_PWR_AVG
#undef CONFIG_CMD_SLEEPMASK
#undef CONFIG_CMD_SLEEPMASK_SET
#undef CONFIG_CMD_SYSLOCK
#undef CONFIG_CMD_TEMP_SENSOR
#undef CONFIG_CMD_TIMERINFO
#undef CONFIG_CONSOLE_CMDHELP
#undef CONFIG_CONSOLE_HISTORY
#undef CONFIG_EC_CMD_PD_CHIP_INFO
#undef CONFIG_CMD_I2C_XFER
#ifndef __ASSEMBLER__
#include "gpio_signal.h"
#include "registers.h"
/* ADC signal */
enum adc_channel {
ADC_VBUS,
ADC_AMON_BMON,
ADC_PSYS,
/* Number of ADC channels */
ADC_CH_COUNT
};
enum pwm_channel {
PWM_CH_KBLIGHT,
/* Number of PWM channels */
PWM_CH_COUNT
};
enum temp_sensor_id {
TEMP_SENSOR_BATTERY,
/* These temp sensors are only readable in S0 */
TEMP_SENSOR_AMBIENT,
TEMP_SENSOR_CHARGER,
TEMP_SENSOR_DRAM,
TEMP_SENSOR_WIFI,
TEMP_SENSOR_COUNT
};
/* TODO: determine the following board specific type-C power constants */
/*
* delay to turn on the power supply max is ~16ms.
* delay to turn off the power supply max is about ~180ms.
*/
#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
/* delay to turn on/off vconn */
#define PD_VCONN_SWAP_DELAY 5000 /* us */
/* Define typical operating power and max power */
#define PD_OPERATING_POWER_MW 15000
#define PD_MAX_POWER_MW 45000
#define PD_MAX_CURRENT_MA 3000
/* Try to negotiate to 20V since i2c noise problems should be fixed. */
#define PD_MAX_VOLTAGE_MV 20000
#ifdef CONFIG_KEYBOARD_FACTORY_TEST
extern const int keyboard_factory_scan_pins[][2];
extern const int keyboard_factory_scan_pins_used;
#endif
/* Reset PD MCU */
void board_reset_pd_mcu(void);
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

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board/chell/build.mk
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# -*- makefile -*-
# Copyright 2015 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is SMSC MEC1322 / external SPI is 512KB / external clock is crystal
CHIP:=mec1322
CHIP_SPI_SIZE_KB:=512
board-y=board.o led.o
board-$(CONFIG_BATTERY_SMART)+=battery.o
board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o

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board/chell/ec.tasklist
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/*
* See CONFIG_TASK_LIST in config.h for details.
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)

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board/chell/gpio.inc
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/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(LID_OPEN, PIN(27), GPIO_INT_BOTH, lid_interrupt)
GPIO_INT(AC_PRESENT, PIN(30), GPIO_INT_BOTH, extpower_interrupt)
GPIO_INT(WP_L, PIN(33), GPIO_INT_BOTH, switch_interrupt)
/* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */
GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt)
#ifdef CONFIG_POWER_S0IX
GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH, power_signal_interrupt)
#endif
/* RSMRST from PMIC */
GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PMIC_INT_L, PIN(50), GPIO_INT_FALLING, power_signal_interrupt)
GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_FALLING | GPIO_PULL_UP, pd_mcu_interrupt)
GPIO_INT(USB_C0_VBUS_WAKE_L,PIN(152), GPIO_INT_BOTH, vbus0_evt)
GPIO_INT(USB_C1_VBUS_WAKE_L,PIN(123), GPIO_INT_BOTH, vbus1_evt)
GPIO_INT(USB_C0_BC12_INT_L, PIN(124), GPIO_INT_FALLING, usb0_evt)
GPIO_INT(USB_C1_BC12_INT_L, PIN(145), GPIO_INT_FALLING, usb1_evt)
GPIO_INT(PMIC_DPWROK, PIN(133), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(UART0_RX, PIN(162), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
/* PMIC */
GPIO(PMIC_LDO_EN, PIN(55), GPIO_OUT_LOW)
GPIO(PMIC_SLP_SUS_L, PIN(201), GPIO_OUT_LOW)
/* I2C pins - these will be reconfigured for alternate function below */
GPIO(I2C0_0_SCL, PIN(15), GPIO_INPUT)
GPIO(I2C0_0_SDA, PIN(16), GPIO_INPUT)
GPIO(I2C0_1_SCL, PIN(134), GPIO_INPUT)
GPIO(I2C0_1_SDA, PIN(17), GPIO_INPUT)
GPIO(I2C1_SCL, PIN(22), GPIO_INPUT)
GPIO(I2C1_SDA, PIN(23), GPIO_INPUT)
GPIO(I2C2_SCL, PIN(20), GPIO_INPUT)
GPIO(I2C2_SDA, PIN(21), GPIO_INPUT)
GPIO(I2C3_SCL, PIN(24), GPIO_INPUT)
GPIO(I2C3_SDA, PIN(25), GPIO_INPUT)
/* PCH */
GPIO(PCH_SCI_L, PIN(26), GPIO_ODR_HIGH)
GPIO(PCH_SMI_L, PIN(44), GPIO_ODR_HIGH)
GPIO(PCH_PWRBTN_L, PIN(45), GPIO_OUTPUT)
GPIO(PCH_SEC_DISABLE_L, PIN(65), GPIO_OUT_HIGH)
GPIO(PCH_WAKE_L, PIN(66), GPIO_ODR_HIGH)
GPIO(PCH_ACOK, PIN(110), GPIO_OUT_LOW)
GPIO(PCH_RCIN_L, PIN(135), GPIO_ODR_HIGH)
GPIO(PCH_RSMRST_L, PIN(143), GPIO_OUT_LOW)
GPIO(PCH_RTCRST, PIN(163), GPIO_OUT_LOW)
GPIO(SYS_RESET_L, PIN(121), GPIO_ODR_HIGH)
GPIO(ENTERING_RW, PIN(41), GPIO_OUT_LOW)
#ifndef CONFIG_POWER_S0IX
GPIO(PCH_SLP_S0_L, PIN(211), GPIO_INPUT)
#endif
/* Devices and power */
GPIO(PP1800_DX_DMIC_EN, PIN(11), GPIO_OUT_LOW)
GPIO(PP1800_DX_AUDIO_EN, PIN(141), GPIO_OUT_LOW)
GPIO(PP3300_DX_WLAN_EN, PIN(203), GPIO_OUT_LOW)
GPIO(WLAN_OFF_L, PIN(132), GPIO_OUT_LOW)
GPIO(TRACKPAD_INT_L, PIN(127), GPIO_INPUT)
GPIO(ENABLE_BACKLIGHT, PIN(202), GPIO_OUT_LOW)
GPIO(ENABLE_TOUCHPAD, PIN(53), GPIO_OUT_LOW)
GPIO(BAT_PRESENT_L, PIN(56), GPIO_INPUT)
GPIO(PLATFORM_EC_PROCHOT, PIN(151), GPIO_INPUT)
GPIO(CPU_PROCHOT, PIN(52), GPIO_OUT_LOW)
/* USB PD and port power */
GPIO(PD_RST_L, PIN(130), GPIO_ODR_HIGH)
GPIO(USB_PD_WAKE, PIN(60), GPIO_OUT_HIGH)
GPIO(USB_C0_DP_HPD, PIN(46), GPIO_OUT_LOW)
GPIO(USB_C1_DP_HPD, PIN(51), GPIO_OUT_LOW)
GPIO(USB_C0_5V_EN, PIN(154), GPIO_OUT_LOW)
GPIO(USB_C1_5V_EN, PIN(204), GPIO_OUT_LOW)
GPIO(USB_C0_CHARGE_EN_L, PIN(64), GPIO_OUT_LOW)
GPIO(USB_C1_CHARGE_EN_L, PIN(210), GPIO_OUT_LOW)
GPIO(USB1_ENABLE, PIN(36), GPIO_OUT_LOW)
GPIO(USB2_OTG_ID, PIN(13), GPIO_ODR_LOW)
GPIO(USB2_OTG_VBUSSENSE, PIN(140), GPIO_OUT_LOW)
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
/* Board version */
GPIO(BOARD_VERSION1, PIN(10), GPIO_INPUT)
GPIO(BOARD_VERSION2, PIN(7), GPIO_INPUT)
GPIO(BOARD_VERSION3, PIN(6), GPIO_INPUT)
GPIO(KBD_KSO2, PIN(101), GPIO_KB_OUTPUT_COL2)
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
GPIO(KEYBOARD_BACKLIGHT, PIN(34), GPIO_OUT_LOW)
/*
* TODO(crosbug.com/p/40848): These LEDs should be under control of the mec1322
* LED control unit. Remove these GPIO definitions once the LED control unit
* is functional.
*/
GPIO(CHARGE_LED_1, PIN(155), GPIO_OUT_LOW)
GPIO(CHARGE_LED_2, PIN(156), GPIO_OUT_LOW)
/* This pins are either NC, NC / pulled up, or connected to test points */
GPIO(NC_031, PIN(31), GPIO_INPUT | GPIO_PULL_UP)
GPIO(NC_047, PIN(47), GPIO_INPUT | GPIO_PULL_UP)
GPIO(NC_067, PIN(67), GPIO_INPUT | GPIO_PULL_UP)
GPIO(EC_FAN1_TTACH, PIN(105), GPIO_INPUT | GPIO_PULL_UP)
GPIO(EC_FAN1_PWM, PIN(136), GPIO_INPUT | GPIO_PULL_UP)
GPIO(ACCELGYRO3_INT_L, PIN(147), GPIO_INPUT)
GPIO(SHD_CS0_L, PIN(150), GPIO_INPUT)
GPIO(ACCELGYRO4_INT_L, PIN(157), GPIO_INPUT)
GPIO(TABLET_MODE_EC, PIN(160), GPIO_INPUT | GPIO_PULL_UP)
GPIO(ACCEL1_INT_L, PIN(161), GPIO_INPUT)
/* Alternate functions GPIO definitions */
/* GPIO162(UART_RX), GPIO165(UART_TX) */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* KB pins */
/* KB ROW - GPIO000-GPIO005 */
ALTERNATE(PIN_MASK(0, 0x3f), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB ROW - GPIO100, GPIO102-GPIO104, GPIO106-GPIO107 */
ALTERNATE(PIN_MASK(10, 0xdd), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB COL - GPIO032 */
ALTERNATE(PIN_MASK(3, 0x04), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO040, GPIO42-GPIO43 */
ALTERNATE(PIN_MASK(4, 0x0d), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO125-GPIO126 */
ALTERNATE(PIN_MASK(12, 0x60), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO142, GPIO144 */
ALTERNATE(PIN_MASK(14, 0x14), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* Keyboard Backlight PWM - GPIO34 */
ALTERNATE(PIN_MASK(3, 0x10), 1, MODULE_PWM, 0)
/* LPC pins */
/* LPC_CLK_RUN_L - GPIO014 */
ALTERNATE(PIN_MASK(1, 0x10), 1, MODULE_LPC, 0)
/* LAD[0:3] - GPIO111-GPIO114, SERIRQ - GPIO115, PCI_CLK - GPIO117 */
ALTERNATE(PIN_MASK(11, 0xbe), 1, MODULE_LPC, 0)
/* LRESET# - GPIO116 */
ALTERNATE(PIN_MASK(11, 0x40), 1, MODULE_LPC, GPIO_INT_BOTH)
/* LFRAME# - GPIO120 */
ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0)
/* SPI pins */
/* MOSI - GPIO054 */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
/* MISO - GPIO164 */
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, GPIO_PULL_UP)
/* PVT_SCLK - GPIO153 */
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)
/* I2C pins */
/* I2C0_0 CLK - GPIO015, I2C0_0 DAT - GPIO016, I2C0_1 DAT - GPIO017 */
ALTERNATE(PIN_MASK(1, 0xe0), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C{1,3} CLK / DAT - GPIO022-GPIO025*/
ALTERNATE(PIN_MASK(2, 0x3c), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C0_1 CLK - GPIO134 */
ALTERNATE(PIN_MASK(13, 0x10), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* ADC pins */
/* ADC1 - GPIO057 / PPVAR_BOOSTIN_SENSE */
ALTERNATE(PIN_MASK(5, 0x80), 1, MODULE_ADC, GPIO_ANALOG)
/* ADC3 - GPIO061 / IADP_ACMON_BMON. ADC4 - GPIO062 / PMON_PSYS */
ALTERNATE(PIN_MASK(6, 0x06), 1, MODULE_ADC, GPIO_ANALOG)
/* LED1 - GPIO155. LED2 - GPIO156 */
/* ALTERNATE(PIN_MASK(15, 0x60), 2, MODULE_POWER_LED, 0) */
/* VCC1_RST# - GPIO131 */
ALTERNATE(PIN_MASK(13, 0x02), 1, MODULE_PMU, GPIO_ODR_HIGH)
/* nRESET_OUT - GPIO121 */
ALTERNATE(PIN_MASK(12, 0x02), 1, MODULE_PMU, GPIO_ODR_HIGH)

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board/chell/led.c
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Power and battery LED control.
*/
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "led_common.h"
#include "util.h"
#define BAT_LED_ON 1
#define BAT_LED_OFF 0
const enum ec_led_id supported_led_ids[] = {
EC_LED_ID_BATTERY_LED};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
enum led_color {
LED_OFF = 0,
LED_AMBER,
LED_WHITE,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
static int bat_led_set_color(enum led_color color)
{
switch (color) {
case LED_OFF:
gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
break;
case LED_AMBER:
gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
break;
case LED_WHITE:
gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
brightness_range[EC_LED_COLOR_YELLOW] = 1;
brightness_range[EC_LED_COLOR_WHITE] = 1;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
switch (led_id) {
case EC_LED_ID_BATTERY_LED:
if (brightness[EC_LED_COLOR_WHITE] != 0)
bat_led_set_color(LED_WHITE);
else if (brightness[EC_LED_COLOR_YELLOW] != 0)
bat_led_set_color(LED_AMBER);
else
bat_led_set_color(LED_OFF);
break;
default:
break;
}
return EC_SUCCESS;
}
static void board_led_set_battery(void)
{
static int battery_ticks;
uint32_t chflags = charge_get_flags();
static int power_ticks;
static int previous_state_suspend;
battery_ticks++;
power_ticks++;
if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
/*
* Reset ticks if entering suspend so LED turns white
* as soon as possible.
*/
if (!previous_state_suspend)
power_ticks = 0;
if (charge_get_state() == PWR_STATE_CHARGE)
/* Always indicate when charging, even in suspend. */
bat_led_set_color(LED_AMBER);
else
/* Blink once every one second. */
bat_led_set_color((power_ticks & 0x4) ?
LED_WHITE : LED_OFF);
previous_state_suspend = 1;
return;
}
previous_state_suspend = 0;
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
bat_led_set_color(LED_AMBER);
break;
case PWR_STATE_DISCHARGE:
if (charge_get_percent() < 12)
bat_led_set_color(
(battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
else
bat_led_set_color(LED_OFF);
break;
case PWR_STATE_ERROR:
bat_led_set_color((battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
break;
case PWR_STATE_CHARGE_NEAR_FULL:
bat_led_set_color(LED_WHITE);
break;
case PWR_STATE_IDLE: /* External power connected in IDLE */
if (chflags & CHARGE_FLAG_FORCE_IDLE)
bat_led_set_color(
(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
else
bat_led_set_color(LED_WHITE);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
/* Called by hook task every TICK */
static void led_tick(void)
{
if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
board_led_set_battery();
}
DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);

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board/chell/lfw/gpio.inc
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/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Minimal set of GPIOs needed for LFW loader
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
/* SPI PVT chip select */
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
/* Alternate functions GPIO definition */
/* UART */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* SPI pins */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)

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board/chell/usb_pd_policy.c
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "atomic.h"
#include "charge_manager.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_mux.h"
#include "usb_pd.h"
#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
PDO_FIXED_COMM_CAP)
/* TODO: fill in correct source and sink capabilities */
const uint32_t pd_src_pdo[] = {
PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
};
const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
const uint32_t pd_snk_pdo[] = {
PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
PDO_BATT(4750, 21000, 15000),
PDO_VAR(4750, 21000, 3000),
};
const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
int pd_is_valid_input_voltage(int mv)
{
return 1;
}
void pd_transition_voltage(int idx)
{
/* No-operation: we are always 5V */
}
int pd_set_power_supply_ready(int port)
{
/* Disable charging */
gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L :
GPIO_USB_C0_CHARGE_EN_L, 1);
/* Provide VBUS */
gpio_set_level(port ? GPIO_USB_C1_5V_EN :
GPIO_USB_C0_5V_EN, 1);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
return EC_SUCCESS; /* we are ready */
}
void pd_power_supply_reset(int port)
{
/* Disable VBUS */
gpio_set_level(port ? GPIO_USB_C1_5V_EN :
GPIO_USB_C0_5V_EN, 0);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
int pd_snk_is_vbus_provided(int port)
{
return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
GPIO_USB_C0_VBUS_WAKE_L);
}
int pd_board_checks(void)
{
return EC_SUCCESS;
}
int pd_check_power_swap(int port)
{
/*
* Allow power swap as long as we are acting as a dual role device,
* otherwise assume our role is fixed (not in S0 or console command
* to fix our role).
*/
return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
}
int pd_check_data_swap(int port,
enum pd_data_role data_role)
{
/* Allow data swap if we are a UFP, otherwise don't allow */
return (data_role == PD_ROLE_UFP) ? 1 : 0;
}
int pd_check_vconn_swap(int port)
{
/* in G3, do not allow vconn swap since pp5000_A rail is off */
return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
}
void pd_execute_data_swap(int port,
enum pd_data_role data_role)
{
/* Do nothing */
}
void pd_check_pr_role(int port,
enum pd_power_role pr_role,
int flags)
{
/*
* If partner is dual-role power and dualrole toggling is on, consider
* if a power swap is necessary.
*/
if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
pd_get_dual_role(port) == PD_DRP_TOGGLE_ON) {
/*
* If we are a sink and partner is not unconstrained, then
* swap to become a source. If we are source and partner is
* unconstrained, swap to become a sink.
*/
int partner_unconstrained = flags & PD_FLAGS_PARTNER_UNCONSTR;
if ((!partner_unconstrained && pr_role == PD_ROLE_SINK) ||
(partner_unconstrained && pr_role == PD_ROLE_SOURCE))
pd_request_power_swap(port);
}
}
void pd_check_dr_role(int port,
enum pd_data_role dr_role,
int flags)
{
/* If UFP, try to switch to DFP */
if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
pd_request_data_swap(port);
}
/* ----------------- Vendor Defined Messages ------------------ */
const struct svdm_response svdm_rsp = {
.identity = NULL,
.svids = NULL,
.modes = NULL,
};
int pd_custom_vdm(int port, int cnt, uint32_t *payload,
uint32_t **rpayload)
{
int cmd = PD_VDO_CMD(payload[0]);
uint16_t dev_id = 0;
int is_rw;
/* make sure we have some payload */
if (cnt == 0)
return 0;
switch (cmd) {
case VDO_CMD_VERSION:
/* guarantee last byte of payload is null character */
*(payload + cnt - 1) = 0;
CPRINTF("version: %s\n", (char *)(payload+1));
break;
case VDO_CMD_READ_INFO:
case VDO_CMD_SEND_INFO:
/* copy hash */
if (cnt == 7) {
dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
is_rw = VDO_INFO_IS_RW(payload[6]);
CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
HW_DEV_ID_MAJ(dev_id),
HW_DEV_ID_MIN(dev_id),
VDO_INFO_SW_DBG_VER(payload[6]),
is_rw);
} else if (cnt == 6) {
/* really old devices don't have last byte */
pd_dev_store_rw_hash(port, dev_id, payload + 1,
EC_IMAGE_UNKNOWN);
}
break;
case VDO_CMD_CURRENT:
CPRINTF("Current: %dmA\n", payload[1]);
break;
case VDO_CMD_FLIP:
usb_mux_flip(port);
break;
#ifdef CONFIG_USB_PD_LOGGING
case VDO_CMD_GET_LOG:
pd_log_recv_vdm(port, cnt, payload);
break;
#endif /* CONFIG_USB_PD_LOGGING */
}
return 0;
}
#ifdef CONFIG_USB_PD_ALT_MODE_DFP
static int dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
/* DP Status VDM as returned by UFP */
static uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
static void svdm_safe_dp_mode(int port)
{
/* make DP interface safe until configure */
dp_flags[port] = 0;
dp_status[port] = 0;
usb_mux_set(port, USB_PD_MUX_NONE,
USB_SWITCH_CONNECT, pd_get_polarity(port));
}
static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
{
/* Only enter mode if device is DFP_D capable */
if (mode_caps & MODE_DP_SNK) {
svdm_safe_dp_mode(port);
return 0;
}
return -1;
}
static int svdm_dp_status(int port, uint32_t *payload)
{
int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
CMD_DP_STATUS | VDO_OPOS(opos));
payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */
0, /* HPD level ... not applicable */
0, /* exit DP? ... no */
0, /* usb mode? ... no */
0, /* multi-function ... no */
(!!(dp_flags[port] & DP_FLAGS_DP_ON)),
0, /* power low? ... no */
(!!(dp_flags[port] & DP_FLAGS_DP_ON)));
return 2;
};
static int svdm_dp_config(int port, uint32_t *payload)
{
int opos = pd_alt_mode(port, TCPC_TX_SOP, USB_SID_DISPLAYPORT);
int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
if (!pin_mode)
return 0;
usb_mux_set(port, mf_pref ? USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED,
USB_SWITCH_CONNECT, pd_get_polarity(port));
payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
CMD_DP_CONFIG | VDO_OPOS(opos));
payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
1, /* DPv1.3 signaling */
2); /* UFP connected */
return 2;
};
#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
__override void svdm_dp_post_config(int port)
{
dp_flags[port] |= DP_FLAGS_DP_ON;
if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
return;
gpio_set_level(PORT_TO_HPD(port), 1);
/* set the minimum time delay (2ms) for the next HPD IRQ */
svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
}
__override int svdm_dp_attention(int port, uint32_t *payload)
{
int cur_lvl;
int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
enum gpio_signal hpd = PORT_TO_HPD(port);
cur_lvl = gpio_get_level(hpd);
dp_status[port] = payload[1];
/* Its initial DP status message prior to config */
if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
if (lvl)
dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
return 1;
}
if (irq & cur_lvl) {
uint64_t now = get_time().val;
/* wait for the minimum spacing between IRQ_HPD if needed */
if (now < svdm_hpd_deadline[port])
usleep(svdm_hpd_deadline[port] - now);
/* generate IRQ_HPD pulse */
gpio_set_level(hpd, 0);
usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
gpio_set_level(hpd, 1);
/* set the minimum time delay (2ms) for the next HPD IRQ */
svdm_hpd_deadline[port] = get_time().val +
HPD_USTREAM_DEBOUNCE_LVL;
} else if (irq & !cur_lvl) {
CPRINTF("ERR:HPD:IRQ&LOW\n");
return 0; /* nak */
} else {
gpio_set_level(hpd, lvl);
/* set the minimum time delay (2ms) for the next HPD IRQ */
svdm_hpd_deadline[port] = get_time().val +
HPD_USTREAM_DEBOUNCE_LVL;
}
/* ack */
return 1;
}
static void svdm_exit_dp_mode(int port)
{
svdm_safe_dp_mode(port);
gpio_set_level(PORT_TO_HPD(port), 0);
}
static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
{
/* Always enter GFU mode */
return 0;
}
static void svdm_exit_gfu_mode(int port)
{
}
static int svdm_gfu_status(int port, uint32_t *payload)
{
/*
* This is called after enter mode is successful, send unstructured
* VDM to read info.
*/
pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
return 0;
}
static int svdm_gfu_config(int port, uint32_t *payload)
{
return 0;
}
static int svdm_gfu_attention(int port, uint32_t *payload)
{
return 0;
}
const struct svdm_amode_fx supported_modes[] = {
{
.svid = USB_SID_DISPLAYPORT,
.enter = &svdm_enter_dp_mode,
.status = &svdm_dp_status,
.config = &svdm_dp_config,
.post_config = &svdm_dp_post_config,
.attention = &svdm_dp_attention,
.exit = &svdm_exit_dp_mode,
},
{
.svid = USB_VID_GOOGLE,
.enter = &svdm_enter_gfu_mode,
.status = &svdm_gfu_status,
.config = &svdm_gfu_config,
.attention = &svdm_gfu_attention,
.exit = &svdm_exit_gfu_mode,
}
};
const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
#endif /* CONFIG_USB_PD_ALT_MODE_DFP */

1
board/chell_pd
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@ -1 +0,0 @@
glados_pd/

230
board/glados/battery.c
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@ -1,230 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "charge_state.h"
#include "console.h"
#include "ec_commands.h"
#include "i2c.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define PARAM_CUT_OFF_LOW 0x10
#define PARAM_CUT_OFF_HIGH 0x00
/* Battery info for BQ40Z55 */
static const struct battery_info info = {
.voltage_max = 8700, /* mV */
.voltage_normal = 7600,
.voltage_min = 6000,
.precharge_current = 256, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 46,
.charging_min_c = 0,
.charging_max_c = 60,
.discharging_min_c = 0,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
int rv;
uint8_t buf[3];
/* Ship mode command must be sent twice to take effect */
buf[0] = SB_MANUFACTURER_ACCESS & 0xff;
buf[1] = PARAM_CUT_OFF_LOW;
buf[2] = PARAM_CUT_OFF_HIGH;
i2c_lock(I2C_PORT_BATTERY, 1);
rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
buf, 3, NULL, 0, I2C_XFER_SINGLE);
rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
buf, 3, NULL, 0, I2C_XFER_SINGLE);
i2c_lock(I2C_PORT_BATTERY, 0);
return rv;
}
#ifdef CONFIG_CHARGER_PROFILE_OVERRIDE
static int fast_charging_allowed = 1;
/*
* This can override the smart battery's charging profile. To make a change,
* modify one or more of requested_voltage, requested_current, or state.
* Leave everything else unchanged.
*
* Return the next poll period in usec, or zero to use the default (which is
* state dependent).
*/
int charger_profile_override(struct charge_state_data *curr)
{
/* temp in 0.1 deg C */
int temp_c = curr->batt.temperature - 2731;
/* keep track of last temperature range for hysteresis */
static enum {
TEMP_RANGE_1,
TEMP_RANGE_2,
TEMP_RANGE_3,
TEMP_RANGE_4,
TEMP_RANGE_5,
} temp_range = TEMP_RANGE_3;
/* keep track of last voltage range for hysteresis */
static enum {
VOLTAGE_RANGE_LOW,
VOLTAGE_RANGE_HIGH,
} voltage_range = VOLTAGE_RANGE_LOW;
/* Current and previous battery voltage */
int batt_voltage;
static int prev_batt_voltage;
/*
* Determine temperature range. The five ranges are:
* < 10C
* 10-15C
* 15-23C
* 23-45C
* > 45C
*
* Add 0.2 degrees of hysteresis.
* If temp reading was bad, use last range.
*/
if (!(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE)) {
if (temp_c < 99)
temp_range = TEMP_RANGE_1;
else if (temp_c > 101 && temp_c < 149)
temp_range = TEMP_RANGE_2;
else if (temp_c > 151 && temp_c < 229)
temp_range = TEMP_RANGE_3;
else if (temp_c > 231 && temp_c < 449)
temp_range = TEMP_RANGE_4;
else if (temp_c > 451)
temp_range = TEMP_RANGE_5;
}
/*
* If battery voltage reading is bad, use the last reading. Otherwise,
* determine voltage range with hysteresis.
*/
if (curr->batt.flags & BATT_FLAG_BAD_VOLTAGE) {
batt_voltage = prev_batt_voltage;
} else {
batt_voltage = prev_batt_voltage = curr->batt.voltage;
if (batt_voltage < 8200)
voltage_range = VOLTAGE_RANGE_LOW;
else if (batt_voltage > 8300)
voltage_range = VOLTAGE_RANGE_HIGH;
}
/*
* If we are not charging or we aren't using fast charging profiles,
* then do not override desired current and voltage.
*/
if (curr->state != ST_CHARGE || !fast_charging_allowed)
return 0;
/*
* Okay, impose our custom will:
* When battery is 0-10C:
* CC at 486mA @ 8.7V
* CV at 8.7V
*
* When battery is <15C:
* CC at 1458mA @ 8.7V
* CV at 8.7V
*
* When battery is <23C:
* CC at 3402mA until 8.3V @ 8.7V
* CC at 2430mA @ 8.7V
* CV at 8.7V
*
* When battery is <45C:
* CC at 4860mA until 8.3V @ 8.7V
* CC at 2430mA @ 8.7V
* CV at 8.7V until current drops to 450mA
*
* When battery is >45C:
* CC at 2430mA @ 8.3V
* CV at 8.3V (when battery is hot we don't go to fully charged)
*/
switch (temp_range) {
case TEMP_RANGE_1:
curr->requested_current = 486;
curr->requested_voltage = 8700;
break;
case TEMP_RANGE_2:
curr->requested_current = 1458;
curr->requested_voltage = 8700;
break;
case TEMP_RANGE_3:
curr->requested_voltage = 8700;
if (voltage_range == VOLTAGE_RANGE_HIGH)
curr->requested_current = 2430;
else
curr->requested_current = 3402;
break;
case TEMP_RANGE_4:
curr->requested_voltage = 8700;
if (voltage_range == VOLTAGE_RANGE_HIGH)
curr->requested_current = 2430;
else
curr->requested_current = 4860;
break;
case TEMP_RANGE_5:
curr->requested_current = 2430;
curr->requested_voltage = 8300;
break;
}
return 0;
}
/* Customs options controllable by host command. */
#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
enum ec_status charger_profile_override_get_param(uint32_t param,
uint32_t *value)
{
if (param == PARAM_FASTCHARGE) {
*value = fast_charging_allowed;
return EC_RES_SUCCESS;
}
return EC_RES_INVALID_PARAM;
}
enum ec_status charger_profile_override_set_param(uint32_t param,
uint32_t value)
{
if (param == PARAM_FASTCHARGE) {
fast_charging_allowed = value;
return EC_RES_SUCCESS;
}
return EC_RES_INVALID_PARAM;
}
static int command_fastcharge(int argc, char **argv)
{
if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
return EC_ERROR_PARAM1;
ccprintf("fastcharge %s\n", fast_charging_allowed ? "on" : "off");
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
"[on|off]",
"Get or set fast charging profile");
#endif /* CONFIG_CHARGER_PROFILE_OVERRIDE */

521
board/glados/board.c
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@ -1,521 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Glados board-specific configuration */
#include "adc_chip.h"
#include "als.h"
#include "bd99992gw.h"
#include "button.h"
#include "charge_manager.h"
#include "charge_state.h"
#include "charger.h"
#include "chipset.h"
#include "console.h"
#include "driver/als_opt3001.h"
#include "driver/accel_kionix.h"
#include "driver/accel_kx022.h"
#include "driver/accelgyro_bmi_common.h"
#include "driver/tcpm/tcpci.h"
#include "extpower.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "i2c.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "math_util.h"
#include "motion_sense.h"
#include "motion_lid.h"
#include "pi3usb9281.h"
#include "power.h"
#include "power_button.h"
#include "spi.h"
#include "switch.h"
#include "system.h"
#include "task.h"
#include "temp_sensor.h"
#include "timer.h"
#include "uart.h"
#include "usb_charge.h"
#include "usb_mux.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "util.h"
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
#define I2C_ADDR_BD99992_FLAGS 0x30
/* Exchange status with PD MCU. */
static void pd_mcu_interrupt(enum gpio_signal signal)
{
#ifdef HAS_TASK_PDCMD
/* Exchange status with PD MCU to determine interrupt cause */
host_command_pd_send_status(0);
#endif
}
void vbus0_evt(enum gpio_signal signal)
{
/* VBUS present GPIO is inverted */
usb_charger_vbus_change(0, !gpio_get_level(signal));
task_wake(TASK_ID_PD_C0);
}
void vbus1_evt(enum gpio_signal signal)
{
/* VBUS present GPIO is inverted */
usb_charger_vbus_change(1, !gpio_get_level(signal));
task_wake(TASK_ID_PD_C1);
}
void usb0_evt(enum gpio_signal signal)
{
task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
}
void usb1_evt(enum gpio_signal signal)
{
task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
}
/*
* enable_input_devices() is called by the tablet_mode ISR, but changes the
* state of GPIOs, so its definition must reside after including gpio_list.
*/
static void enable_input_devices(void);
DECLARE_DEFERRED(enable_input_devices);
void tablet_mode_interrupt(enum gpio_signal signal)
{
hook_call_deferred(&enable_input_devices_data, 0);
}
#include "gpio_list.h"
/* ADC channels */
const struct adc_t adc_channels[] = {
/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
[ADC_VBUS] = {"VBUS", 30000, 1024, 0, 1},
/* Adapter current output or battery discharging current */
[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
/* System current consumption */
[ADC_PSYS] = {"PSYS", 1, 1, 0, 4},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
const struct i2c_port_t i2c_ports[] = {
{"pmic", MEC1322_I2C0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
{"muxes", MEC1322_I2C0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
{"pd_mcu", MEC1322_I2C1, 500, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
{"sensors", MEC1322_I2C2, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA },
{"batt", MEC1322_I2C3, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA },
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
{
.bus_type = EC_BUS_TYPE_I2C,
.i2c_info = {
.port = I2C_PORT_TCPC,
.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
},
.drv = &tcpci_tcpm_drv,
},
{
.bus_type = EC_BUS_TYPE_I2C,
.i2c_info = {
.port = I2C_PORT_TCPC,
.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1,
},
.drv = &tcpci_tcpm_drv,
},
};
/* SPI devices */
const struct spi_device_t spi_devices[] = {
{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
const enum gpio_signal hibernate_wake_pins[] = {
GPIO_AC_PRESENT,
GPIO_LID_OPEN,
GPIO_POWER_BUTTON_L,
};
const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
struct pi3usb9281_config pi3usb9281_chips[] = {
{
.i2c_port = I2C_PORT_USB_CHARGER_1,
.mux_lock = NULL,
},
{
.i2c_port = I2C_PORT_USB_CHARGER_2,
.mux_lock = NULL,
},
};
BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
{
.usb_port = 0,
.i2c_port = I2C_PORT_USB_MUX,
.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
.driver = &pi3usb3x532_usb_mux_driver,
},
{
.usb_port = 1,
.i2c_port = I2C_PORT_USB_MUX,
.i2c_addr_flags = 0x10,
.driver = &ps8740_usb_mux_driver,
}
};
/**
* Reset PD MCU
*/
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_PD_RST_L, 0);
usleep(100);
gpio_set_level(GPIO_PD_RST_L, 1);
}
const struct temp_sensor_t temp_sensors[] = {
{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0, 4},
/* These BD99992GW temp sensors are only readable in S0 */
{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM0, 4},
{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM1, 4},
{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM2, 4},
{"Wifi", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
BD99992GW_ADC_CHANNEL_SYSTHERM3, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/* ALS instances. Must be in same order as enum als_id. */
struct als_t als[] = {
{"TI", opt3001_init, opt3001_read_lux, 5},
};
BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
static void board_pmic_init(void)
{
/* No need to re-init PMIC since settings are sticky across sysjump */
if (system_jumped_late())
return;
/* Set CSDECAYEN / VCCIO decays to 0V at assertion of SLP_S0# */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x4a);
/*
* Set V100ACNT / V1.00A Control Register:
* Nominal output = 1.0V.
*/
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x1a);
/*
* Set V085ACNT / V0.85A Control Register:
* Lower power mode = 0.7V.
* Nominal output = 1.0V.
*/
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
/* VRMODECTRL - enable low-power mode for VCCIO and V0.85A */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3b, 0x18);
}
DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_DEFAULT);
/* Initialize board. */
static void board_init(void)
{
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
/* Enable pericom BC1.2 interrupts */
gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
/* Enable tablet mode interrupt for input device enable */
gpio_enable_interrupt(GPIO_TABLET_MODE_L);
/* Provide AC status to the PCH */
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/**
* Buffer the AC present GPIO to the PCH.
*/
static void board_extpower(void)
{
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
/**
* Set active charge port -- only one port can be active at a time.
*
* @param charge_port Charge port to enable.
*
* Returns EC_SUCCESS if charge port is accepted and made active,
* EC_ERROR_* otherwise.
*/
int board_set_active_charge_port(int charge_port)
{
/* charge port is a realy physical port */
int is_real_port = (charge_port >= 0 &&
charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
/* check if we are source vbus on that port */
int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
GPIO_USB_C1_5V_EN);
if (is_real_port && source) {
CPRINTS("Skip enable p%d", charge_port);
return EC_ERROR_INVAL;
}
CPRINTS("New chg p%d", charge_port);
if (charge_port == CHARGE_PORT_NONE) {
/* Disable both ports */
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
} else {
/* Make sure non-charging port is disabled */
gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L :
GPIO_USB_C1_CHARGE_EN_L, 1);
/* Enable charging port */
gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L :
GPIO_USB_C0_CHARGE_EN_L, 0);
}
return EC_SUCCESS;
}
/**
* Set the charge limit based upon desired maximum.
*
* @param port Port number.
* @param supplier Charge supplier type.
* @param charge_ma Desired charge limit (mA).
* @param charge_mv Negotiated charge voltage (mV).
*/
void board_set_charge_limit(int port, int supplier, int charge_ma,
int max_ma, int charge_mv)
{
charge_set_input_current_limit(MAX(charge_ma,
CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
}
/* Enable or disable input devices, based upon chipset state and tablet mode */
static void enable_input_devices(void)
{
int kb_enable = 1;
int tp_enable = 1;
/* Disable both TP and KB in tablet mode */
if (!gpio_get_level(GPIO_TABLET_MODE_L))
kb_enable = tp_enable = 0;
/* Disable TP if chipset is off */
else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
tp_enable = 0;
keyboard_scan_enable(kb_enable, KB_SCAN_DISABLE_LID_ANGLE);
gpio_set_level(GPIO_ENABLE_TOUCHPAD, tp_enable);
}
/* Called on AP S5 -> S3 transition */
static void board_chipset_startup(void)
{
gpio_set_level(GPIO_USB1_ENABLE, 1);
gpio_set_level(GPIO_USB2_ENABLE, 1);
hook_call_deferred(&enable_input_devices_data, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
/* Called on AP S3 -> S5 transition */
static void board_chipset_shutdown(void)
{
gpio_set_level(GPIO_USB1_ENABLE, 0);
gpio_set_level(GPIO_USB2_ENABLE, 0);
hook_call_deferred(&enable_input_devices_data, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
/* Called on AP S3 -> S0 transition */
static void board_chipset_resume(void)
{
gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 1);
gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 1);
/*
* Now that we have enabled the rail to the sensors, let's give enough
* time for the sensors to boot up. Without this delay, the very first
* i2c transactions always fail because the sensors aren't ready yet.
* In testing, a 2ms delay seemed to be reliable, but we'll delay for
* 3ms just to be safe.
*
* Additionally, this hook needs to be run before the motion sense hook
* tries to initialize the sensors.
*/
msleep(3);
}
DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume,
MOTION_SENSE_HOOK_PRIO-1);
/* Called on AP S0 -> S3 transition */
static void board_chipset_suspend(void)
{
gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 0);
gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
void board_hibernate_late(void)
{
/* Turn off LEDs in hibernate */
gpio_set_level(GPIO_CHARGE_LED_1, 0);
gpio_set_level(GPIO_CHARGE_LED_2, 0);
/*
* Set PD wake low so that it toggles high to generate a wake
* event once we leave hibernate.
*/
gpio_set_level(GPIO_USB_PD_WAKE, 0);
}
/* Any glados boards post version 2 should have ROP_LDO_EN stuffed. */
#define BOARD_MIN_ID_LOD_EN 2
/* Make the pmic re-sequence the power rails under these conditions. */
#define PMIC_RESET_FLAGS \
(EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD)
static void board_handle_reboot(void)
{
int flags;
if (system_jumped_late())
return;
if (system_get_board_version() < BOARD_MIN_ID_LOD_EN)
return;
/* Interrogate current reset flags from previous reboot. */
flags = system_get_reset_flags();
if (!(flags & PMIC_RESET_FLAGS))
return;
/* Preserve AP off request. */
if (flags & EC_RESET_FLAG_AP_OFF)
chip_save_reset_flags(EC_RESET_FLAG_AP_OFF);
ccprintf("Restarting system with PMIC.\n");
/* Flush console */
cflush();
/* Bring down all rails but RTC rail (including EC power). */
gpio_set_flags(GPIO_BATLOW_L_PMIC_LDO_EN, GPIO_OUT_HIGH);
while (1)
; /* wait here */
}
DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
#ifdef HAS_TASK_MOTIONSENSE
/* Motion sensors */
/* Mutexes */
static struct mutex g_lid_mutex;
static struct mutex g_base_mutex;
static struct kionix_accel_data g_kx022_data;
static struct bmi_drv_data_t g_bmi160_data;
struct motion_sensor_t motion_sensors[] = {
/*
* Note: bmi160: supports accelerometer and gyro sensor
* Requirement: accelerometer sensor must init before gyro sensor
* DO NOT change the order of the following table.
*/
[BASE_ACCEL] = {
.name = "Base Accel",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_BMI160,
.type = MOTIONSENSE_TYPE_ACCEL,
.location = MOTIONSENSE_LOC_BASE,
.drv = &bmi160_drv,
.mutex = &g_base_mutex,
.drv_data = &g_bmi160_data,
.port = I2C_PORT_ACCEL,
.addr = BMI160_ADDR0,
.rot_standard_ref = NULL, /* Identity matrix. */
.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs */
.min_frequency = BMI_ACCEL_MIN_FREQ,
.max_frequency = BMI_ACCEL_MAX_FREQ,
.config = {
/* EC use accel for angle detection */
[SENSOR_CONFIG_EC_S0] = {
.odr = 10000 | ROUND_UP_FLAG,
.ec_rate = 100 * MSEC,
},
},
},
[BASE_GYRO] = {
.name = "Base Gyro",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_BMI160,
.type = MOTIONSENSE_TYPE_GYRO,
.location = MOTIONSENSE_LOC_BASE,
.drv = &bmi160_drv,
.mutex = &g_base_mutex,
.drv_data = &g_bmi160_data,
.port = I2C_PORT_ACCEL,
.addr = BMI160_ADDR0,
.default_range = 1000, /* dps */
.rot_standard_ref = NULL, /* Identity Matrix. */
.min_frequency = BMI_GYRO_MIN_FREQ,
.max_frequency = BMI_GYRO_MAX_FREQ,
},
[LID_ACCEL] = {
.name = "Lid Accel",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_KX022,
.type = MOTIONSENSE_TYPE_ACCEL,
.location = MOTIONSENSE_LOC_LID,
.drv = &kionix_accel_drv,
.mutex = &g_lid_mutex,
.drv_data = &g_kx022_data,
.port = I2C_PORT_ACCEL,
.addr = KX022_ADDR1,
.rot_standard_ref = NULL, /* Identity matrix. */
.default_range = 2, /* g, enough for laptop. */
.min_frequency = KX022_ACCEL_MIN_FREQ,
.max_frequency = KX022_ACCEL_MAX_FREQ,
.config = {
/* EC use accel for angle detection */
[SENSOR_CONFIG_EC_S0] = {
.odr = 10000 | ROUND_UP_FLAG,
.ec_rate = 100 * MSEC,
},
},
},
};
const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
#endif /* defined(HAS_TASK_MOTIONSENSE) */

220
board/glados/board.h
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@ -1,220 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Glados board configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/*
* Allow dangerous commands.
* TODO(shawnn): Remove this config before production.
*/
#define CONFIG_SYSTEM_UNLOCKED
/* Optional features */
#define CONFIG_ACCELGYRO_BMI160
#define CONFIG_ACCEL_KX022
#define CONFIG_ADC
#define CONFIG_ALS_OPT3001
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_VERSION_GPIO
#define CONFIG_CHARGE_MANAGER
#define CONFIG_CHARGE_RAMP_HW
#define CONFIG_CHARGER
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_ISL9237
#define CONFIG_CHARGER_ILIM_PIN_DISABLED
#define CONFIG_CHARGER_INPUT_CURRENT 512
#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
#define CONFIG_CHARGER_PROFILE_OVERRIDE
#define CONFIG_CHARGER_SENSE_RESISTOR 10
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
#define CONFIG_CHIPSET_SKYLAKE
#define CONFIG_CHIPSET_RESET_HOOK
#define CONFIG_CLOCK_CRYSTAL
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_HOSTCMD_PD
#define CONFIG_HOSTCMD_PD_PANIC
#define CONFIG_I2C
#define CONFIG_I2C_MASTER
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_COMMON
#define CONFIG_LID_ANGLE
#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
#define CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LTO
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
/* All data won't fit in data RAM. So, moving boundary slightly. */
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE (108 * 1024)
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* We're space constrained on GLaDOS, so reduce the UART TX buffer size. */
#undef CONFIG_UART_TX_BUF_SIZE
#define CONFIG_UART_TX_BUF_SIZE 512
#define CONFIG_USB_CHARGER
#define CONFIG_USB_MUX_PI3USB30532
#define CONFIG_USB_MUX_PS8740
#define CONFIG_USB_POWER_DELIVERY
#define CONFIG_USB_PD_TCPMV1
#define CONFIG_USB_PD_ALT_MODE
#define CONFIG_USB_PD_ALT_MODE_DFP
#define CONFIG_USB_PD_DP_HPD_GPIO
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_LOGGING
#define CONFIG_USB_PD_PORT_MAX_COUNT 2
#define CONFIG_USB_PD_TCPM_TCPCI
#define CONFIG_USB_PD_TRY_SRC
#define CONFIG_USB_PD_VBUS_DETECT_GPIO
#define CONFIG_BC12_DETECT_PI3USB9281
#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
#define CONFIG_USBC_SS_MUX
#define CONFIG_USBC_SS_MUX_DFP_ONLY
#define CONFIG_USBC_VCONN
#define CONFIG_USBC_VCONN_SWAP
#define CONFIG_VBOOT_HASH
#define CONFIG_VOLUME_BUTTONS
#define CONFIG_SPI_FLASH_PORT 1
#define CONFIG_SPI_FLASH
#define CONFIG_FLASH_SIZE 524288
#define CONFIG_SPI_FLASH_W25X40
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_BD99992GW
#define CONFIG_THERMISTOR_NCP15WB
#define CONFIG_DPTF
/*
* Enable 1 slot of secure temporary storage to support
* suspend/resume with read/write memory training.
*/
#define CONFIG_VSTORE
#define CONFIG_VSTORE_SLOT_COUNT 1
#define CONFIG_WATCHDOG_HELP
#define CONFIG_WIRELESS
#define CONFIG_WIRELESS_SUSPEND \
(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
/* LED signals */
#define GPIO_BAT_LED_RED GPIO_CHARGE_LED_1
#define GPIO_BAT_LED_GREEN GPIO_CHARGE_LED_2
/* I2C ports */
#define I2C_PORT_PMIC MEC1322_I2C0_0
#define I2C_PORT_USB_CHARGER_1 MEC1322_I2C0_1
#define I2C_PORT_USB_MUX MEC1322_I2C0_1
#define I2C_PORT_USB_CHARGER_2 MEC1322_I2C0_0
#define I2C_PORT_PD_MCU MEC1322_I2C1
#define I2C_PORT_TCPC MEC1322_I2C1
#define I2C_PORT_ALS MEC1322_I2C2
#define I2C_PORT_ACCEL MEC1322_I2C2
#define I2C_PORT_BATTERY MEC1322_I2C3
#define I2C_PORT_CHARGER MEC1322_I2C3
/* Thermal sensors read through PMIC ADC interface */
#define I2C_PORT_THERMAL I2C_PORT_PMIC
/* Ambient Light Sensor address */
#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
/* Modules we want to exclude */
#undef CONFIG_CMD_HASH
#undef CONFIG_CMD_TEMP_SENSOR
#undef CONFIG_CMD_TIMERINFO
#undef CONFIG_CONSOLE_CMDHELP
#undef CONFIG_CMD_ADC
#undef CONFIG_CMD_ACCELSPOOF
#undef CONFIG_CMD_FASTCHARGE
#undef CONFIG_CMD_GETTIME
#undef CONFIG_CMD_MEM
#ifdef SECTION_IS_RO
#undef CONFIG_CMD_BATTFAKE
#undef CONFIG_CMD_MD
#undef CONFIG_CMD_POWERINDEBUG
#endif
#ifndef __ASSEMBLER__
#include "gpio_signal.h"
#include "registers.h"
/* ADC signal */
enum adc_channel {
ADC_VBUS,
ADC_AMON_BMON,
ADC_PSYS,
/* Number of ADC channels */
ADC_CH_COUNT
};
enum temp_sensor_id {
TEMP_SENSOR_BATTERY,
/* These temp sensors are only readable in S0 */
TEMP_SENSOR_AMBIENT,
TEMP_SENSOR_CHARGER,
TEMP_SENSOR_DRAM,
TEMP_SENSOR_WIFI,
TEMP_SENSOR_COUNT
};
enum sensor_id {
BASE_ACCEL,
BASE_GYRO,
LID_ACCEL,
SENSOR_COUNT,
};
/* Light sensors */
enum als_id {
ALS_OPT3001 = 0,
ALS_COUNT
};
/* TODO: determine the following board specific type-C power constants */
/*
* delay to turn on the power supply max is ~16ms.
* delay to turn off the power supply max is about ~180ms.
*/
#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
/* delay to turn on/off vconn */
#define PD_VCONN_SWAP_DELAY 5000 /* us */
/* Define typical operating power and max power */
#define PD_OPERATING_POWER_MW 15000
#define PD_MAX_POWER_MW 45000
#define PD_MAX_CURRENT_MA 3000
/* Try to negotiate to 20V since i2c noise problems should be fixed. */
#define PD_MAX_VOLTAGE_MV 20000
/* Reset PD MCU */
void board_reset_pd_mcu(void);
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

15
board/glados/build.mk
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@ -1,15 +0,0 @@
# -*- makefile -*-
# Copyright 2015 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is SMSC MEC1322 / external SPI is 512KB / external clock is crystal
CHIP:=mec1322
CHIP_SPI_SIZE_KB:=512
board-y=board.o led.o
board-$(CONFIG_BATTERY_SMART)+=battery.o
board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o

24
board/glados/ec.tasklist
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@ -1,24 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/*
* See CONFIG_TASK_LIST in config.h for details.
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(ALS, als_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)

185
board/glados/gpio.inc
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@ -1,185 +0,0 @@
/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(LID_OPEN, PIN(27), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
GPIO_INT(AC_PRESENT, PIN(30), GPIO_INT_BOTH, extpower_interrupt)
GPIO_INT(WP_L, PIN(33), GPIO_INT_BOTH, switch_interrupt)
/* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */
GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt)
/* RSMRST from PMIC */
GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(VOLUME_UP_L, PIN(31), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
GPIO_INT(VOLUME_DOWN_L, PIN(47), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
GPIO_INT(PMIC_INT_L, PIN(50), GPIO_INT_FALLING, power_signal_interrupt)
GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_FALLING | GPIO_PULL_UP, pd_mcu_interrupt)
GPIO_INT(USB_C0_VBUS_WAKE_L,PIN(152), GPIO_INT_BOTH, vbus0_evt)
GPIO_INT(USB_C1_VBUS_WAKE_L,PIN(123), GPIO_INT_BOTH, vbus1_evt)
GPIO_INT(USB_C0_BC12_INT_L, PIN(124), GPIO_INT_FALLING, usb0_evt)
GPIO_INT(USB_C1_BC12_INT_L, PIN(145), GPIO_INT_FALLING, usb1_evt)
GPIO_INT(TABLET_MODE_L, PIN(160), GPIO_INT_BOTH | GPIO_PULL_UP, tablet_mode_interrupt)
/* Delayed PWR_OK from PMIC */
GPIO_INT(PMIC_DPWROK, PIN(133), GPIO_INT_BOTH, power_signal_interrupt)
/* UART input */
GPIO_INT(UART0_RX, PIN(162), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
/*
* This pulldown should be removed and SLP_S0 should be enabled as a power
* signal interrupt in future hardware followers. The signal is pulled up in
* the SoC when the primary rails are on and/or ramping.
* In order to not get interrupt storms there should be external logic
* which makes this a true binary signal into the EC.
*/
GPIO(PCH_SLP_S0_L, PIN(211), GPIO_INPUT | GPIO_PULL_DOWN)
GPIO(PD_RST_L, PIN(130), GPIO_ODR_HIGH)
GPIO(USB2_OTG_ID, PIN(13), GPIO_ODR_LOW)
/* I2C pins - these will be reconfigured for alternate function below */
GPIO(I2C0_0_SCL, PIN(15), GPIO_INPUT)
GPIO(I2C0_0_SDA, PIN(16), GPIO_INPUT)
GPIO(I2C0_1_SCL, PIN(134), GPIO_INPUT)
GPIO(I2C0_1_SDA, PIN(17), GPIO_INPUT)
GPIO(I2C1_SCL, PIN(22), GPIO_INPUT)
GPIO(I2C1_SDA, PIN(23), GPIO_INPUT)
GPIO(I2C2_SCL, PIN(20), GPIO_INPUT)
GPIO(I2C2_SDA, PIN(21), GPIO_INPUT)
GPIO(I2C3_SCL, PIN(24), GPIO_INPUT)
GPIO(I2C3_SDA, PIN(25), GPIO_INPUT)
GPIO(PCH_SCI_L, PIN(26), GPIO_ODR_HIGH)
/* KB BL PWM, only connected to TP */
GPIO(PWM_KBLIGHT, PIN(34), GPIO_OUT_LOW)
GPIO(USB1_ENABLE, PIN(36), GPIO_OUT_LOW)
GPIO(USB2_ENABLE, PIN(67), GPIO_OUT_LOW)
GPIO(ENTERING_RW, PIN(41), GPIO_OUT_LOW)
GPIO(PCH_SMI_L, PIN(44), GPIO_ODR_HIGH)
GPIO(PCH_PWRBTN_L, PIN(45), GPIO_OUTPUT)
GPIO(USB_C0_DP_HPD, PIN(46), GPIO_OUT_LOW)
GPIO(USB_C1_DP_HPD, PIN(51), GPIO_OUT_LOW)
GPIO(CPU_PROCHOT, PIN(52), GPIO_OUT_LOW)
GPIO(ENABLE_TOUCHPAD, PIN(53), GPIO_OUT_LOW)
GPIO(BAT_PRESENT_L, PIN(56), GPIO_INPUT)
GPIO(USB_PD_WAKE, PIN(60), GPIO_OUT_HIGH)
/* When asserted, ME does not lock security descriptor */
GPIO(PCH_SEC_DISABLE_L, PIN(65), GPIO_OUT_HIGH)
GPIO(PCH_WAKE_L, PIN(66), GPIO_ODR_HIGH)
GPIO(EC_FAN1_TTACH, PIN(105), GPIO_INPUT | GPIO_PULL_UP)
/* Fan PWM output - NC / testing only */
GPIO(EC_FAN1_PWM, PIN(136), GPIO_OUT_LOW)
GPIO(PCH_ACOK, PIN(110), GPIO_OUT_LOW)
/* Interrupts from accelerometer / gyro -- not yet implemented */
GPIO(ACCEL1_INT, PIN(161), GPIO_INPUT)
GPIO(ACCEL2_INT, PIN(127), GPIO_INPUT)
GPIO(ACCEL3_INT, PIN(147), GPIO_INPUT)
GPIO(WLAN_OFF_L, PIN(132), GPIO_OUT_LOW)
/* RCIN# line to PCH for 8042 emulation */
GPIO(PCH_RCIN_L, PIN(135), GPIO_ODR_HIGH)
GPIO(USB2_OTG_VBUSSENSE, PIN(140), GPIO_OUT_LOW)
GPIO(PCH_RSMRST_L, PIN(143), GPIO_OUT_LOW)
/* prochot input from devices */
GPIO(PLATFORM_EC_PROCHOT, PIN(151), GPIO_INPUT | GPIO_PULL_UP)
GPIO(USB_C0_5V_EN, PIN(154), GPIO_OUT_LOW)
GPIO(USB_C1_5V_EN, PIN(204), GPIO_OUT_LOW)
GPIO(USB_C0_CHARGE_EN_L, PIN(64), GPIO_OUT_LOW)
GPIO(PP1800_DX_SENSOR_EN, PIN(11), GPIO_OUT_LOW)
/* From lid sensor */
GPIO(ENABLE_BACKLIGHT, PIN(202), GPIO_OUT_LOW)
GPIO(PP3300_WLAN_EN, PIN(203), GPIO_OUT_LOW)
GPIO(BOARD_VERSION1, PIN(6), GPIO_INPUT)
GPIO(BOARD_VERSION2, PIN(7), GPIO_INPUT)
GPIO(BOARD_VERSION3, PIN(10), GPIO_INPUT)
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
GPIO(SYS_RESET_L, PIN(121), GPIO_ODR_HIGH)
/*
* TODO(crosbug.com/p/40848): These LEDs should be under control of the mec1322
* LED control unit. Remove these GPIO definitions once the LED control unit
* is functional.
*/
GPIO(CHARGE_LED_1, PIN(155), GPIO_OUT_LOW)
GPIO(CHARGE_LED_2, PIN(156), GPIO_OUT_LOW)
/*
* BATLOW_L and ROP_LDO_EN are stuffing options. Set as input to dynamically
* handle the stuffing option based on board id. As both signals have external
* pulls setting this pin as input won't harm anything.
*/
GPIO(BATLOW_L_PMIC_LDO_EN, PIN(55), GPIO_INPUT)
GPIO(ACCEL4_INT, PIN(157), GPIO_INPUT)
GPIO(PP1800_DX_AUDIO_EN, PIN(141), GPIO_OUT_LOW)
/* NC / stuffing option */
GPIO(PCH_RTCRST, PIN(163), GPIO_OUT_LOW)
GPIO(PMIC_SLP_SUS_L, PIN(201), GPIO_OUT_LOW)
GPIO(USB_C1_CHARGE_EN_L, PIN(210), GPIO_OUT_LOW)
/* Alternate functions GPIO definitions */
/* GPIO162(UART_RX), GPIO165(UART_TX) */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* KB pins */
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
/* KB ROW - GPIO000-GPIO005 */
ALTERNATE(PIN_MASK(0, 0x3f), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB ROW - GPIO100-GPIO104, GPIO106-GPIO107 */
ALTERNATE(PIN_MASK(10, 0xdf), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB COL - GPIO032 */
ALTERNATE(PIN_MASK(3, 0x04), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO040, GPIO42-GPIO43 */
ALTERNATE(PIN_MASK(4, 0x0d), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO125-GPIO126 */
ALTERNATE(PIN_MASK(12, 0x60), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO142, GPIO144 */
ALTERNATE(PIN_MASK(14, 0x14), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* LPC pins */
/* LPC_CLK_RUN_L - GPIO014 */
ALTERNATE(PIN_MASK(1, 0x10), 1, MODULE_LPC, 0)
/* LAD[0:3] - GPIO111-GPIO114, SERIRQ - GPIO115, PCI_CLK - GPIO117 */
ALTERNATE(PIN_MASK(11, 0xbe), 1, MODULE_LPC, 0)
/* LRESET# - GPIO116 */
ALTERNATE(PIN_MASK(11, 0x40), 1, MODULE_LPC, GPIO_INT_BOTH)
/* LFRAME# - GPIO120 */
ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0)
/* SPI pins */
/* MOSI - GPIO054 */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
/* MISO - GPIO164 */
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, GPIO_PULL_UP)
/* PVT_SCLK - GPIO153 */
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)
/* SHD_CS0# - GPIO150. Shared SPI chip select */
ALTERNATE(PIN_MASK(15, 0x00), 1, MODULE_SPI, 0)
/* I2C pins */
/* I2C0_0 CLK - GPIO015, I2C0_0 DAT - GPIO016, I2C0_1 DAT - GPIO017 */
ALTERNATE(PIN_MASK(1, 0xe0), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C{1,2,3} CLK / DAT - GPIO020-GPIO025*/
ALTERNATE(PIN_MASK(2, 0x3f), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C0_1 CLK - GPIO134 */
ALTERNATE(PIN_MASK(13, 0x10), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* ADC pins */
/* ADC1 - GPIO057 / PPVAR_BOOSTIN_SENSE */
ALTERNATE(PIN_MASK(5, 0x80), 1, MODULE_ADC, GPIO_ANALOG)
/* ADC3 - GPIO061 / IADP_ACMON_BMON. ADC4 - GPIO062 / PMON_PSYS */
ALTERNATE(PIN_MASK(6, 0x06), 1, MODULE_ADC, GPIO_ANALOG)
/* LED1 - GPIO155. LED2 - GPIO156 */
ALTERNATE(PIN_MASK(15, 0x60), 2, MODULE_POWER_LED, 0)
/* VCC1_RST# - GPIO131 */
ALTERNATE(PIN_MASK(13, 0x02), 1, MODULE_PMU, 0)
/* nRESET_OUT - GPIO121 */
ALTERNATE(PIN_MASK(12, 0x02), 1, MODULE_PMU, 0)

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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Power and battery LED control for Glados.
*/
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "led_common.h"
#include "util.h"
#define BAT_LED_ON 1
#define BAT_LED_OFF 0
#define CRITICAL_LOW_BATTERY_PERCENTAGE 3
#define LOW_BATTERY_PERCENTAGE 10
#define LED_TOTAL_4SECS_TICKS 4
#define LED_TOTAL_2SECS_TICKS 2
#define LED_ON_1SEC_TICKS 1
#define LED_ON_2SECS_TICKS 2
const enum ec_led_id supported_led_ids[] = {
EC_LED_ID_BATTERY_LED};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
enum led_color {
LED_OFF = 0,
LED_RED,
LED_AMBER,
LED_GREEN,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
static int bat_led_set_color(enum led_color color)
{
switch (color) {
case LED_OFF:
gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
break;
case LED_RED:
gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
break;
case LED_AMBER:
gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
break;
case LED_GREEN:
gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
brightness_range[EC_LED_COLOR_RED] = 1;
brightness_range[EC_LED_COLOR_GREEN] = 1;
}
static int glados_led_set_color_battery(enum led_color color)
{
return bat_led_set_color(color);
}
static int glados_led_set_color(enum ec_led_id led_id, enum led_color color)
{
int rv;
led_auto_control(led_id, 0);
switch (led_id) {
case EC_LED_ID_BATTERY_LED:
rv = glados_led_set_color_battery(color);
break;
default:
return EC_ERROR_UNKNOWN;
}
return rv;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
if (brightness[EC_LED_COLOR_RED] != 0 &&
brightness[EC_LED_COLOR_GREEN] != 0)
glados_led_set_color(led_id, LED_AMBER);
else if (brightness[EC_LED_COLOR_RED] != 0)
glados_led_set_color(led_id, LED_RED);
else if (brightness[EC_LED_COLOR_GREEN] != 0)
glados_led_set_color(led_id, LED_GREEN);
else
glados_led_set_color(led_id, LED_OFF);
return EC_SUCCESS;
}
static void glados_led_set_battery(void)
{
static int battery_ticks;
uint32_t chflags = charge_get_flags();
battery_ticks++;
/* BAT LED behavior:
* Same as the chromeos spec
* Green/Amber for CHARGE_FLAG_FORCE_IDLE
*/
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
glados_led_set_color_battery(LED_AMBER);
break;
case PWR_STATE_DISCHARGE:
/* Less than 3%, blink one second every two second */
if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE)
glados_led_set_color_battery(
(battery_ticks % LED_TOTAL_2SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
/* Less than 10%, blink one second every four seconds */
else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
charge_get_percent() < LOW_BATTERY_PERCENTAGE)
glados_led_set_color_battery(
(battery_ticks % LED_TOTAL_4SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
else
glados_led_set_color_battery(LED_OFF);
break;
case PWR_STATE_ERROR:
glados_led_set_color_battery(
(battery_ticks % LED_TOTAL_2SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_RED : LED_OFF);
break;
case PWR_STATE_CHARGE_NEAR_FULL:
glados_led_set_color_battery(LED_GREEN);
break;
case PWR_STATE_IDLE: /* External power connected in IDLE */
if (chflags & CHARGE_FLAG_FORCE_IDLE)
glados_led_set_color_battery(
(battery_ticks % LED_TOTAL_4SECS_TICKS <
LED_ON_2SECS_TICKS) ? LED_GREEN : LED_AMBER);
else
glados_led_set_color_battery(LED_GREEN);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
/** * Called by hook task every 1 sec */
static void led_second(void)
{
if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
glados_led_set_battery();
}
DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);

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/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Minimal set of GPIOs needed for LFW loader
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
/* SPI PVT chip select */
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
/* Alternate functions GPIO definition */
/* UART */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* SPI pins */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)

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board/glados/usb_pd_policy.c
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "atomic.h"
#include "charge_manager.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_mux.h"
#include "usb_pd.h"
#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
int pd_set_power_supply_ready(int port)
{
/* Disable charging */
gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L :
GPIO_USB_C0_CHARGE_EN_L, 1);
/* Provide VBUS */
gpio_set_level(port ? GPIO_USB_C1_5V_EN :
GPIO_USB_C0_5V_EN, 1);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
return EC_SUCCESS; /* we are ready */
}
void pd_power_supply_reset(int port)
{
/* Disable VBUS */
gpio_set_level(port ? GPIO_USB_C1_5V_EN :
GPIO_USB_C0_5V_EN, 0);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
int pd_snk_is_vbus_provided(int port)
{
return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
GPIO_USB_C0_VBUS_WAKE_L);
}
int pd_check_vconn_swap(int port)
{
/* in G3, do not allow vconn swap since pp5000_A rail is off */
return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
}

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169
board/glados_pd/board.c
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* glados_pd board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "i2c.h"
#include "registers.h"
#include "switch.h"
#include "system.h"
#include "task.h"
#include "usb_pd.h"
#include "usb_pd_tcpc.h"
#include "util.h"
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
/* Indicate which source is driving the ec_int line. */
static uint32_t ec_int_status;
static uint32_t pd_status_flags;
void pd_send_ec_int(void)
{
/* If any sources are active, then drive the line low */
gpio_set_level(GPIO_EC_INT, !ec_int_status);
}
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= BIT(0);
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1 (C0 RX)
* Chan 3 : SPI1_TX (C0 TX)
* Chan 4 : TIM3_CH1 (C1 RX)
* Chan 5 : SPI2_TX (C1 TX)
*/
}
#include "gpio_list.h"
__override uint8_t board_get_usb_pd_port_count(void)
{
return CONFIG_USB_PD_PORT_MAX_COUNT;
}
void pd_set_suspend(int port, int suspend)
{
/*
* Do nothing. This is only here to make the linker happy for this
* old board on ToT.
*/
}
/* Initialize board. */
static void board_init(void)
{
/* Enable interrupts on VBUS transitions. */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
/* Set PD MCU system status bits */
if (system_jumped_late())
pd_status_flags |= PD_STATUS_JUMPED_TO_IMAGE;
if (system_is_in_rw())
pd_status_flags |= PD_STATUS_IN_RW;
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/* ADC channels */
const struct adc_t adc_channels[] = {
/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
[ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
[ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
[ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
[ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"slave", I2C_PORT_SLAVE, 1000, GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA}
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
void tcpc_alert(int port)
{
/*
* This function is called when the TCPC sets one of
* bits in the Alert register and that bit's corresponding
* location in the Alert_Mask register is set.
*/
atomic_or(&ec_int_status, port ?
PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0);
pd_send_ec_int();
}
void tcpc_alert_clear(int port)
{
/*
* The TCPM has acknowledged all Alert bits and the
* Alert# line needs to be set inactive. Clear
* the corresponding port's bit in the static variable.
*/
atomic_clear(&ec_int_status, port ?
PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0);
pd_send_ec_int();
}
static void system_hibernate_deferred(void)
{
ccprintf("EC requested hibernate\n");
cflush();
system_hibernate(0, 0);
}
DECLARE_DEFERRED(system_hibernate_deferred);
/****************************************************************************/
/* Console commands */
static int command_ec_int(int argc, char **argv)
{
/* Indicate that ec_int gpio is active due to host command */
atomic_or(&ec_int_status, PD_STATUS_HOST_EVENT);
pd_send_ec_int();
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(ecint, command_ec_int,
"",
"Toggle EC interrupt line");
static enum ec_status ec_status_host_cmd(struct host_cmd_handler_args *args)
{
const struct ec_params_pd_status *p = args->params;
struct ec_response_pd_status *r = args->response;
/*
* ec_int_status is used to store state for HOST_EVENT,
* TCPC 0 Alert, and TCPC 1 Alert bits.
*/
r->status = ec_int_status | pd_status_flags;
args->response_size = sizeof(*r);
/* Have the PD follow the EC into hibernate. */
if (p->status & EC_STATUS_HIBERNATING)
hook_call_deferred(&system_hibernate_deferred_data, 0);
/*
* If the source of the EC int line was HOST_EVENT, it has
* been acknowledged so can always clear HOST_EVENT bit
* from the ec_int_status variable
*/
atomic_clear(&ec_int_status, PD_STATUS_HOST_EVENT);
return EC_RES_SUCCESS;
}
DECLARE_HOST_COMMAND(EC_CMD_PD_EXCHANGE_STATUS, ec_status_host_cmd,
EC_VER_MASK(EC_VER_PD_EXCHANGE_STATUS));

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board/glados_pd/board.h
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* glados_pd board configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/*
* The console task is too big to include in both RO and RW images. Therefore,
* if the console task is defined, then only build an RW image. This can be
* useful for debugging to have a full console. Otherwise, without this task,
* a full RO and RW is built with a limited one-way output console.
*/
#ifdef HAS_TASK_CONSOLE
/*
* The flash size is only 32kB.
* No space for 2 partitions,
* put only RW at the beginning of the flash
*/
#undef CONFIG_FW_INCLUDE_RO
#undef CONFIG_RW_MEM_OFF
#define CONFIG_RW_MEM_OFF 0
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE 0
/* Fake full size if we had a RO partition */
#undef CONFIG_RW_SIZE
#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
#endif /* HAS_TASK_CONSOLE */
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* the UART console is on USART1 (PA9/PA10) */
#undef CONFIG_UART_CONSOLE
#define CONFIG_UART_CONSOLE 1
/* Optional features */
#define CONFIG_ADC
#undef CONFIG_ADC_WATCHDOG
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_COMMON_GPIO_SHORTNAMES
#undef CONFIG_DEBUG_ASSERT
#define CONFIG_FORCE_CONSOLE_RESUME
#define CONFIG_HIBERNATE
#define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP2
#undef CONFIG_HOSTCMD_EVENTS
#define CONFIG_HW_CRC
#define CONFIG_I2C
#define CONFIG_I2C_SLAVE
#undef CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LTO
#define CONFIG_STM_HWTIMER32
#undef CONFIG_TASK_PROFILING
#undef CONFIG_UART_TX_BUF_SIZE
#undef CONFIG_UART_TX_DMA
#undef CONFIG_UART_RX_DMA
#define CONFIG_UART_TX_BUF_SIZE 128
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_INTERNAL_COMP
#define CONFIG_USB_PD_PORT_MAX_COUNT 2
#define CONFIG_USB_PD_TCPC
#define CONFIG_USB_PD_TCPC_TRACK_VBUS
#define CONFIG_USBC_VCONN
#define CONFIG_VBOOT_HASH
#define CONFIG_WATCHDOG
#undef CONFIG_WATCHDOG_HELP
/*
* TODO(crosbug.com/p/50519): Remove CONFIG_SYSTEM_UNLOCKED prior to building
* MP FW.
*/
#define CONFIG_SYSTEM_UNLOCKED
#ifdef HAS_TASK_CONSOLE
#undef CONFIG_CONSOLE_HISTORY
#define CONFIG_CONSOLE_HISTORY 2
#else
#undef CONFIG_CONSOLE_CMDHELP
#define CONFIG_DEBUG_PRINTF
#define UARTN CONFIG_UART_CONSOLE
#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
#endif /* HAS_TASK_CONSOLE */
/* Use PSTATE embedded in the RO image, not in its own erase block */
#undef CONFIG_FLASH_PSTATE_BANK
#undef CONFIG_FW_PSTATE_SIZE
#define CONFIG_FW_PSTATE_SIZE 0
/* I2C ports configuration */
#define I2C_PORT_SLAVE 0
#define I2C_PORT_EC I2C_PORT_SLAVE
/* slave address for host commands */
#ifdef HAS_TASK_HOSTCMD
#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS CONFIG_USB_PD_I2C_SLAVE_ADDR_FLAGS
#endif
#ifndef __ASSEMBLER__
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_ADC 3
#include "gpio_signal.h"
/* ADC signal */
enum adc_channel {
ADC_C1_CC1_PD = 0,
ADC_C0_CC1_PD,
ADC_C0_CC2_PD,
ADC_C1_CC2_PD,
/* Number of ADC channels */
ADC_CH_COUNT
};
/* 1.5A Rp */
#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

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# -*- makefile -*-
# Copyright 2015 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F051C8T
CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f05x
# Not enough SRAM: Disable all tests
test-list-y=
board-y=board.o
# This target builds RW only. Therefore, remove RO from dependencies.
all_deps=$(patsubst ro,,$(def_all_deps))

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USB-C Dual TCPC Example
=======================
This board configuration implements a USB-C TCPC for two ports.
The design uses a microcontroller running code from the Chromium EC
codebase to implement the TCPC. The code tries to follow the "USB
Type-C Port Controller Interface Specification" that is released as
part of the
[USB 3.1 Specification](http://www.usb.org/developers/docs/).
Building
--------
### Chromium OS chroot
All the following instructions have been verified in a Chromium OS
chroot. You can find how to set one up on the
[Chromium development
wiki](http://dev.chromium.org/chromium-os/quick-start-guide).
### Build the TCPM code
`cd src/platform/ec`
`make BOARD=glados_pd`
Schematic
---------
![schematic image](glados_pd.png)
Note that you may need to zoom in the browser to read the image if
reading this through the git source tree browser. A
[pdf of this schematic](glados_pd.pdf) is in the
[`board/glados_pd`](.) directory. It shows three main areas.
The two (identical) sections on the left provide the analog interface
to the CC line. Each CC line is identical. Resistors are used in
combination to set the resistor applied to CC:
Resistor |`USB_Cx_CCy_DEVICE_ODL`|`USB_Cx_CCy_HOST_HIGH`|Value
---------|-----------------------|----------------------|-----
1.5A Rp | high impedance | high 3.3V | 5.11k+6.98k pullup
3A Rp | high 3.3V | high impedance | 5.11k pullup
Rd | low 0V | high impedance | 5.11k pulldown
When USB-PD transmission is required the `USB_Cx_CCy_MCU` is set low
and the data transmitted on `USB_Cx_CCy_TX_DATA`. The two resistors
form a divider that sets the level to match the BMC
specification. These resistors and the capacitor on the pulldown may
need tuning for a given application to meet the required TX eye mask.
The `EN_PP3300_USB_PD` is a critical enable output from the MCU. It
must be pulled down when power is off (not shown here, it is done as
part of the load switch on the power supply page) and remains low
until the microcontroller is ready for operation. It:
1. Enables the `PP3300_USB_PD` power supply that powers
all the USB-C port related components (eg the low speed mux `U24`
shown here and the high speed mux that is not part of this example
page)
2. Controls the isolation FET (two parts of `Q1`,two parts of `Q6`) to
disconnet the CC lines when power is off or the MCU is
intializing. When power is enabled the enable will put the gate at
3.3V and ensure no higher voltage on CC will reach the MCU.
3. Disables the Dead Battery pulldown once the MCU is ready for
operation. The Dead Battery Rd pulldown is provided by a FET (two
parts of `Q24` and `Q12`) and resistor. When there is no power, the
gate is pulled down to ground. A DFP application of Rp will pull up
the source and provide the required Vgs=-0.7 (Vgsth max should be 1V)
to turn on the FET and connect the Rd pulldown. Once there is power
and the MCU is running it will drive `EN_PP3300_USB_PD` high and
disable the FET.
There is a load switch (`U9`,`U10`,`U11`,`U12`) to provide current
limited **Vconn**.
The main area of the schematic is the STM32F051 microcontroller that
runs the [`glados_pd`](.) code.
There is a quirk in `U24`. For port `C0` the transmit data is provided
by the SPI1 controller as `SPI1_MISO`. The internal I/O multiplex
allows this to be driven on either pin `PB4` or `PA6` and thus support
driving whichever CC line is needed. Port `C1` uses the SPI2
controller which (on this package) can only use pin `PB14`, so an
external mux is used to direct this to the appropriate port.
### Replacement with Two TCPC parts
This schematic page can be replaced by two TCPC parts.
![Two TCPC block diagram](block.png)
Flashing and Running
--------------------
### Flashing the firmware binary
The microcontroller can be pre-programmed or is programmed in the
factory by pulling `USB_PD_BOOT0` high and resetting the part to
initiate a firmware update over UART. During development the
[Servo board](http://www.chromium.org/chromium-os/servo) can be used
for this.
Once programmed for the first time, the part supports secure update of
the Read/Write copy.
Known Issues
------------
1. This is the first version of the documentation...
Troubleshooting
---------------

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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* See CONFIG_TASK_LIST in config.h for details.
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
/* TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) */ \
TASK_ALWAYS(PD_C0, pd_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C1, pd_task, NULL, TASK_STACK_SIZE)

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/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
/* Interrupts */
GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(C, 14), GPIO_INT_BOTH, pd_vbus_evt_p0)
GPIO_INT(USB_C1_VBUS_WAKE_L, PIN(C, 15), GPIO_INT_BOTH, pd_vbus_evt_p1)
/*
* Older boards have A13 connected to a test point with no PU / PD, so we must
* enable an internal PU.
* Newer boards have A13 connected to 3.3V / GND through a 100K resistor, so
* we must not enable an internal PU. All MP boards will use the newer config.
* TODO(crosbug.com/p/50518): Remove CONFIG_SYSTEM_UNLOCKED prior to building
* MP FW.
*/
#ifdef CONFIG_SYSTEM_UNLOCKED
GPIO_INT(WP_L, PIN(A, 13), GPIO_INT_BOTH | GPIO_PULL_UP,
switch_interrupt)
#else
GPIO_INT(WP_L, PIN(A, 13), GPIO_INT_BOTH, switch_interrupt)
#endif
/* PD RX/TX */
GPIO(USB_C0_CC1_PD, PIN(A, 2), GPIO_ANALOG)
GPIO(USB_C_REF, PIN(A, 1), GPIO_ANALOG)
GPIO(USB_C1_CC1_PD, PIN(A, 0), GPIO_ANALOG)
GPIO(USB_C0_CC2_PD, PIN(A, 4), GPIO_ANALOG)
GPIO(USB_C1_CC2_PD, PIN(A, 5), GPIO_ANALOG)
GPIO(USB_C1_CCX_TX_DATA, PIN(B, 14), GPIO_INPUT)
GPIO(USB_C0_CC1_TX_DATA, PIN(B, 4), GPIO_INPUT)
GPIO(USB_C1_CC2_TX_SEL, PIN(B, 0), GPIO_OUT_LOW) /* C1_CC2_TX_SEL */
GPIO(USB_C0_CC2_TX_DATA, PIN(A, 6), GPIO_INPUT)
GPIO(USB_PD_VBUS_WAKE, PIN(C, 13), GPIO_INPUT)
GPIO(PP3300_USB_PD_EN, PIN(A, 15), GPIO_OUT_HIGH)
GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1), GPIO_OUT_LOW)
GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2), GPIO_OUT_LOW)
GPIO(USB_C1_CC1_VCONN1_EN, PIN(B, 9), GPIO_OUT_LOW)
GPIO(USB_C1_CC2_VCONN1_EN, PIN(F, 0), GPIO_OUT_LOW)
GPIO(USB_C0_HOST_HIGH, PIN(A, 3), GPIO_OUT_LOW)
GPIO(USB_C1_HOST_HIGH, PIN(A, 7), GPIO_OUT_LOW)
GPIO(USB_C0_CC1_ODL, PIN(A, 11), GPIO_ODR_LOW)
GPIO(USB_C0_CC2_ODL, PIN(A, 12), GPIO_ODR_LOW)
GPIO(USB_C1_CC1_ODL, PIN(B, 12), GPIO_ODR_LOW)
GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW)
/*
* I2C pins should be configured as inputs until I2C module is
* initialized. This will avoid driving the lines unintentionally.
*/
GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT)
GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT)
#ifdef BOARD_OAK_PD
GPIO(EC_INT, PIN(B, 5), GPIO_OUT_HIGH)
#else
GPIO(EC_INT, PIN(A, 14), GPIO_ODR_HIGH)
#endif
UNIMPLEMENTED(ENTERING_RW)
#if 0
/* Alternate functions */
GPIO(USB_C1_TX_CLKOUT, PIN(B, 15), GPIO_OUT_LOW)
GPIO(USB_C0_TX_CLKOUT, PIN(B, 8), GPIO_OUT_LOW)
GPIO(USB_C1_TX_CLKIN, PIN(B, 13), GPIO_OUT_LOW)
GPIO(USB_C0_TX_CLKIN, PIN(B, 3), GPIO_OUT_LOW)
#endif
ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */
ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8 */
ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15 */
ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */
ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */

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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "adc.h"
#include "chip/stm32/registers.h"
#include "gpio.h"
#include "ec_commands.h"
/* USB Power delivery board configuration */
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 16
#define TIM_CLOCK_PD_RX_C0 1
#define TIM_CLOCK_PD_TX_C1 15
#define TIM_CLOCK_PD_RX_C1 3
/* Timer channel */
#define TIM_TX_CCR_C0 1
#define TIM_RX_CCR_C0 1
#define TIM_TX_CCR_C1 2
#define TIM_RX_CCR_C1 1
#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0)
#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0)
/* RX timer capture/compare register */
#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1))
#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0)
/* TX and RX timer register */
#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1))
#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1))
#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0)
#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0)
/* use the hardware accelerator for CRC */
#define CONFIG_HW_CRC
/* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */
#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
static inline void spi_enable_clock(int port)
{
if (port == 0)
STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
else
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
}
/* DMA for transmit uses DMA CH3 for C0 and DMA_CH5 for C1 */
#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH5 : STM32_DMAC_CH3)
/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/
/* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */
#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1
/* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */
#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
#define TIM_CCR_CS 1
/*
* EXTI line 21 is connected to the CMP1 output,
* EXTI line 22 is connected to the CMP2 output,
* C0 uses CMP2, and C1 uses CMP1.
*/
#define EXTI_COMP_MASK(p) ((p) ? BIT(21) : BIT(22))
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
/* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */
#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH4 : STM32_DMAC_CH2)
/* the pins used for communication need to be hi-speed */
static inline void pd_set_pins_speed(int port)
{
if (port == 0) {
/* 40 MHz pin speed on SPI PB3&4,
* (USB_C0_TX_CLKIN & USB_C0_CC1_TX_DATA)
*/
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0;
/* 40 MHz pin speed on TIM16_CH1 (PB8),
* (USB_C0_TX_CLKOUT)
*/
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000;
} else {
/* 40 MHz pin speed on SPI PB13/14,
* (USB_C1_TX_CLKIN & USB_C1_CCX_TX_DATA)
*/
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000;
/* 40 MHz pin speed on TIM15_CH2 (PB15) */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000;
}
}
/* Reset SPI peripheral used for TX */
static inline void pd_tx_spi_reset(int port)
{
if (port == 0) {
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
} else {
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= BIT(14);
STM32_RCC_APB1RSTR &= ~BIT(14);
}
}
/* Drive the CC line from the TX block */
static inline void pd_tx_enable(int port, int polarity)
{
if (port == 0) {
/* put SPI function on TX pin */
if (polarity) {
/* USB_C0_CC2_TX_DATA: PA6 is SPI1 MISO */
gpio_set_alternate_function(GPIO_A, 0x0040, 0);
/* MCU ADC PA4 pin output low */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*4))) /* PA4 disable ADC */
| (1 << (2*4)); /* Set as GPO */
gpio_set_level(GPIO_USB_C0_CC2_PD, 0);
} else {
/* USB_C0_CC1_TX_DATA: PB4 is SPI1 MISO */
gpio_set_alternate_function(GPIO_B, 0x0010, 0);
/* MCU ADC PA2 pin output low */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*2))) /* PA2 disable ADC */
| (1 << (2*2)); /* Set as GPO */
gpio_set_level(GPIO_USB_C0_CC1_PD, 0);
}
} else {
/* put SPI function on TX pin */
/* USB_C1_CCX_TX_DATA: PB14 is SPI1 MISO */
gpio_set_alternate_function(GPIO_B, 0x4000, 0);
/* MCU ADC pin output low */
if (polarity) {
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*5))) /* PA5 disable ADC */
| (1 << (2*5)); /* Set as GPO */
gpio_set_level(GPIO_USB_C1_CC2_PD, 0);
} else {
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*0))) /* PA0 disable ADC */
| (1 << (2*0)); /* Set as GPO */
gpio_set_level(GPIO_USB_C1_CC1_PD, 0);
}
/*
* There is a pin muxer to select CC1 or CC2 TX_DATA,
* Pin mux is controlled by USB_C1_CC2_TX_SEL pin,
* USB_C1_CC1_TX_DATA will be selected, if polarity is 0,
* USB_C1_CC2_TX_DATA will be selected, if polarity is 1 .
*/
gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity);
}
}
/* Put the TX driver in Hi-Z state */
static inline void pd_tx_disable(int port, int polarity)
{
if (port == 0) {
if (polarity) {
/* Set TX_DATA to Hi-Z, PA6 is SPI1 MISO */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*6)));
/* set ADC PA4 pin to ADC function (Hi-Z) */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
| (3 << (2*4))); /* PA4 as ADC */
} else {
/* Set TX_DATA to Hi-Z, PB4 is SPI1 MISO */
STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
& ~(3 << (2*4)));
/* set ADC PA2 pin to ADC function (Hi-Z) */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
| (3 << (2*2))); /* PA2 as ADC */
}
} else {
/* Set TX_DATA (PB14) Hi-Z */
STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
& ~(3 << (2*14)));
if (polarity) {
/* set ADC PA5 pin to ADC function (Hi-Z) */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
| (3 << (2*5))); /* PA5 as ADC */
} else {
/* set ADC PA0 pin to ADC function (Hi-Z) */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
| (3 << (2*0))); /* PA0 as ADC */
}
}
}
/* we know the plug polarity, do the right configuration */
static inline void pd_select_polarity(int port, int polarity)
{
uint32_t val = STM32_COMP_CSR;
/* Use window mode so that COMP1 and COMP2 share non-inverting input */
val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
if (port == 0) {
/* C0 use the right comparator inverted input for COMP2 */
STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
(polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */
: STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
} else {
/* C1 use the right comparator inverted input for COMP1 */
STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
(polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */
: STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
}
}
/* Initialize pins used for TX and put them in Hi-Z */
static inline void pd_tx_init(void)
{
gpio_config_module(MODULE_USB_PD, 1);
}
static inline void pd_set_host_mode(int port, int enable)
{
if (port == 0) {
if (enable) {
/* Pull up for host mode */
gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_OUTPUT);
gpio_set_level(GPIO_USB_C0_HOST_HIGH, 1);
/* High-Z is used for host mode. */
gpio_set_level(GPIO_USB_C0_CC1_ODL, 1);
gpio_set_level(GPIO_USB_C0_CC2_ODL, 1);
/* Set TX Hi-Z */
gpio_set_flags(GPIO_USB_C0_CC1_TX_DATA, GPIO_INPUT);
gpio_set_flags(GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
} else {
/* Set HOST_HIGH to High-Z for device mode. */
gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_INPUT);
/* Pull low for device mode. */
gpio_set_level(GPIO_USB_C0_CC1_ODL, 0);
gpio_set_level(GPIO_USB_C0_CC2_ODL, 0);
}
} else {
if (enable) {
/* Pull up for host mode */
gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_OUTPUT);
gpio_set_level(GPIO_USB_C1_HOST_HIGH, 1);
/* High-Z is used for host mode. */
gpio_set_level(GPIO_USB_C1_CC1_ODL, 1);
gpio_set_level(GPIO_USB_C1_CC2_ODL, 1);
/* Set TX Hi-Z */
gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
} else {
/* Set HOST_HIGH to High-Z for device mode. */
gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_INPUT);
/* Pull low for device mode. */
gpio_set_level(GPIO_USB_C1_CC1_ODL, 0);
gpio_set_level(GPIO_USB_C1_CC2_ODL, 0);
}
}
}
/**
* Initialize various GPIOs and interfaces to safe state at start of pd_task.
*
* These include:
* VBUS, charge path based on power role.
* Physical layer CC transmit.
* VCONNs disabled.
*
* @param port USB-C port number
* @param power_role Power role of device
*/
static inline void pd_config_init(int port, uint8_t power_role)
{
/*
* Set CC pull resistors, and charge_en and vbus_en GPIOs to match
* the initial role.
*/
pd_set_host_mode(port, power_role);
/* Initialize TX pins and put them in Hi-Z */
pd_tx_init();
if (port == 0) {
gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0);
gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0);
} else {
gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN, 0);
gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN, 0);
}
}
static inline int pd_adc_read(int port, int cc)
{
if (port == 0)
return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD);
else
return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD);
}
static inline void pd_set_vconn(int port, int polarity, int enable)
{
/* Set VCONN on the opposite CC line from the polarity */
if (port == 0) {
gpio_set_level(polarity ? GPIO_USB_C0_CC1_VCONN1_EN :
GPIO_USB_C0_CC2_VCONN1_EN, enable);
/* Set TX_DATA pin to Hi-Z */
gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA :
GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
} else {
gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN :
GPIO_USB_C1_CC2_VCONN1_EN, enable);
/* Set TX_DATA pin to Hi-Z */
gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
}
}
#endif /* __CROS_EC_USB_PD_CONFIG_H */

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kevin

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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Board is only valid for host tools */
#ifndef HOST_TOOLS_BUILD
#error "Can only build for host tools"
#endif

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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Board is only valid for host tools */

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board/kevin/build.mk
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# -*- makefile -*-
# Copyright 2016 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# Board is only valid for host tools
CHIP:=npcx
CHIP_VARIANT:=npcx5m5g
board-y=board.o

7
board/kevin/ec.tasklist
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/* Copyright 2016 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Board is only valid for host tools */
#define CONFIG_TASK_LIST

1
board/oak_pd
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glados_pd