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common: replace 1 << digits, with BIT(digits) 

Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.

Fix an error in motion_lid try to set bit 31 of a signed integer.

BUG=None
BRANCH=None
TEST=compile

Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This commit is contained in:
Gwendal Grignou 2019-03-11 15:57:52 -07:00 committed by chrome-bot
parent 0bfc511527
commit bb266fc26f
263 changed files with 2486 additions and 2482 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
board/atlas/board.c
View File

@ -274,7 +274,7 @@ static void board_report_pmic_fault(const char *str)
BD99992GW_REG_RESETIRQ1, &vrfault) != EC_SUCCESS)
return;
if (!(vrfault & (1 << 4)))
if (!(vrfault & BIT(4)))
return;
/* VRFAULT has occurred, print VRFAULT status bits. */
@ -293,7 +293,7 @@ static void board_report_pmic_fault(const char *str)
/* Clear all faults -- Write 1 to clear. */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992,
BD99992GW_REG_RESETIRQ1, (1 << 4));
BD99992GW_REG_RESETIRQ1, BIT(4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992,
BD99992GW_REG_PWRSTAT1, pwrstat1);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992,

12
board/coffeecake/board.c
View File

@ -140,15 +140,15 @@ void board_set_usb_output_voltage(int mv)
void board_config_pre_init(void)
{
/* Enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/* Enable DAC interface clock. */
STM32_RCC_APB1ENR |= (1 << 29);
STM32_RCC_APB1ENR |= BIT(29);
/* Delay 1 APB clock cycle after the clock is enabled */
clock_wait_bus_cycles(BUS_APB, 1);
/* Set 5Vsafe Vdac */
board_set_usb_output_voltage(5000);
/* Remap USART DMA to match the USART driver */
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
}
#ifdef CONFIG_SPI_FLASH
@ -156,7 +156,7 @@ void board_config_pre_init(void)
static void board_init_spi2(void)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
STM32_SYSCFG_CFGR1 |= BIT(24);
/* Set pin NSS to general purpose output mode (01b). */
/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
@ -176,8 +176,8 @@ static void board_init_spi2(void)
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
STM32_RCC_APB1RSTR |= BIT(14);
STM32_RCC_APB1RSTR &= ~BIT(14);
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;

6
board/coffeecake/usb_pd_config.h
View File

@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) (1 << 21)
#define EXTI_COMP_MASK(p) BIT(21)
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */

20
board/cr50/rdd.c
View File

@ -34,15 +34,15 @@ enum ccd_block_flags {
* UARTs. Disabling these can be helpful if the AP or EC is doing
* something which creates an interrupt storm on these ports.
*/
CCD_BLOCK_AP_UART = (1 << 0),
CCD_BLOCK_EC_UART = (1 << 1),
CCD_BLOCK_AP_UART = BIT(0),
CCD_BLOCK_EC_UART = BIT(1),
/*
* Any ports shared with servo. Disabling these will stop CCD from
* interfering with servo, in the case where both CCD and servo is
* connected but servo isn't properly detected.
*/
CCD_BLOCK_SERVO_SHARED = (1 << 2)
CCD_BLOCK_SERVO_SHARED = BIT(2)
};
/* Which UARTs are blocked by console command */
@ -128,28 +128,28 @@ enum ccd_state_flag {
/* Flags for individual devices/ports */
/* AP UART is enabled. RX-only, unless TX is also enabled. */
CCD_ENABLE_UART_AP = (1 << 0),
CCD_ENABLE_UART_AP = BIT(0),
/* AP UART transmit is enabled. Requires AP UART enabled. */
CCD_ENABLE_UART_AP_TX = (1 << 1),
CCD_ENABLE_UART_AP_TX = BIT(1),
/* EC UART is enabled. RX-only, unless TX is also enabled. */
CCD_ENABLE_UART_EC = (1 << 2),
CCD_ENABLE_UART_EC = BIT(2),
/* EC UART transmit is enabled. Requires EC UART enabled. */
CCD_ENABLE_UART_EC_TX = (1 << 3),
CCD_ENABLE_UART_EC_TX = BIT(3),
/*
* EC UART bit-banging is enabled. Requires EC UART enabled, and
* blocks EC UART transmit.
*/
CCD_ENABLE_UART_EC_BITBANG = (1 << 4),
CCD_ENABLE_UART_EC_BITBANG = BIT(4),
/* I2C port is enabled */
CCD_ENABLE_I2C = (1 << 5),
CCD_ENABLE_I2C = BIT(5),
/* SPI port is enabled for AP and/or EC flash */
CCD_ENABLE_SPI = (1 << 6),
CCD_ENABLE_SPI = BIT(6),
};
int console_is_restricted(void)

28
board/cr50/scratch_reg1.h
View File

@ -11,8 +11,8 @@
* Bit assignments of the LONG_LIFE_SCRATCH1 register. This register survives
* all kinds of resets, it is cleared only on the Power ON event.
*/
#define BOARD_SLAVE_CONFIG_SPI (1 << 0) /* TPM uses SPI interface */
#define BOARD_SLAVE_CONFIG_I2C (1 << 1) /* TPM uses I2C interface */
#define BOARD_SLAVE_CONFIG_SPI BIT(0) /* TPM uses SPI interface */
#define BOARD_SLAVE_CONFIG_I2C BIT(1) /* TPM uses I2C interface */
/*
* The gaps are left to ensure backwards compatibility with the earliest cr50
@ -21,20 +21,20 @@
*/
/* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
#define BOARD_NEEDS_SYS_RST_PULL_UP (1 << 5) /* Add a pullup to sys_rst_l */
#define BOARD_USE_PLT_RESET (1 << 6) /* Use plt_rst_l instead of */
#define BOARD_NEEDS_SYS_RST_PULL_UP BIT(5) /* Add a pullup to sys_rst_l */
#define BOARD_USE_PLT_RESET BIT(6) /* Use plt_rst_l instead of */
/* sys_rst_l to monitor the */
/* system resets */
/* Bits to store write protect bit state across deep sleep and resets. */
#define BOARD_WP_ASSERTED (1 << 8)
#define BOARD_FORCING_WP (1 << 9)
#define BOARD_WP_ASSERTED BIT(8)
#define BOARD_FORCING_WP BIT(9)
/*
* Bit to signal to compatible RO to suppress its uart output.
* Helps to reduce time to resume from deep sleep.
*/
#define BOARD_NO_RO_UART (1 << 10)
#define BOARD_NO_RO_UART BIT(10)
/*
* Bits to store current case-closed debug state across deep sleep.
@ -46,18 +46,18 @@
#define BOARD_CCD_STATE (3 << BOARD_CCD_SHIFT)
/* Prevent Cr50 from entering deep sleep when the AP is off */
#define BOARD_DEEP_SLEEP_DISABLED (1 << 13)
#define BOARD_DEEP_SLEEP_DISABLED BIT(13)
/* Use Cr50_RX_AP_TX to determine if the AP is off or on */
#define BOARD_DETECT_AP_WITH_UART (1 << 14)
#define BOARD_DETECT_AP_WITH_UART BIT(14)
/* ITE EC sync sequence generation after reset is required. */
#define BOARD_ITE_EC_SYNC_NEEDED (1 << 15)
#define BOARD_ITE_EC_SYNC_NEEDED BIT(15)
/*
* Enable delayed write protect disable for systems that can be opened
* in less than 2 minutes
*/
#define BOARD_WP_DISABLE_DELAY (1 << 16)
#define BOARD_WP_DISABLE_DELAY BIT(16)
/*
* Enable custom options required for the closed source EC on the
* Sarien/Arcada boards. Includes the following behavior
@ -67,18 +67,18 @@
* EC extended reset
* Power+Refresh recovery mode (instead of Power+Refresh+Esc)
*/
#define BOARD_CLOSED_SOURCE_SET1 (1 << 17)
#define BOARD_CLOSED_SOURCE_SET1 BIT(17)
/*
* Wait until PLT_RST_L is asserted before deasserting reset.
*/
#define BOARD_CLOSED_LOOP_RESET (1 << 18)
#define BOARD_CLOSED_LOOP_RESET BIT(18)
/*
* The board uses INA pins as GPIOs, so it can't support reading inas using usb
* i2c.
*/
#define BOARD_NO_INA_SUPPORT (1 << 19)
#define BOARD_NO_INA_SUPPORT BIT(19)
/*
* Macro to capture all properties related to board strapping pins. This must be

2
board/cr50/wp.c
View File

@ -277,7 +277,7 @@ int board_wipe_tpm(void)
* git sha c7282f6.
*/
#define FWMP_HASH_SIZE 32
#define FWMP_DEV_DISABLE_CCD_UNLOCK (1 << 6)
#define FWMP_DEV_DISABLE_CCD_UNLOCK BIT(6)
#define FIRMWARE_FLAG_DEV_MODE 0x02
struct RollbackSpaceFirmware {

4
board/dingdong/board.c
View File

@ -95,9 +95,9 @@ void hpd_event(enum gpio_signal signal)
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/* Remap USART DMA to match the USART driver */
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
}
/* Initialize board. */

6
board/dingdong/usb_pd_config.h
View File

@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) (1 << 21)
#define EXTI_COMP_MASK(p) BIT(21)
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */

2
board/discovery-stm32f072/board.c
View File

@ -160,7 +160,7 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
void usb_spi_board_enable(struct usb_spi_config const *config)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
STM32_SYSCFG_CFGR1 |= BIT(24);
/* Configure SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 1);

6
board/eve/board.c
View File

@ -374,7 +374,7 @@ static void board_report_pmic_fault(const char *str)
!= EC_SUCCESS)
return;
if (!(vrfault & (1 << 4)))
if (!(vrfault & BIT(4)))
return;
/* VRFAULT has occurred, print VRFAULT status bits. */
@ -390,7 +390,7 @@ static void board_report_pmic_fault(const char *str)
pwrstat2);
/* Clear all faults -- Write 1 to clear. */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
@ -901,7 +901,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &g_bmi160_data,
.port = I2C_PORT_GYRO,
.addr = BMI160_ADDR0,
.default_range = 1 << 11, /* 16LSB / uT, fixed */
.default_range = BIT(11), /* 16LSB / uT, fixed */
.rot_standard_ref = &mag_standard_ref,
.min_frequency = BMM150_MAG_MIN_FREQ,
.max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),

2
board/fizz/board.c
View File

@ -703,7 +703,7 @@ static const struct charge_port_info bj_adapters[] = {
* KBL-U Celeron 3965 7 65
* KBL-U Celeron 3865 0 65
*/
#define BJ_ADAPTER_90W_MASK (1 << 4 | 1 << 5 | 1 << 6)
#define BJ_ADAPTER_90W_MASK (BIT(4) | BIT(5) | BIT(6))
static void setup_bj(void)
{

2
board/flapjack/board.h
View File

@ -210,7 +210,7 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
/* Define panel size mask according to skuid */
#define SKU_ID_PANEL_SIZE_MASK (1 << 1)
#define SKU_ID_PANEL_SIZE_MASK BIT(1)
#ifndef __ASSEMBLER__

2
board/glados_pd/board.c
View File

@ -37,7 +37,7 @@ void pd_send_ec_int(void)
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1 (C0 RX)

10
board/glados_pd/usb_pd_config.h
View File

@ -72,7 +72,7 @@ static inline void spi_enable_clock(int port)
* EXTI line 22 is connected to the CMP2 output,
* C0 uses CMP2, and C1 uses CMP1.
*/
#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22))
#define EXTI_COMP_MASK(p) ((p) ? BIT(21) : BIT(22))
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
@ -108,12 +108,12 @@ static inline void pd_tx_spi_reset(int port)
{
if (port == 0) {
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
} else {
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
STM32_RCC_APB1RSTR |= BIT(14);
STM32_RCC_APB1RSTR &= ~BIT(14);
}
}

8
board/glkrvp/chg_usb_pd.c
View File

@ -19,10 +19,10 @@
#define PTN5110_EXT_GPIO_CONFIG 0x92
#define PTN5110_EXT_GPIO_CONTROL 0x93
#define PTN5110_EXT_GPIO_FRS_EN (1 << 6)
#define PTN5110_EXT_GPIO_EN_SRC (1 << 5)
#define PTN5110_EXT_GPIO_EN_SNK1 (1 << 4)
#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L (1 << 3)
#define PTN5110_EXT_GPIO_FRS_EN BIT(6)
#define PTN5110_EXT_GPIO_EN_SRC BIT(5)
#define PTN5110_EXT_GPIO_EN_SNK1 BIT(4)
#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L BIT(3)
enum glkrvp_charge_ports {
TYPE_C_PORT_0,

8
board/glkrvp_ite/chg_usb_pd.c
View File

@ -19,10 +19,10 @@
#define PTN5110_EXT_GPIO_CONFIG 0x92
#define PTN5110_EXT_GPIO_CONTROL 0x93
#define PTN5110_EXT_GPIO_FRS_EN (1 << 6)
#define PTN5110_EXT_GPIO_EN_SRC (1 << 5)
#define PTN5110_EXT_GPIO_EN_SNK1 (1 << 4)
#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L (1 << 3)
#define PTN5110_EXT_GPIO_FRS_EN BIT(6)
#define PTN5110_EXT_GPIO_EN_SRC BIT(5)
#define PTN5110_EXT_GPIO_EN_SNK1 BIT(4)
#define PTN5110_EXT_GPIO_IILIM_5V_VBUS_L BIT(3)
enum glkrvp_charge_ports {
TYPE_C_PORT_0,

4
board/hammer/board.c
View File

@ -224,7 +224,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_PWM - 1);
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/* Remap USART DMA to match the USART driver */
/*
@ -232,7 +232,7 @@ void board_config_pre_init(void)
* Chan 4 : USART1_TX
* Chan 5 : USART1_RX
*/
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */
STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
}
int board_has_keyboard_backlight(void)

10
board/hoho/board.c
View File

@ -97,9 +97,9 @@ void hpd_event(enum gpio_signal signal)
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/* Remap USART DMA to match the USART driver */
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
}
#ifdef CONFIG_SPI_FLASH
@ -107,7 +107,7 @@ void board_config_pre_init(void)
static void board_init_spi2(void)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
STM32_SYSCFG_CFGR1 |= BIT(24);
/* Set pin NSS to general purpose output mode (01b). */
/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
@ -127,8 +127,8 @@ static void board_init_spi2(void)
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
STM32_RCC_APB1RSTR |= BIT(14);
STM32_RCC_APB1RSTR &= ~BIT(14);
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;

6
board/hoho/usb_pd_config.h
View File

@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) (1 << 21)
#define EXTI_COMP_MASK(p) BIT(21)
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */

2
board/host/charger.c
View File

@ -24,7 +24,7 @@ static const struct charger_info mock_charger_info = {
.input_current_step = 128,
};
#define OPTION_CHARGE_INHIBIT (1 << 0)
#define OPTION_CHARGE_INHIBIT BIT(0)
static uint32_t mock_option;
static uint32_t mock_mode;

4
board/jerry/board.c
View File

@ -48,7 +48,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/* Remap USART DMA to match the USART driver */
/*
@ -58,5 +58,5 @@ void board_config_pre_init(void)
* Chan 4 : USART1_TX
* Chan 5 : USART1_RX
*/
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */
STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
}

2
board/kukui/board.c
View File

@ -426,7 +426,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &g_bmi160_data,
.port = I2C_PORT_ACCEL,
.addr = BMI160_ADDR0,
.default_range = 1 << 11, /* 16LSB / uT, fixed */
.default_range = BIT(11), /* 16LSB / uT, fixed */
.rot_standard_ref = &mag_standard_ref,
.min_frequency = BMM150_MAG_MIN_FREQ,
.max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),

4
board/mchpevb1/board.c
View File

@ -880,10 +880,10 @@ static void ds1624_update(void)
DS1624_READ_TEMP16, &temp);
d = (temp & 0x7FFF) >> 8;
if ((uint32_t)temp & (1 << 7))
if ((uint32_t)temp & BIT(7))
d++;
if ((uint32_t)temp & (1 << 15))
if ((uint32_t)temp & BIT(15))
d |= (1u << 31);
ds1624_temp = (int32_t)d;

6
board/nami/board.h
View File

@ -301,9 +301,9 @@ enum model_id {
MODEL_BARD = 2,
};
#define SKU_ID_MASK_CONVERTIBLE (1 << 9)
#define SKU_ID_MASK_KEYPAD (1 << 15)
#define SKU_ID_MASK_UK2 (1 << 18)
#define SKU_ID_MASK_CONVERTIBLE BIT(9)
#define SKU_ID_MASK_KEYPAD BIT(15)
#define SKU_ID_MASK_UK2 BIT(18)
/* TODO(crosbug.com/p/61098): Verify the numbers below. */
/*

4
board/nami/led.c
View File

@ -80,9 +80,9 @@ struct led_pattern {
};
#define PULSE_NO 0
#define PULSE(interval) (1 << 7 | (interval))
#define PULSE(interval) (BIT(7) | (interval))
#define BLINK(interval) (interval)
#define ALTERNATE(interval) (1 << 6 | (interval))
#define ALTERNATE(interval) (BIT(6) | (interval))
#define IS_PULSING(pulse) ((pulse) & 0x80)
#define IS_ALTERNATE(pulse) ((pulse) & 0x40)
#define PULSE_INTERVAL(pulse) (((pulse) & 0x3f) * 100 * MSEC)

4
board/nautilus/board.c
View File

@ -288,7 +288,7 @@ static void board_report_pmic_fault(const char *str)
!= EC_SUCCESS)
return;
if (!(vrfault & (1 << 4)))
if (!(vrfault & BIT(4)))
return;
/* VRFAULT has occurred, print VRFAULT status bits. */
@ -304,7 +304,7 @@ static void board_report_pmic_fault(const char *str)
pwrstat2);
/* Clear all faults -- Write 1 to clear. */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);

10
board/nocturne/board.c
View File

@ -544,7 +544,7 @@ static void board_pmic_init(void)
/* Mask V5A_DS3_PG from PMIC PGMASK1. */
if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x18, &pgmask1))
return;
pgmask1 |= (1 << 2);
pgmask1 |= BIT(2);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x18, pgmask1);
board_pmic_disable_slp_s0_vr_decay();
@ -645,7 +645,7 @@ static void board_report_pmic_fault(const char *str)
!= EC_SUCCESS)
return;
if (!(vrfault & (1 << 4)))
if (!(vrfault & BIT(4)))
return;
/* VRFAULT has occurred, print VRFAULT status bits. */
@ -661,7 +661,7 @@ static void board_report_pmic_fault(const char *str)
pwrstat2);
/* Clear all faults -- Write 1 to clear. */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
@ -799,7 +799,7 @@ uint16_t tcpc_get_alert_status(void)
if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
/* The TCPCI spec says to ignore bits 14:12. */
regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
regval &= ~(BIT(14) | BIT(13) | BIT(12));
if (regval)
status |= PD_STATUS_TCPC_ALERT_0;
@ -809,7 +809,7 @@ uint16_t tcpc_get_alert_status(void)
if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
/* TCPCI spec says to ignore bits 14:12. */
regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
regval &= ~(BIT(14) | BIT(13) | BIT(12));
if (regval)
status |= PD_STATUS_TCPC_ALERT_1;

6
board/plankton/usb_pd_config.h
View File

@ -51,7 +51,7 @@ static inline void spi_enable_clock(int port)
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) (1 << 21)
#define EXTI_COMP_MASK(p) BIT(21)
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */

6
board/poppy/board.c
View File

@ -378,7 +378,7 @@ static void board_report_pmic_fault(const char *str)
!= EC_SUCCESS)
return;
if (!(vrfault & (1 << 4)))
if (!(vrfault & BIT(4)))
return;
/* VRFAULT has occurred, print VRFAULT status bits. */
@ -394,7 +394,7 @@ static void board_report_pmic_fault(const char *str)
pwrstat2);
/* Clear all faults -- Write 1 to clear. */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
@ -808,7 +808,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &g_bmi160_data,
.port = I2C_PORT_GYRO,
.addr = BMI160_ADDR0,
.default_range = 1 << 11, /* 16LSB / uT, fixed */
.default_range = BIT(11), /* 16LSB / uT, fixed */
.rot_standard_ref = &mag_standard_ref,
.min_frequency = BMM150_MAG_MIN_FREQ,
.max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),

2
board/rainier/board.c
View File

@ -416,7 +416,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &bmp280_drv_data,
.port = CONFIG_SPI_ACCEL_PORT,
.addr = BMI160_SET_SPI_ADDRESS(CONFIG_SPI_ACCEL_PORT),
.default_range = 1 << 18, /* 1bit = 4 Pa, 16bit ~= 2600 hPa */
.default_range = BIT(18), /* 1bit = 4 Pa, 16bit ~= 2600 hPa */
.min_frequency = BMP280_BARO_MIN_FREQ,
.max_frequency = BMP280_BARO_MAX_FREQ,
},

4
board/rammus/board.c
View File

@ -312,7 +312,7 @@ static void board_report_pmic_fault(const char *str)
!= EC_SUCCESS)
return;
if (!(vrfault & (1 << 4)))
if (!(vrfault & BIT(4)))
return;
/* VRFAULT has occurred, print VRFAULT status bits. */
@ -328,7 +328,7 @@ static void board_report_pmic_fault(const char *str)
pwrstat2);
/* Clear all faults -- Write 1 to clear. */
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, BIT(4));
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);

4
board/reef/board.c
View File

@ -803,7 +803,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &g_bmi160_data,
.port = I2C_PORT_GYRO,
.addr = BMI160_ADDR0,
.default_range = 1 << 11, /* 16LSB / uT, fixed */
.default_range = BIT(11), /* 16LSB / uT, fixed */
.rot_standard_ref = &mag_standard_ref,
.min_frequency = BMM150_MAG_MIN_FREQ,
.max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
@ -818,7 +818,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &bmp280_drv_data,
.port = I2C_PORT_BARO,
.addr = BMP280_I2C_ADDRESS1,
.default_range = 1 << 18, /* 1bit = 4 Pa, 16bit ~= 2600 hPa */
.default_range = BIT(18), /* 1bit = 4 Pa, 16bit ~= 2600 hPa */
.min_frequency = BMP280_BARO_MIN_FREQ,
.max_frequency = BMP280_BARO_MAX_FREQ,
},

4
board/reef_mchp/board.c
View File

@ -1052,7 +1052,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &g_bmi160_data,
.port = I2C_PORT_GYRO,
.addr = BMI160_ADDR0,
.default_range = 1 << 11, /* 16LSB / uT, fixed */
.default_range = BIT(11), /* 16LSB / uT, fixed */
.rot_standard_ref = &mag_standard_ref,
.min_frequency = BMM150_MAG_MIN_FREQ,
.max_frequency = BMM150_MAG_MAX_FREQ(SPECIAL),
@ -1067,7 +1067,7 @@ struct motion_sensor_t motion_sensors[] = {
.drv_data = &bmp280_drv_data,
.port = I2C_PORT_BARO,
.addr = BMP280_I2C_ADDRESS1,
.default_range = 1 << 18, /* 1bit = 4 Pa, 16bit ~= 2600 hPa */
.default_range = BIT(18), /* 1bit = 4 Pa, 16bit ~= 2600 hPa */
.min_frequency = BMP280_BARO_MIN_FREQ,
.max_frequency = BMP280_BARO_MAX_FREQ,
},

2
board/samus/board.c
View File

@ -87,7 +87,7 @@ const struct adc_t adc_channels[] = {
* now.
*/
{"BatteryTemp", LM4_ADC_SEQ2, 1, 1, 0,
LM4_AIN(10), 0x06 /* IE0 | END0 */, LM4_GPIO_B, (1<<4)},
LM4_AIN(10), 0x06 /* IE0 | END0 */, LM4_GPIO_B, BIT(4)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);

4
board/samus/board.h
View File

@ -202,8 +202,8 @@ void bkboost_det_interrupt(enum gpio_signal signal);
void jtag_interrupt(enum gpio_signal signal);
/* Bit masks for turning on PP5000 rail in G3 */
#define PP5000_IN_G3_AC (1 << 0)
#define PP5000_IN_G3_LIGHTBAR (1 << 1)
#define PP5000_IN_G3_AC BIT(0)
#define PP5000_IN_G3_LIGHTBAR BIT(1)
/* Enable/disable PP5000 rail mask in G3 */
void set_pp5000_in_g3(int mask, int enable);

6
board/samus/panel.c
View File

@ -35,7 +35,7 @@
#define LP8555_REG_CURRENT_MAXCURR_50MA 0x07
#define LP8555_REG_STEP 0x15
#define LP8555_REG_STEP_STEP_0MS (0 << 0)
#define LP8555_REG_STEP_STEP_8MS (1 << 0)
#define LP8555_REG_STEP_STEP_8MS BIT(0)
#define LP8555_REG_STEP_STEP_16MS (2 << 0)
#define LP8555_REG_STEP_STEP_24MS (3 << 0)
#define LP8555_REG_STEP_STEP_28MS (4 << 0)
@ -43,7 +43,7 @@
#define LP8555_REG_STEP_STEP_100MS (6 << 0)
#define LP8555_REG_STEP_STEP_200MS (7 << 0)
#define LP8555_REG_STEP_PWM_IN_HYST_NONE (0 << 3)
#define LP8555_REG_STEP_PWM_IN_HYST_1LSB (1 << 3)
#define LP8555_REG_STEP_PWM_IN_HYST_1LSB BIT(3)
#define LP8555_REG_STEP_PWM_IN_HYST_2LSB (2 << 3)
#define LP8555_REG_STEP_PWM_IN_HYST_4LSB (3 << 3)
#define LP8555_REG_STEP_PWM_IN_HYST_8LSB (4 << 3)
@ -51,7 +51,7 @@
#define LP8555_REG_STEP_PWM_IN_HYST_32LSB (6 << 3)
#define LP8555_REG_STEP_PWM_IN_HYST_64LSB (7 << 3)
#define LP8555_REG_STEP_SMOOTH_NONE (0 << 6)
#define LP8555_REG_STEP_SMOOTH_LIGHT (1 << 6)
#define LP8555_REG_STEP_SMOOTH_LIGHT BIT(6)
#define LP8555_REG_STEP_SMOOTH_MEDIUM (2 << 6)
#define LP8555_REG_STEP_SMOOTH_HEAVY (3 << 6)

4
board/samus_pd/board.c
View File

@ -181,7 +181,7 @@ void pch_evt(enum gpio_signal signal)
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1 (C0 RX)
@ -196,7 +196,7 @@ void board_config_pre_init(void)
* Remap USART1 RX/TX DMA to match uart driver. Remap SPI2 RX/TX and
* TIM3_CH1 for unique DMA channels.
*/
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) | (1 << 24) | (1 << 30);
STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) | BIT(24) | BIT(30);
}
#include "gpio_list.h"

10
board/samus_pd/usb_pd_config.h
View File

@ -64,7 +64,7 @@ static inline void spi_enable_clock(int port)
#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) ((p) ? (1<<22) : (1 << 21))
#define EXTI_COMP_MASK(p) ((p) ? BIT(22) : BIT(21))
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@ -93,12 +93,12 @@ static inline void pd_tx_spi_reset(int port)
{
if (port == 0) {
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
STM32_RCC_APB1RSTR |= BIT(14);
STM32_RCC_APB1RSTR &= ~BIT(14);
} else {
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
}
}

4
board/servo_micro/board.c
View File

@ -43,12 +43,12 @@ void board_config_pre_init(void)
* i2c : no dma
* tim16/17: no dma
*/
STM32_SYSCFG_CFGR1 |= (1 << 26); /* Remap USART3 RX/TX DMA */
STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */
/* Remap SPI2 to DMA channels 6 and 7 */
/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
/* but cros_ec hardcodes a 6/7 assumption in registers.h */
STM32_SYSCFG_CFGR1 |= (1 << 24);
STM32_SYSCFG_CFGR1 |= BIT(24);
}

10
board/servo_v4/board.c
View File

@ -41,7 +41,7 @@
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/*
* the DMA mapping is :
@ -60,13 +60,13 @@ void board_config_pre_init(void)
* Reference Manual
*/
/* Remap USART1 Tx from DMA channel 2 to channel 4 */
STM32_SYSCFG_CFGR1 |= (1 << 9);
STM32_SYSCFG_CFGR1 |= BIT(9);
/* Remap USART1 Rx from DMA channel 3 to channel 5 */
STM32_SYSCFG_CFGR1 |= (1 << 10);
STM32_SYSCFG_CFGR1 |= BIT(10);
/* Remap TIM3_CH1 from DMA channel 4 to channel 6 */
STM32_SYSCFG_CFGR1 |= (1 << 30);
STM32_SYSCFG_CFGR1 |= BIT(30);
/* Remap SPI2 Tx from DMA channel 5 to channel 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
STM32_SYSCFG_CFGR1 |= BIT(24);
}
/******************************************************************************

10
board/servo_v4/usb_pd_config.h
View File

@ -83,7 +83,7 @@ static inline void spi_enable_clock(int port)
* EXTI line 22 is connected to the CMP2 output,
* CHG uses CMP2, and DUT uses CMP1.
*/
#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22))
#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
@ -119,12 +119,12 @@ static inline void pd_tx_spi_reset(int port)
{
if (port == 0) {
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
} else {
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
STM32_RCC_APB1RSTR |= BIT(14);
STM32_RCC_APB1RSTR &= ~BIT(14);
}
}

6
board/twinkie/board.c
View File

@ -34,10 +34,10 @@ void vbus_event(enum gpio_signal signal)
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
/* Remap USART DMA to match the USART driver and TIM2 DMA */
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10) /* Remap USART1 RX/TX DMA */
| (1 << 29);/* Remap TIM2 DMA */
STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */
| BIT(29);/* Remap TIM2 DMA */
/* 40 MHz pin speed on UART PA9/PA10 */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000;
/* 40 MHz pin speed on TX clock out PB9 */

2
board/twinkie/simpletrace.c
View File

@ -223,7 +223,7 @@ void trace_packets(void)
dma_disable(STM32_DMAC_CH7);
task_disable_irq(STM32_IRQ_DMA_CHANNEL_4_7);
/* remove TIM1 CH1/2/3 DMA remapping */
STM32_SYSCFG_CFGR1 &= ~(1 << 28);
STM32_SYSCFG_CFGR1 &= ~BIT(28);
#endif
/* "classical" PD RX configuration */

4
board/twinkie/sniffer.c
View File

@ -256,7 +256,7 @@ static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx)
void sniffer_init(void)
{
/* remap TIM1 CH1/2/3 to DMA channel 6 */
STM32_SYSCFG_CFGR1 |= 1 << 28;
STM32_SYSCFG_CFGR1 |= BIT(28);
/* TIM1 CH1 for CC1 RX */
rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1),
@ -266,7 +266,7 @@ void sniffer_init(void)
TIM_RX2_CCR_IDX, 2);
/* turn on COMP/SYSCFG */
STM32_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= BIT(0);
STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
STM32_COMP_CMP1INSEL_VREF12 |
STM32_COMP_CMP1OUTSEL_TIM1_IC1 |

6
board/twinkie/usb_pd_config.h
View File

@ -51,7 +51,7 @@ static inline void spi_enable_clock(int port)
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
#define EXTI_COMP_MASK(p) (BIT(21) | BIT(22))
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
@ -71,8 +71,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */

46
board/zinger/hardware.c
View File

@ -17,12 +17,12 @@
static void system_init(void)
{
/* Enable access to RCC CSR register and RTC backup registers */
STM32_PWR_CR |= 1 << 8;
STM32_PWR_CR |= BIT(8);
/* switch on LSI */
STM32_RCC_CSR |= 1 << 0;
STM32_RCC_CSR |= BIT(0);
/* Wait for LSI to be ready */
while (!(STM32_RCC_CSR & (1 << 1)))
while (!(STM32_RCC_CSR & BIT(1)))
;
/* re-configure RTC if needed */
if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) {
@ -108,7 +108,7 @@ static void adc_init(void)
;
}
/* Single conversion, right aligned, 12-bit */
STM32_ADC_CFGR1 = 1 << 12; /* (1 << 15) => AUTOOFF */;
STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */;
/* clock is ADCCLK (ADEN must be off when writing this reg) */
STM32_ADC_CFGR2 = 0;
/* Sampling time : 71.5 ADC clock cycles, about 5us */
@ -172,9 +172,9 @@ void hardware_init(void)
power_init();
/* Clear the hardware reset cause by setting the RMVF bit */
STM32_RCC_CSR |= 1 << 24;
STM32_RCC_CSR |= BIT(24);
/* Clear SBF in PWR_CSR */
STM32_PWR_CR |= 1 << 3;
STM32_PWR_CR |= BIT(3);
/*
* WORKAROUND: as we cannot de-activate the watchdog during
@ -206,7 +206,7 @@ static int adc_enable_last_watchdog(void)
static inline int adc_watchdog_enabled(void)
{
return STM32_ADC_CFGR1 & (1 << 23);
return STM32_ADC_CFGR1 & BIT(23);
}
int adc_read_channel(enum adc_channel ch)
@ -222,9 +222,9 @@ int adc_read_channel(enum adc_channel ch)
/* Clear flags */
STM32_ADC_ISR = 0x8e;
/* Start conversion */
STM32_ADC_CR |= 1 << 2; /* ADSTART */
STM32_ADC_CR |= BIT(2); /* ADSTART */
/* Wait for end of conversion */
while (!(STM32_ADC_ISR & (1 << 2)))
while (!(STM32_ADC_ISR & BIT(2)))
;
/* read converted value */
value = STM32_ADC_DR;
@ -249,12 +249,12 @@ int adc_enable_watchdog(int ch, int high, int low)
/* Clear flags */
STM32_ADC_ISR = 0x8e;
/* Set Watchdog enable bit on a single channel / continuous mode */
STM32_ADC_CFGR1 = (ch << 26) | (1 << 23) | (1 << 22)
| (1 << 13) | (1 << 12);
STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22)
| BIT(13) | BIT(12);
/* Enable watchdog interrupt */
STM32_ADC_IER = 1 << 7;
STM32_ADC_IER = BIT(7);
/* Start continuous conversion */
STM32_ADC_CR |= 1 << 2; /* ADSTART */
STM32_ADC_CR |= BIT(2); /* ADSTART */
return EC_SUCCESS;
}
@ -262,12 +262,12 @@ int adc_enable_watchdog(int ch, int high, int low)
int adc_disable_watchdog(void)
{
/* Stop on-going conversion */
STM32_ADC_CR |= 1 << 4; /* ADSTP */
STM32_ADC_CR |= BIT(4); /* ADSTP */
/* Wait for conversion to stop */
while (STM32_ADC_CR & (1 << 4))
while (STM32_ADC_CR & BIT(4))
;
/* CONT=0 -> continuous mode off / Clear Watchdog enable */
STM32_ADC_CFGR1 = 1 << 12;
STM32_ADC_CFGR1 = BIT(12);
/* Disable interrupt */
STM32_ADC_IER = 0;
/* Clear flags */
@ -294,13 +294,13 @@ int adc_disable_watchdog(void)
#define KEY2 0xCDEF89AB
/* Lock bits for FLASH_CR register */
#define PG (1<<0)
#define PER (1<<1)
#define OPTPG (1<<4)
#define OPTER (1<<5)
#define STRT (1<<6)
#define CR_LOCK (1<<7)
#define OPTWRE (1<<9)
#define PG BIT(0)
#define PER BIT(1)
#define OPTPG BIT(4)
#define OPTER BIT(5)
#define STRT BIT(6)
#define CR_LOCK BIT(7)
#define OPTWRE BIT(9)
int flash_physical_write(int offset, int size, const char *data)
{

10
board/zinger/runtime.c
View File

@ -94,19 +94,19 @@ DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1);
static void zinger_config_hispeed_clock(void)
{
/* Ensure that HSI8 is ON */
if (!(STM32_RCC_CR & (1 << 1))) {
if (!(STM32_RCC_CR & BIT(1))) {
/* Enable HSI */
STM32_RCC_CR |= 1 << 0;
STM32_RCC_CR |= BIT(0);
/* Wait for HSI to be ready */
while (!(STM32_RCC_CR & (1 << 1)))
while (!(STM32_RCC_CR & BIT(1)))
;
}
/* PLLSRC = HSI, PLLMUL = x12 (x HSI/2) = 48Mhz */
STM32_RCC_CFGR = 0x00288000;
/* Enable PLL */
STM32_RCC_CR |= 1 << 24;
STM32_RCC_CR |= BIT(24);
/* Wait for PLL to be ready */
while (!(STM32_RCC_CR & (1 << 25)))
while (!(STM32_RCC_CR & BIT(25)))
;
/* switch SYSCLK to PLL */

8
board/zinger/usb_pd_config.h
View File

@ -47,7 +47,7 @@ static inline void spi_enable_clock(int port)
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
/* connect TIM3 CH1 to TIM3_CH2 input */
#define TIM_CCR_CS 2
#define EXTI_COMP_MASK(p) (1 << 7)
#define EXTI_COMP_MASK(p) BIT(7)
#define IRQ_COMP STM32_IRQ_EXTI4_15
/* the RX is inverted, triggers on rising edge */
#define EXTI_XTSR STM32_EXTI_RTSR
@ -64,8 +64,8 @@ static inline void pd_set_pins_speed(int port)
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
STM32_RCC_APB2RSTR |= BIT(12);
STM32_RCC_APB2RSTR &= ~BIT(12);
}
/* Drive the CC line from the TX block */
@ -81,7 +81,7 @@ static inline void pd_tx_enable(int port, int polarity)
static inline void pd_tx_disable(int port, int polarity)
{
/* Put TX GND (PA4) in Hi-Z state */
STM32_GPIO_BSRR(GPIO_A) = 1 << 4 /* Set */;
STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */;
/* Put SPI MISO (PA6) in Hi-Z by putting it in input mode */
STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6));
}

2
board/zinger/usb_pd_policy.c
View File

@ -70,7 +70,7 @@ static enum faults fault;
static timestamp_t fault_deadline;
/* ADC in 12-bit mode */
#define ADC_SCALE (1 << 12)
#define ADC_SCALE BIT(12)
/* ADC power supply : VDDA = 3.3V */
#define VDDA_MV 3300
/* Current sense resistor : 5 milliOhm */

2
chip/g/dcrypto/gcm.c
View File

@ -46,7 +46,7 @@ static void gcm_init_iv(
if (iv_len == 12) {
memcpy(counter, iv, 12);
counter[3] = 1 << 24;
counter[3] = BIT(24);
} else {
size_t i;
uint32_t len = iv_len;

8
chip/g/gpio.c
View File

@ -426,10 +426,10 @@ static void show_pinmux(const char *name, int i, int ofs)
ccprintf("%08x: %s%-2d %2d %s%s%s%s ",
GC_PINMUX_BASE_ADDR + i * 8 + ofs,
name, i, sel,
(ctl & (1<<2)) ? " IN" : "",
(ctl & (1<<3)) ? " PD" : "",
(ctl & (1<<4)) ? " PU" : "",
(ctl & (1<<5)) ? " INV" : "");
(ctl & BIT(2)) ? " IN" : "",
(ctl & BIT(3)) ? " PD" : "",
(ctl & BIT(4)) ? " PU" : "",
(ctl & BIT(5)) ? " INV" : "");
print_periph(sel);

2
chip/g/i2cs.c
View File

@ -73,7 +73,7 @@
#include "task.h"
#include "tpm_log.h"
#define REGISTER_FILE_SIZE (1 << 6) /* 64 bytes. */
#define REGISTER_FILE_SIZE BIT(6) /* 64 bytes. */
#define REGISTER_FILE_MASK (REGISTER_FILE_SIZE - 1)
/* Console output macros */

2
chip/g/idle.c
View File

@ -202,7 +202,7 @@ static void idle_init(void)
* If bus obfuscation is enabled disable sleep.
*/
if ((GR_FUSE(OBFUSCATION_EN) == 5) ||
(GR_FUSE(FW_DEFINED_BROM_APPLYSEC) & (1 << 3)) ||
(GR_FUSE(FW_DEFINED_BROM_APPLYSEC) & BIT(3)) ||
(runlevel_is_high() && GREAD(GLOBALSEC, OBFS_SW_EN))) {
CPRINTS("bus obfuscation enabled disabling sleep");
idle_default = IDLE_WFI;

4
chip/g/ite_flash.c
View File

@ -47,8 +47,8 @@ void generate_ite_sync(void)
* 1 to be able to generate two necessary waveforms.
*/
both_zero = 0;
one_zero = 1 << 13;
zero_one = 1 << 12;
one_zero = BIT(13);
zero_one = BIT(12);
both_one = one_zero | zero_one;
/* Address of the mask byte register to use to set both pins. */

2
chip/g/pmu.c
View File

@ -10,7 +10,7 @@
* RC Trim constants
*/
#define RCTRIM_RESOLUTION (12)
#define RCTRIM_LOAD_VAL (1 << 11)
#define RCTRIM_LOAD_VAL BIT(11)
#define RCTRIM_RANGE_MAX (7 * 7)
#define RCTRIM_RANGE_MIN (-8 * 7)
#define RCTRIM_RANGE (RCTRIM_RANGE_MAX - RCTRIM_RANGE_MIN + 1)

40
chip/g/registers.h
View File

@ -387,7 +387,7 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer,
*/
#define GP_OUT(v) (GC_USB_GGPIO_GPO_MASK & ((v) << GC_USB_GGPIO_GPO_LSB))
#define GP_IN(v) (GC_USB_GGPIO_GPI_MASK & ((v) << GC_USB_GGPIO_GPI_LSB))
#define GGPIO_WRITE(reg, val) GP_OUT(((1 << 15) | /* write bit */ \
#define GGPIO_WRITE(reg, val) GP_OUT((BIT(15) | /* write bit */ \
(((val) & 0xFF) << 4) | /* value */ \
((reg) & 0x0F))) /* register */
#define GGPIO_READ(reg) GP_OUT((reg) & 0x0F) /* register */
@ -399,14 +399,14 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer,
#define USB_SEL_PHY0 0x00 /* bit 0 */
#define USB_SEL_PHY1 0x01 /* bit 0 */
#define USB_IDLE_PHY_CTRL_REG 1 /* register number */
#define USB_FS_SUSPENDB (1 << 7)
#define USB_FS_EDGE_SEL (1 << 6)
#define USB_DM_PULLUP_EN (1 << 5)
#define USB_DP_RPU2_ENB (1 << 4)
#define USB_DP_RPU1_ENB (1 << 3)
#define USB_TX_OEB (1 << 2)
#define USB_TX_DPO (1 << 1)
#define USB_TX_DMO (1 << 0)
#define USB_FS_SUSPENDB BIT(7)
#define USB_FS_EDGE_SEL BIT(6)
#define USB_DM_PULLUP_EN BIT(5)
#define USB_DP_RPU2_ENB BIT(4)
#define USB_DP_RPU1_ENB BIT(3)
#define USB_TX_OEB BIT(2)
#define USB_TX_DPO BIT(1)
#define USB_TX_DMO BIT(0)
#define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB)
#define GAHBCFG_GLB_INTR_EN (1 << GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
@ -515,8 +515,8 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer,
#define DXEPCTL_USBACTEP (1 << GC_USB_DIEPCTL0_USBACTEP_LSB)
#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB)
#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
#define DXEPCTL_SET_D0PID (1 << 28)
#define DXEPCTL_SET_D1PID (1 << 29)
#define DXEPCTL_SET_D0PID BIT(28)
#define DXEPCTL_SET_D1PID BIT(29)
#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
@ -528,12 +528,12 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer,
#define DOEPDMA_BS_HOST_BSY (3 << 30)
#define DOEPDMA_BS_MASK (3 << 30)
#define DOEPDMA_RXSTS_MASK (3 << 28)
#define DOEPDMA_LAST (1 << 27)
#define DOEPDMA_SP (1 << 26)
#define DOEPDMA_IOC (1 << 25)
#define DOEPDMA_SR (1 << 24)
#define DOEPDMA_MTRF (1 << 23)
#define DOEPDMA_NAK (1 << 16)
#define DOEPDMA_LAST BIT(27)
#define DOEPDMA_SP BIT(26)
#define DOEPDMA_IOC BIT(25)
#define DOEPDMA_SR BIT(24)
#define DOEPDMA_MTRF BIT(23)
#define DOEPDMA_NAK BIT(16)
#define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0)
#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0)
@ -543,9 +543,9 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer,
#define DIEPDMA_BS_HOST_BSY (3 << 30)
#define DIEPDMA_BS_MASK (3 << 30)
#define DIEPDMA_TXSTS_MASK (3 << 28)
#define DIEPDMA_LAST (1 << 27)
#define DIEPDMA_SP (1 << 26)
#define DIEPDMA_IOC (1 << 25)
#define DIEPDMA_LAST BIT(27)
#define DIEPDMA_SP BIT(26)
#define DIEPDMA_IOC BIT(25)
#define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0)
#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0)

2
chip/g/signed_header.h
View File

@ -100,7 +100,7 @@ BUILD_ASSERT(offsetof(struct SignedHeader, info_chk_) == 1020);
*
* This convention is enforced at the key generation time.
*/
#define G_SIGNED_FOR_PROD(h) ((h)->keyid & (1 << 2))
#define G_SIGNED_FOR_PROD(h) ((h)->keyid & BIT(2))
#endif /* __CROS_EC_SIGNED_HEADER_H */

2
chip/g/sps.h
View File

@ -19,7 +19,7 @@ enum sps_mode {
};
/* Receive and transmit FIFO size and mask. */
#define SPS_FIFO_SIZE (1 << 10)
#define SPS_FIFO_SIZE BIT(10)
#define SPS_FIFO_MASK (SPS_FIFO_SIZE - 1)
/*

6
chip/g/usb_spi.h
View File

@ -77,9 +77,9 @@ enum usb_spi_request {
/* USB SPI device bitmasks */
enum usb_spi {
USB_SPI_DISABLE = 0,
USB_SPI_AP = (1 << 0),
USB_SPI_EC = (1 << 1),
USB_SPI_H1 = (1 << 2),
USB_SPI_AP = BIT(0),
USB_SPI_EC = BIT(1),
USB_SPI_H1 = BIT(2),
USB_SPI_ALL = USB_SPI_AP | USB_SPI_EC | USB_SPI_H1
};

2
chip/host/host_test.h
View File

@ -9,7 +9,7 @@
#define __CROS_EC_HOST_TEST_H
/* Emulator exit codes */
#define EXIT_CODE_HIBERNATE (1 << 7)
#define EXIT_CODE_HIBERNATE BIT(7)
/* Get emulator executable name */
const char *__get_prog_name(void);

2
chip/ish/host_command_heci.c
View File

@ -114,7 +114,7 @@ static int heci_get_protocol_info(struct host_cmd_handler_args *args)
struct ec_response_get_protocol_info *r = args->response;
memset(r, 0, sizeof(*r));
r->protocol_versions = (1 << 3);
r->protocol_versions = BIT(3);
r->max_request_packet_size = HECI_CROS_EC_LIMIT_PACKET_SIZE;
r->max_response_packet_size = HECI_CROS_EC_RESPONSE_MAX;

6
chip/ish/hpet.h
View File

@ -48,9 +48,9 @@
* Use this register to see HPET timer are settled after a write.
*/
#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160)
#define HPET_T1_CMP_SETTLING (1 << 8)
#define HPET_T1_CAP_SETTLING (1 << 5)
#define HPET_MAIN_COUNTER_SETTLING (1 << 2)
#define HPET_T1_CMP_SETTLING BIT(8)
#define HPET_T1_CAP_SETTLING BIT(5)
#define HPET_MAIN_COUNTER_SETTLING BIT(2)
#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | \
HPET_T1_CMP_SETTLING)

28
chip/ish/ipc_heci.c
View File

@ -58,25 +58,25 @@
#define MNG_ILLEGAL_CMD 0xFF
/* Peripheral Interrupt Satus Register */
#define IPC_PISR_HOST2ISH_BIT (1<<0)
#define IPC_PISR_PMC2ISH_BIT (1<<1)
#define IPC_PISR_CSME2ISH_BIT (1<<2)
#define IPC_PISR_HOST2ISH_BIT BIT(0)
#define IPC_PISR_PMC2ISH_BIT BIT(1)
#define IPC_PISR_CSME2ISH_BIT BIT(2)
/* Peripheral Interrupt Mask Register */
#define IPC_PIMR_HOST2ISH_BIT (1<<0)
#define IPC_PIMR_PMC2ISH_BIT (1<<1)
#define IPC_PIMR_CSME2ISH_BIT (1<<2)
#define IPC_PIMR_HOST2ISH_BIT BIT(0)
#define IPC_PIMR_PMC2ISH_BIT BIT(1)
#define IPC_PIMR_CSME2ISH_BIT BIT(2)
#define IPC_PIMR_ISH2HOST_CLR_BIT (1<<11)
#define IPC_PIMR_ISH2PMC_CLR_BIT (1<<12)
#define IPC_PIMR_ISH2CSME_CLR_BIT (1<<13)
#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11)
#define IPC_PIMR_ISH2PMC_CLR_BIT BIT(12)
#define IPC_PIMR_ISH2CSME_CLR_BIT BIT(13)
/* Peripheral Interrupt DB(DoorBell) Clear Status Register */
#define IPC_DB_CLR_STS_ISH2HOST_BIT (1<<0)
#define IPC_DB_CLR_STS_ISH2ISP_BIT (1<<2)
#define IPC_DB_CLR_STS_ISH2AUDIO_BIT (1<<3)
#define IPC_DB_CLR_STS_ISH2PMC_BIT (1<<8)
#define IPC_DB_CLR_STS_ISH2CSME_BIT (1<<16)
#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0)
#define IPC_DB_CLR_STS_ISH2ISP_BIT BIT(2)
#define IPC_DB_CLR_STS_ISH2AUDIO_BIT BIT(3)
#define IPC_DB_CLR_STS_ISH2PMC_BIT BIT(8)
#define IPC_DB_CLR_STS_ISH2CSME_BIT BIT(16)
/* Doorbell */
#define IPC_DB_MSG_LENGTH_FIELD 0x3FF

10
chip/ish/ish_i2c.h
View File

@ -154,11 +154,11 @@ enum {
TX_BUFFER_DEPTH_OFFSET = 16,
RX_BUFFER_DEPTH_OFFSET = 8,
/* IC_INTR_MASK VALUES */
M_RX_FULL = (1 << 2),
M_TX_EMPTY = (1 << 4),
M_TX_ABRT = (1 << 6),
M_STOP_DET = (1 << 9),
M_START_DET = (1 << 10),
M_RX_FULL = BIT(2),
M_TX_EMPTY = BIT(4),
M_TX_ABRT = BIT(6),
M_STOP_DET = BIT(9),
M_START_DET = BIT(10),
IC_INTR_WRITE_MASK_VAL = (M_STOP_DET | M_TX_ABRT),
IC_INTR_READ_MASK_VAL = (M_RX_FULL | M_TX_ABRT),
DISABLE_INT = 0,

12
chip/ish/registers.h
View File

@ -122,15 +122,15 @@ enum ish_i2c_port {
/* PMU Registers */
#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c)
#define VNN_REQ_IPC_HOST_WRITE (1 << 3) /* Power for IPC host write */
#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */
#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40)
#define PMU_VNN_REQ_ACK_STATUS (1 << 0) /* VNN req and ack status */
#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */
#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c)
#define PMU_RST_PREP_GET (1 << 0)
#define PMU_RST_PREP_AVAIL (1 << 1)
#define PMU_RST_PREP_INT_MASK (1 << 31)
#define PMU_RST_PREP_GET BIT(0)
#define PMU_RST_PREP_AVAIL BIT(1)
#define PMU_RST_PREP_INT_MASK BIT(31)
/* CCU Registers */
#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0)
@ -163,7 +163,7 @@ enum ish_i2c_port {
#define LAPIC_ISR_REG 0xFEE00170
#define LAPIC_IRR_REG (ISH_LAPIC_BASE + 0x200)
#define LAPIC_ESR_REG (ISH_LAPIC_BASE + 0x280)
#define LAPIC_ERR_RECV_ILLEGAL (1 << 6)
#define LAPIC_ERR_RECV_ILLEGAL BIT(6)
#define LAPIC_ICR_REG (ISH_LAPIC_BASE + 0x300)
#endif /* __CROS_EC_REGISTERS_H */

6
chip/ish/uart_defs.h
View File

@ -150,20 +150,20 @@
/* UART config flag, send to sc_io_control if the current UART line has HW
* flow control lines connected.
*/
#define UART_CONFIG_HW_FLOW_CONTROL (1<<0)
#define UART_CONFIG_HW_FLOW_CONTROL BIT(0)
/* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is
* raised only when the rx buffer is completely full. Otherwise, the event
* is raised after a timeout is received on the UART line,
* and all data received until now is provided.
*/
#define UART_CONFIG_DELIVER_FULL_RX_BUF (1<<1)
#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1)
/* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted
* is raised when all rx buffers that were added are full. Otherwise, no
* event is raised.
*/
#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF (1<<2)
#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2)
#define UART_INT_DEVICES 2
#define UART_EXT_DEVICES 8

4
chip/it83xx/adc.c
View File

@ -222,8 +222,8 @@ static void adc_init(void)
* NOTE: A sample time delay (60us) also need to be included in
* conversion time, so the final result is ~= 121.6us.
*/
IT83XX_ADC_ADCSTS &= ~(1 << 7);
IT83XX_ADC_ADCCFG &= ~(1 << 5);
IT83XX_ADC_ADCSTS &= ~BIT(7);
IT83XX_ADC_ADCCFG &= ~BIT(5);
IT83XX_ADC_ADCCTL = 1;
task_waiting = TASK_ID_INVALID;

24
chip/it83xx/clock.c
View File

@ -62,11 +62,11 @@ struct clock_gate_ctrl {
static void clock_module_disable(void)
{
/* bit0: FSPI interface tri-state */
IT83XX_SMFI_FLHCTRL3R |= (1 << 0);
IT83XX_SMFI_FLHCTRL3R |= BIT(0);
/* bit7: USB pad power-on disable */
IT83XX_GCTRL_PMER2 &= ~(1 << 7);
IT83XX_GCTRL_PMER2 &= ~BIT(7);
/* bit7: USB debug disable */
IT83XX_GCTRL_MCCR &= ~(1 << 7);
IT83XX_GCTRL_MCCR &= ~BIT(7);
clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
@ -146,7 +146,7 @@ void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode)
void __ram_code clock_pll_changed(void)
{
IT83XX_GCTRL_SSCR &= ~(1 << 0);
IT83XX_GCTRL_SSCR &= ~BIT(0);
/*
* Update PLL settings.
* Writing data to this register doesn't change the
@ -199,7 +199,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
* We have to set chip select pin as input mode in order to
* change PLL.
*/
IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | (1 << 7);
IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7);
#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
/*
* On DX version, we have to disable eSPI pad before changing
@ -281,10 +281,10 @@ void clock_init(void)
clock_module_disable();
#ifdef CONFIG_HOSTCMD_X86
IT83XX_WUC_WUESR4 = (1 << 2);
IT83XX_WUC_WUESR4 = BIT(2);
task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
/* bit2, wake-up enable for LPC access */
IT83XX_WUC_WUENR4 |= (1 << 2);
IT83XX_WUC_WUENR4 |= BIT(2);
#endif
}
@ -349,7 +349,7 @@ void clock_refresh_console_in_use(void)
static void clock_event_timer_clock_change(enum ext_timer_clock_source clock,
uint32_t count)
{
IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0);
IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock;
IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count;
IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3;
@ -370,7 +370,7 @@ static void clock_htimer_enable(void)
static int clock_allow_low_power_idle(void)
{
if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0)))
if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)))
return 0;
if (*et_ctrl_regs[EVENT_EXT_TIMER].isr &
@ -412,7 +412,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
chip_clear_pending_irq(i);
}
/* bit5: watchdog is disabled. */
IT83XX_ETWD_ETWCTRL |= (1 << 5);
IT83XX_ETWD_ETWCTRL |= BIT(5);
/* Setup GPIOs for hibernate */
if (board_hibernate_late)
board_hibernate_late();
@ -501,7 +501,7 @@ defined(CONFIG_HOSTCMD_ESPI)
#ifdef CONFIG_HOSTCMD_X86
/* disable lpc access wui */
task_disable_irq(IT83XX_IRQ_WKINTAD);
IT83XX_WUC_WUESR4 = (1 << 2);
IT83XX_WUC_WUESR4 = BIT(2);
task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
#endif
/* disable uart wui */
@ -534,7 +534,7 @@ void __idle(void)
/* Check if the EC can enter deep doze mode or not */
if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) {
/* reset low power mode hw timer */
IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= (1 << 1);
IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1);
sleep_mode_t0 = get_time();
#ifdef CONFIG_HOSTCMD_X86
/* enable lpc access wui */

26
chip/it83xx/ec2i.c
View File

@ -160,9 +160,9 @@ enum ec2i_access {
enum ec2i_status_mask {
/* 1: EC read-access is still processing. */
EC2I_STATUS_CRIB = (1 << 1),
EC2I_STATUS_CRIB = BIT(1),
/* 1: EC write-access is still processing with IHD register. */
EC2I_STATUS_CWIB = (1 << 2),
EC2I_STATUS_CWIB = BIT(2),
EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
};
@ -179,7 +179,7 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data)
int rv = EC_ERROR_UNKNOWN;
/* bit1 : VCC power on */
if (IT83XX_SWUC_SWCTL1 & (1 << 1)) {
if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
/*
* Wait that both CRIB and CWIB bits in IBCTL register
* are cleared.
@ -191,15 +191,15 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data)
/* Write the data to IHD register */
IT83XX_EC2I_IHD = data;
/* Enable EC access to the PNPCFG registers */
IT83XX_EC2I_IBMAE |= (1 << 0);
IT83XX_EC2I_IBMAE |= BIT(0);
/* bit0: EC to I-Bus access enabled. */
IT83XX_EC2I_IBCTL |= (1 << 0);
IT83XX_EC2I_IBCTL |= BIT(0);
/* Wait the CWIB bit in IBCTL cleared. */
rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB);
/* Disable EC access to the PNPCFG registers. */
IT83XX_EC2I_IBMAE &= ~(1 << 0);
IT83XX_EC2I_IBMAE &= ~BIT(0);
/* Disable EC to I-Bus access. */
IT83XX_EC2I_IBCTL &= ~(1 << 0);
IT83XX_EC2I_IBCTL &= ~BIT(0);
}
}
@ -212,7 +212,7 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
uint8_t ihd = 0;
/* bit1 : VCC power on */
if (IT83XX_SWUC_SWCTL1 & (1 << 1)) {
if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
/*
* Wait that both CRIB and CWIB bits in IBCTL register
* are cleared.
@ -222,19 +222,19 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
/* Set indirect host I/O offset. */
IT83XX_EC2I_IHIOA = sel;
/* Enable EC access to the PNPCFG registers */
IT83XX_EC2I_IBMAE |= (1 << 0);
IT83XX_EC2I_IBMAE |= BIT(0);
/* bit1: a read-action */
IT83XX_EC2I_IBCTL |= (1 << 1);
IT83XX_EC2I_IBCTL |= BIT(1);
/* bit0: EC to I-Bus access enabled. */
IT83XX_EC2I_IBCTL |= (1 << 0);
IT83XX_EC2I_IBCTL |= BIT(0);
/* Wait the CRIB bit in IBCTL cleared. */
rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB);
/* Read the data from IHD register */
ihd = IT83XX_EC2I_IHD;
/* Disable EC access to the PNPCFG registers. */
IT83XX_EC2I_IBMAE &= ~(1 << 0);
IT83XX_EC2I_IBMAE &= ~BIT(0);
/* Disable EC to I-Bus access. */
IT83XX_EC2I_IBCTL &= ~(1 << 0);
IT83XX_EC2I_IBCTL &= ~BIT(0);
}
}

20
chip/it83xx/espi.c
View File

@ -431,7 +431,7 @@ void __ram_code espi_fw_reset_module(void)
* 01b: The VCC power status is treated as power-on.
*/
IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0);
IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | (1 << 6);
IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | BIT(6);
}
#endif
@ -457,9 +457,9 @@ static int espi_get_reset_enable_config(void)
* 10b: espi_reset# is enabled on GPD2.
* 11b: reset is disabled.
*/
if (espi_rst->port == GPIO_D && espi_rst->mask == (1 << 2)) {
if (espi_rst->port == GPIO_D && espi_rst->mask == BIT(2)) {
config = IT83XX_GPIO_GCR_LPC_RST_D2;
} else if (espi_rst->port == GPIO_B && espi_rst->mask == (1 << 7)) {
} else if (espi_rst->port == GPIO_B && espi_rst->mask == BIT(7)) {
config = IT83XX_GPIO_GCR_LPC_RST_B7;
} else {
config = IT83XX_GPIO_GCR_LPC_RST_DISABLE;
@ -575,10 +575,10 @@ void espi_enable_pad(int enable)
{
if (enable)
/* Enable eSPI pad. */
IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6);
IT83XX_ESPI_ESGCTRL2 &= ~BIT(6);
else
/* Disable eSPI pad. */
IT83XX_ESPI_ESGCTRL2 |= (1 << 6);
IT83XX_ESPI_ESGCTRL2 |= BIT(6);
}
#endif
@ -593,7 +593,7 @@ void espi_init(void)
* 100b: 66MHz
*/
#ifdef IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | (1 << 2);
IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2);
#endif
/* reset vw_index_flag at initialization */
espi_reset_vw_index_flags();
@ -602,16 +602,16 @@ void espi_init(void)
* bit[3]: The reset source of PNPCFG is RSTPNP bit in RSTCH
* register and WRST#.
*/
IT83XX_GCTRL_RSTS &= ~(1 << 3);
IT83XX_GCTRL_RSTS &= ~BIT(3);
task_clear_pending_irq(IT83XX_IRQ_ESPI_VW);
/* bit7: VW interrupt enable */
IT83XX_ESPI_VWCTRL0 |= (1 << 7);
IT83XX_ESPI_VWCTRL0 |= BIT(7);
task_enable_irq(IT83XX_IRQ_ESPI_VW);
/* bit7: eSPI interrupt enable */
IT83XX_ESPI_ESGCTRL1 |= (1 << 7);
IT83XX_ESPI_ESGCTRL1 |= BIT(7);
/* bit4: eSPI to WUC enable */
IT83XX_ESPI_ESGCTRL2 |= (1 << 4);
IT83XX_ESPI_ESGCTRL2 |= BIT(4);
task_enable_irq(IT83XX_IRQ_ESPI);
/* enable interrupt and reset from eSPI_reset# */

424
chip/it83xx/gpio.c
View File

@ -100,111 +100,111 @@ static const struct {
uint8_t wuc_mask;
} gpio_irqs[] = {
/* irq gpio_port,gpio_mask,wuc_group,wuc_mask */
[IT83XX_IRQ_WKO20] = {GPIO_D, (1<<0), 2, (1<<0)},
[IT83XX_IRQ_WKO21] = {GPIO_D, (1<<1), 2, (1<<1)},
[IT83XX_IRQ_WKO22] = {GPIO_C, (1<<4), 2, (1<<2)},
[IT83XX_IRQ_WKO23] = {GPIO_C, (1<<6), 2, (1<<3)},
[IT83XX_IRQ_WKO24] = {GPIO_D, (1<<2), 2, (1<<4)},
[IT83XX_IRQ_WKO20] = {GPIO_D, BIT(0), 2, BIT(0)},
[IT83XX_IRQ_WKO21] = {GPIO_D, BIT(1), 2, BIT(1)},
[IT83XX_IRQ_WKO22] = {GPIO_C, BIT(4), 2, BIT(2)},
[IT83XX_IRQ_WKO23] = {GPIO_C, BIT(6), 2, BIT(3)},
[IT83XX_IRQ_WKO24] = {GPIO_D, BIT(2), 2, BIT(4)},
#ifdef IT83XX_GPIO_INT_FLEXIBLE
[IT83XX_IRQ_WKO40] = {GPIO_E, (1<<5), 4, (1<<0)},
[IT83XX_IRQ_WKO45] = {GPIO_E, (1<<6), 4, (1<<5)},
[IT83XX_IRQ_WKO46] = {GPIO_E, (1<<7), 4, (1<<6)},
[IT83XX_IRQ_WKO40] = {GPIO_E, BIT(5), 4, BIT(0)},
[IT83XX_IRQ_WKO45] = {GPIO_E, BIT(6), 4, BIT(5)},
[IT83XX_IRQ_WKO46] = {GPIO_E, BIT(7), 4, BIT(6)},
#endif
[IT83XX_IRQ_WKO50] = {GPIO_K, (1<<0), 5, (1<<0)},
[IT83XX_IRQ_WKO51] = {GPIO_K, (1<<1), 5, (1<<1)},
[IT83XX_IRQ_WKO52] = {GPIO_K, (1<<2), 5, (1<<2)},
[IT83XX_IRQ_WKO53] = {GPIO_K, (1<<3), 5, (1<<3)},
[IT83XX_IRQ_WKO54] = {GPIO_K, (1<<4), 5, (1<<4)},
[IT83XX_IRQ_WKO55] = {GPIO_K, (1<<5), 5, (1<<5)},
[IT83XX_IRQ_WKO56] = {GPIO_K, (1<<6), 5, (1<<6)},
[IT83XX_IRQ_WKO57] = {GPIO_K, (1<<7), 5, (1<<7)},
[IT83XX_IRQ_WKO60] = {GPIO_H, (1<<0), 6, (1<<0)},
[IT83XX_IRQ_WKO61] = {GPIO_H, (1<<1), 6, (1<<1)},
[IT83XX_IRQ_WKO62] = {GPIO_H, (1<<2), 6, (1<<2)},
[IT83XX_IRQ_WKO63] = {GPIO_H, (1<<3), 6, (1<<3)},
[IT83XX_IRQ_WKO64] = {GPIO_F, (1<<4), 6, (1<<4)},
[IT83XX_IRQ_WKO65] = {GPIO_F, (1<<5), 6, (1<<5)},
[IT83XX_IRQ_WKO65] = {GPIO_F, (1<<6), 6, (1<<6)},
[IT83XX_IRQ_WKO67] = {GPIO_F, (1<<7), 6, (1<<7)},
[IT83XX_IRQ_WKO70] = {GPIO_E, (1<<0), 7, (1<<0)},
[IT83XX_IRQ_WKO71] = {GPIO_E, (1<<1), 7, (1<<1)},
[IT83XX_IRQ_WKO72] = {GPIO_E, (1<<2), 7, (1<<2)},
[IT83XX_IRQ_WKO73] = {GPIO_E, (1<<3), 7, (1<<3)},
[IT83XX_IRQ_WKO74] = {GPIO_I, (1<<4), 7, (1<<4)},
[IT83XX_IRQ_WKO75] = {GPIO_I, (1<<5), 7, (1<<5)},
[IT83XX_IRQ_WKO76] = {GPIO_I, (1<<6), 7, (1<<6)},
[IT83XX_IRQ_WKO77] = {GPIO_I, (1<<7), 7, (1<<7)},
[IT83XX_IRQ_WKO80] = {GPIO_A, (1<<3), 8, (1<<0)},
[IT83XX_IRQ_WKO81] = {GPIO_A, (1<<4), 8, (1<<1)},
[IT83XX_IRQ_WKO82] = {GPIO_A, (1<<5), 8, (1<<2)},
[IT83XX_IRQ_WKO83] = {GPIO_A, (1<<6), 8, (1<<3)},
[IT83XX_IRQ_WKO84] = {GPIO_B, (1<<2), 8, (1<<4)},
[IT83XX_IRQ_WKO85] = {GPIO_C, (1<<0), 8, (1<<5)},
[IT83XX_IRQ_WKO86] = {GPIO_C, (1<<7), 8, (1<<6)},
[IT83XX_IRQ_WKO87] = {GPIO_D, (1<<7), 8, (1<<7)},
[IT83XX_IRQ_WKO88] = {GPIO_H, (1<<4), 9, (1<<0)},
[IT83XX_IRQ_WKO89] = {GPIO_H, (1<<5), 9, (1<<1)},
[IT83XX_IRQ_WKO90] = {GPIO_H, (1<<6), 9, (1<<2)},
[IT83XX_IRQ_WKO91] = {GPIO_A, (1<<0), 9, (1<<3)},
[IT83XX_IRQ_WKO92] = {GPIO_A, (1<<1), 9, (1<<4)},
[IT83XX_IRQ_WKO93] = {GPIO_A, (1<<2), 9, (1<<5)},
[IT83XX_IRQ_WKO94] = {GPIO_B, (1<<4), 9, (1<<6)},
[IT83XX_IRQ_WKO95] = {GPIO_C, (1<<2), 9, (1<<7)},
[IT83XX_IRQ_WKO96] = {GPIO_F, (1<<0), 10, (1<<0)},
[IT83XX_IRQ_WKO97] = {GPIO_F, (1<<1), 10, (1<<1)},
[IT83XX_IRQ_WKO98] = {GPIO_F, (1<<2), 10, (1<<2)},
[IT83XX_IRQ_WKO99] = {GPIO_F, (1<<3), 10, (1<<3)},
[IT83XX_IRQ_WKO100] = {GPIO_A, (1<<7), 10, (1<<4)},
[IT83XX_IRQ_WKO101] = {GPIO_B, (1<<0), 10, (1<<5)},
[IT83XX_IRQ_WKO102] = {GPIO_B, (1<<1), 10, (1<<6)},
[IT83XX_IRQ_WKO103] = {GPIO_B, (1<<3), 10, (1<<7)},
[IT83XX_IRQ_WKO104] = {GPIO_B, (1<<5), 11, (1<<0)},
[IT83XX_IRQ_WKO105] = {GPIO_B, (1<<6), 11, (1<<1)},
[IT83XX_IRQ_WKO106] = {GPIO_B, (1<<7), 11, (1<<2)},
[IT83XX_IRQ_WKO107] = {GPIO_C, (1<<1), 11, (1<<3)},
[IT83XX_IRQ_WKO108] = {GPIO_C, (1<<3), 11, (1<<4)},
[IT83XX_IRQ_WKO109] = {GPIO_C, (1<<5), 11, (1<<5)},
[IT83XX_IRQ_WKO110] = {GPIO_D, (1<<3), 11, (1<<6)},
[IT83XX_IRQ_WKO111] = {GPIO_D, (1<<4), 11, (1<<7)},
[IT83XX_IRQ_WKO112] = {GPIO_D, (1<<5), 12, (1<<0)},
[IT83XX_IRQ_WKO113] = {GPIO_D, (1<<6), 12, (1<<1)},
[IT83XX_IRQ_WKO114] = {GPIO_E, (1<<4), 12, (1<<2)},
[IT83XX_IRQ_WKO115] = {GPIO_G, (1<<0), 12, (1<<3)},
[IT83XX_IRQ_WKO116] = {GPIO_G, (1<<1), 12, (1<<4)},
[IT83XX_IRQ_WKO117] = {GPIO_G, (1<<2), 12, (1<<5)},
[IT83XX_IRQ_WKO118] = {GPIO_G, (1<<6), 12, (1<<6)},
[IT83XX_IRQ_WKO119] = {GPIO_I, (1<<0), 12, (1<<7)},
[IT83XX_IRQ_WKO120] = {GPIO_I, (1<<1), 13, (1<<0)},
[IT83XX_IRQ_WKO121] = {GPIO_I, (1<<2), 13, (1<<1)},
[IT83XX_IRQ_WKO122] = {GPIO_I, (1<<3), 13, (1<<2)},
[IT83XX_IRQ_WKO50] = {GPIO_K, BIT(0), 5, BIT(0)},
[IT83XX_IRQ_WKO51] = {GPIO_K, BIT(1), 5, BIT(1)},
[IT83XX_IRQ_WKO52] = {GPIO_K, BIT(2), 5, BIT(2)},
[IT83XX_IRQ_WKO53] = {GPIO_K, BIT(3), 5, BIT(3)},
[IT83XX_IRQ_WKO54] = {GPIO_K, BIT(4), 5, BIT(4)},
[IT83XX_IRQ_WKO55] = {GPIO_K, BIT(5), 5, BIT(5)},
[IT83XX_IRQ_WKO56] = {GPIO_K, BIT(6), 5, BIT(6)},
[IT83XX_IRQ_WKO57] = {GPIO_K, BIT(7), 5, BIT(7)},
[IT83XX_IRQ_WKO60] = {GPIO_H, BIT(0), 6, BIT(0)},
[IT83XX_IRQ_WKO61] = {GPIO_H, BIT(1), 6, BIT(1)},
[IT83XX_IRQ_WKO62] = {GPIO_H, BIT(2), 6, BIT(2)},
[IT83XX_IRQ_WKO63] = {GPIO_H, BIT(3), 6, BIT(3)},
[IT83XX_IRQ_WKO64] = {GPIO_F, BIT(4), 6, BIT(4)},
[IT83XX_IRQ_WKO65] = {GPIO_F, BIT(5), 6, BIT(5)},
[IT83XX_IRQ_WKO65] = {GPIO_F, BIT(6), 6, BIT(6)},
[IT83XX_IRQ_WKO67] = {GPIO_F, BIT(7), 6, BIT(7)},
[IT83XX_IRQ_WKO70] = {GPIO_E, BIT(0), 7, BIT(0)},
[IT83XX_IRQ_WKO71] = {GPIO_E, BIT(1), 7, BIT(1)},
[IT83XX_IRQ_WKO72] = {GPIO_E, BIT(2), 7, BIT(2)},
[IT83XX_IRQ_WKO73] = {GPIO_E, BIT(3), 7, BIT(3)},
[IT83XX_IRQ_WKO74] = {GPIO_I, BIT(4), 7, BIT(4)},
[IT83XX_IRQ_WKO75] = {GPIO_I, BIT(5), 7, BIT(5)},
[IT83XX_IRQ_WKO76] = {GPIO_I, BIT(6), 7, BIT(6)},
[IT83XX_IRQ_WKO77] = {GPIO_I, BIT(7), 7, BIT(7)},
[IT83XX_IRQ_WKO80] = {GPIO_A, BIT(3), 8, BIT(0)},
[IT83XX_IRQ_WKO81] = {GPIO_A, BIT(4), 8, BIT(1)},
[IT83XX_IRQ_WKO82] = {GPIO_A, BIT(5), 8, BIT(2)},
[IT83XX_IRQ_WKO83] = {GPIO_A, BIT(6), 8, BIT(3)},
[IT83XX_IRQ_WKO84] = {GPIO_B, BIT(2), 8, BIT(4)},
[IT83XX_IRQ_WKO85] = {GPIO_C, BIT(0), 8, BIT(5)},
[IT83XX_IRQ_WKO86] = {GPIO_C, BIT(7), 8, BIT(6)},
[IT83XX_IRQ_WKO87] = {GPIO_D, BIT(7), 8, BIT(7)},
[IT83XX_IRQ_WKO88] = {GPIO_H, BIT(4), 9, BIT(0)},
[IT83XX_IRQ_WKO89] = {GPIO_H, BIT(5), 9, BIT(1)},
[IT83XX_IRQ_WKO90] = {GPIO_H, BIT(6), 9, BIT(2)},
[IT83XX_IRQ_WKO91] = {GPIO_A, BIT(0), 9, BIT(3)},
[IT83XX_IRQ_WKO92] = {GPIO_A, BIT(1), 9, BIT(4)},
[IT83XX_IRQ_WKO93] = {GPIO_A, BIT(2), 9, BIT(5)},
[IT83XX_IRQ_WKO94] = {GPIO_B, BIT(4), 9, BIT(6)},
[IT83XX_IRQ_WKO95] = {GPIO_C, BIT(2), 9, BIT(7)},
[IT83XX_IRQ_WKO96] = {GPIO_F, BIT(0), 10, BIT(0)},
[IT83XX_IRQ_WKO97] = {GPIO_F, BIT(1), 10, BIT(1)},
[IT83XX_IRQ_WKO98] = {GPIO_F, BIT(2), 10, BIT(2)},
[IT83XX_IRQ_WKO99] = {GPIO_F, BIT(3), 10, BIT(3)},
[IT83XX_IRQ_WKO100] = {GPIO_A, BIT(7), 10, BIT(4)},
[IT83XX_IRQ_WKO101] = {GPIO_B, BIT(0), 10, BIT(5)},
[IT83XX_IRQ_WKO102] = {GPIO_B, BIT(1), 10, BIT(6)},
[IT83XX_IRQ_WKO103] = {GPIO_B, BIT(3), 10, BIT(7)},
[IT83XX_IRQ_WKO104] = {GPIO_B, BIT(5), 11, BIT(0)},
[IT83XX_IRQ_WKO105] = {GPIO_B, BIT(6), 11, BIT(1)},
[IT83XX_IRQ_WKO106] = {GPIO_B, BIT(7), 11, BIT(2)},
[IT83XX_IRQ_WKO107] = {GPIO_C, BIT(1), 11, BIT(3)},
[IT83XX_IRQ_WKO108] = {GPIO_C, BIT(3), 11, BIT(4)},
[IT83XX_IRQ_WKO109] = {GPIO_C, BIT(5), 11, BIT(5)},
[IT83XX_IRQ_WKO110] = {GPIO_D, BIT(3), 11, BIT(6)},
[IT83XX_IRQ_WKO111] = {GPIO_D, BIT(4), 11, BIT(7)},
[IT83XX_IRQ_WKO112] = {GPIO_D, BIT(5), 12, BIT(0)},
[IT83XX_IRQ_WKO113] = {GPIO_D, BIT(6), 12, BIT(1)},
[IT83XX_IRQ_WKO114] = {GPIO_E, BIT(4), 12, BIT(2)},
[IT83XX_IRQ_WKO115] = {GPIO_G, BIT(0), 12, BIT(3)},
[IT83XX_IRQ_WKO116] = {GPIO_G, BIT(1), 12, BIT(4)},
[IT83XX_IRQ_WKO117] = {GPIO_G, BIT(2), 12, BIT(5)},
[IT83XX_IRQ_WKO118] = {GPIO_G, BIT(6), 12, BIT(6)},
[IT83XX_IRQ_WKO119] = {GPIO_I, BIT(0), 12, BIT(7)},
[IT83XX_IRQ_WKO120] = {GPIO_I, BIT(1), 13, BIT(0)},
[IT83XX_IRQ_WKO121] = {GPIO_I, BIT(2), 13, BIT(1)},
[IT83XX_IRQ_WKO122] = {GPIO_I, BIT(3), 13, BIT(2)},
#ifdef IT83XX_GPIO_INT_FLEXIBLE
[IT83XX_IRQ_WKO123] = {GPIO_G, (1<<3), 13, (1<<3)},
[IT83XX_IRQ_WKO124] = {GPIO_G, (1<<4), 13, (1<<4)},
[IT83XX_IRQ_WKO125] = {GPIO_G, (1<<5), 13, (1<<5)},
[IT83XX_IRQ_WKO126] = {GPIO_G, (1<<7), 13, (1<<6)},
[IT83XX_IRQ_WKO123] = {GPIO_G, BIT(3), 13, BIT(3)},
[IT83XX_IRQ_WKO124] = {GPIO_G, BIT(4), 13, BIT(4)},
[IT83XX_IRQ_WKO125] = {GPIO_G, BIT(5), 13, BIT(5)},
[IT83XX_IRQ_WKO126] = {GPIO_G, BIT(7), 13, BIT(6)},
#endif
[IT83XX_IRQ_WKO128] = {GPIO_J, (1<<0), 14, (1<<0)},
[IT83XX_IRQ_WKO129] = {GPIO_J, (1<<1), 14, (1<<1)},
[IT83XX_IRQ_WKO130] = {GPIO_J, (1<<2), 14, (1<<2)},
[IT83XX_IRQ_WKO131] = {GPIO_J, (1<<3), 14, (1<<3)},
[IT83XX_IRQ_WKO132] = {GPIO_J, (1<<4), 14, (1<<4)},
[IT83XX_IRQ_WKO133] = {GPIO_J, (1<<5), 14, (1<<5)},
[IT83XX_IRQ_WKO136] = {GPIO_L, (1<<0), 15, (1<<0)},
[IT83XX_IRQ_WKO137] = {GPIO_L, (1<<1), 15, (1<<1)},
[IT83XX_IRQ_WKO138] = {GPIO_L, (1<<2), 15, (1<<2)},
[IT83XX_IRQ_WKO139] = {GPIO_L, (1<<3), 15, (1<<3)},
[IT83XX_IRQ_WKO140] = {GPIO_L, (1<<4), 15, (1<<4)},
[IT83XX_IRQ_WKO141] = {GPIO_L, (1<<5), 15, (1<<5)},
[IT83XX_IRQ_WKO142] = {GPIO_L, (1<<6), 15, (1<<6)},
[IT83XX_IRQ_WKO143] = {GPIO_L, (1<<7), 15, (1<<7)},
[IT83XX_IRQ_WKO128] = {GPIO_J, BIT(0), 14, BIT(0)},
[IT83XX_IRQ_WKO129] = {GPIO_J, BIT(1), 14, BIT(1)},
[IT83XX_IRQ_WKO130] = {GPIO_J, BIT(2), 14, BIT(2)},
[IT83XX_IRQ_WKO131] = {GPIO_J, BIT(3), 14, BIT(3)},
[IT83XX_IRQ_WKO132] = {GPIO_J, BIT(4), 14, BIT(4)},
[IT83XX_IRQ_WKO133] = {GPIO_J, BIT(5), 14, BIT(5)},
[IT83XX_IRQ_WKO136] = {GPIO_L, BIT(0), 15, BIT(0)},
[IT83XX_IRQ_WKO137] = {GPIO_L, BIT(1), 15, BIT(1)},
[IT83XX_IRQ_WKO138] = {GPIO_L, BIT(2), 15, BIT(2)},
[IT83XX_IRQ_WKO139] = {GPIO_L, BIT(3), 15, BIT(3)},
[IT83XX_IRQ_WKO140] = {GPIO_L, BIT(4), 15, BIT(4)},
[IT83XX_IRQ_WKO141] = {GPIO_L, BIT(5), 15, BIT(5)},
[IT83XX_IRQ_WKO142] = {GPIO_L, BIT(6), 15, BIT(6)},
[IT83XX_IRQ_WKO143] = {GPIO_L, BIT(7), 15, BIT(7)},
#ifdef IT83XX_GPIO_INT_FLEXIBLE
[IT83XX_IRQ_WKO144] = {GPIO_M, (1<<0), 16, (1<<0)},
[IT83XX_IRQ_WKO145] = {GPIO_M, (1<<1), 16, (1<<1)},
[IT83XX_IRQ_WKO146] = {GPIO_M, (1<<2), 16, (1<<2)},
[IT83XX_IRQ_WKO147] = {GPIO_M, (1<<3), 16, (1<<3)},
[IT83XX_IRQ_WKO148] = {GPIO_M, (1<<4), 16, (1<<4)},
[IT83XX_IRQ_WKO149] = {GPIO_M, (1<<5), 16, (1<<5)},
[IT83XX_IRQ_WKO150] = {GPIO_M, (1<<6), 16, (1<<6)},
[IT83XX_IRQ_WKO144] = {GPIO_M, BIT(0), 16, BIT(0)},
[IT83XX_IRQ_WKO145] = {GPIO_M, BIT(1), 16, BIT(1)},
[IT83XX_IRQ_WKO146] = {GPIO_M, BIT(2), 16, BIT(2)},
[IT83XX_IRQ_WKO147] = {GPIO_M, BIT(3), 16, BIT(3)},
[IT83XX_IRQ_WKO148] = {GPIO_M, BIT(4), 16, BIT(4)},
[IT83XX_IRQ_WKO149] = {GPIO_M, BIT(5), 16, BIT(5)},
[IT83XX_IRQ_WKO150] = {GPIO_M, BIT(6), 16, BIT(6)},
#endif
[IT83XX_IRQ_COUNT-1] = {0, 0, 0, 0},
};
@ -238,119 +238,119 @@ struct gpio_1p8v_t {
static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
#ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED
[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)},
[5] = {&IT83XX_GPIO_GRC24, (1 << 1)},
[6] = {&IT83XX_GPIO_GRC24, (1 << 5)},
[7] = {&IT83XX_GPIO_GRC24, (1 << 6)} },
[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)},
[4] = {&IT83XX_GPIO_GRC22, (1 << 0)},
[5] = {&IT83XX_GPIO_GRC19, (1 << 7)},
[6] = {&IT83XX_GPIO_GRC19, (1 << 6)},
[7] = {&IT83XX_GPIO_GRC24, (1 << 4)} },
[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, (1 << 7)},
[1] = {&IT83XX_GPIO_GRC19, (1 << 5)},
[2] = {&IT83XX_GPIO_GRC19, (1 << 4)},
[4] = {&IT83XX_GPIO_GRC24, (1 << 2)},
[6] = {&IT83XX_GPIO_GRC24, (1 << 3)},
[7] = {&IT83XX_GPIO_GRC19, (1 << 3)} },
[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)},
[1] = {&IT83XX_GPIO_GRC19, (1 << 1)},
[2] = {&IT83XX_GPIO_GRC19, (1 << 0)},
[3] = {&IT83XX_GPIO_GRC20, (1 << 7)},
[4] = {&IT83XX_GPIO_GRC20, (1 << 6)},
[5] = {&IT83XX_GPIO_GRC22, (1 << 4)},
[6] = {&IT83XX_GPIO_GRC22, (1 << 5)},
[7] = {&IT83XX_GPIO_GRC22, (1 << 6)} },
[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)},
[1] = {&IT83XX_GPIO_GCR28, (1 << 6)},
[2] = {&IT83XX_GPIO_GCR28, (1 << 7)},
[4] = {&IT83XX_GPIO_GRC22, (1 << 2)},
[5] = {&IT83XX_GPIO_GRC22, (1 << 3)},
[6] = {&IT83XX_GPIO_GRC20, (1 << 4)},
[7] = {&IT83XX_GPIO_GRC20, (1 << 3)} },
[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 4)},
[1] = {&IT83XX_GPIO_GCR28, (1 << 5)},
[2] = {&IT83XX_GPIO_GRC20, (1 << 2)},
[3] = {&IT83XX_GPIO_GRC20, (1 << 1)},
[4] = {&IT83XX_GPIO_GRC20, (1 << 0)},
[5] = {&IT83XX_GPIO_GRC21, (1 << 7)},
[6] = {&IT83XX_GPIO_GRC21, (1 << 6)},
[7] = {&IT83XX_GPIO_GRC21, (1 << 5)} },
[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 2)},
[1] = {&IT83XX_GPIO_GRC21, (1 << 4)},
[2] = {&IT83XX_GPIO_GCR28, (1 << 3)},
[6] = {&IT83XX_GPIO_GRC21, (1 << 3)} },
[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)},
[1] = {&IT83XX_GPIO_GRC21, (1 << 1)},
[2] = {&IT83XX_GPIO_GRC21, (1 << 0)},
[5] = {&IT83XX_GPIO_GCR27, (1 << 7)},
[6] = {&IT83XX_GPIO_GCR28, (1 << 0)} },
[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, (1 << 3)},
[1] = {&IT83XX_GPIO_GRC23, (1 << 4)},
[2] = {&IT83XX_GPIO_GRC23, (1 << 5)},
[3] = {&IT83XX_GPIO_GRC23, (1 << 6)},
[4] = {&IT83XX_GPIO_GRC23, (1 << 7)},
[5] = {&IT83XX_GPIO_GCR27, (1 << 4)},
[6] = {&IT83XX_GPIO_GCR27, (1 << 5)},
[7] = {&IT83XX_GPIO_GCR27, (1 << 6)} },
[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)},
[1] = {&IT83XX_GPIO_GRC23, (1 << 1)},
[2] = {&IT83XX_GPIO_GRC23, (1 << 2)},
[3] = {&IT83XX_GPIO_GRC23, (1 << 3)},
[4] = {&IT83XX_GPIO_GCR27, (1 << 0)},
[5] = {&IT83XX_GPIO_GCR27, (1 << 1)},
[6] = {&IT83XX_GPIO_GCR27, (1 << 2)} },
[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, (1 << 0)},
[1] = {&IT83XX_GPIO_GCR26, (1 << 1)},
[2] = {&IT83XX_GPIO_GCR26, (1 << 2)},
[3] = {&IT83XX_GPIO_GCR26, (1 << 3)},
[4] = {&IT83XX_GPIO_GCR26, (1 << 4)},
[5] = {&IT83XX_GPIO_GCR26, (1 << 5)},
[6] = {&IT83XX_GPIO_GCR26, (1 << 6)},
[7] = {&IT83XX_GPIO_GCR26, (1 << 7)} },
[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, (1 << 0)},
[1] = {&IT83XX_GPIO_GCR25, (1 << 1)},
[2] = {&IT83XX_GPIO_GCR25, (1 << 2)},
[3] = {&IT83XX_GPIO_GCR25, (1 << 3)},
[4] = {&IT83XX_GPIO_GCR25, (1 << 4)},
[5] = {&IT83XX_GPIO_GCR25, (1 << 5)},
[6] = {&IT83XX_GPIO_GCR25, (1 << 6)},
[7] = {&IT83XX_GPIO_GCR25, (1 << 7)} },
[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
[5] = {&IT83XX_GPIO_GRC24, BIT(1)},
[6] = {&IT83XX_GPIO_GRC24, BIT(5)},
[7] = {&IT83XX_GPIO_GRC24, BIT(6)} },
[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
[4] = {&IT83XX_GPIO_GRC22, BIT(0)},
[5] = {&IT83XX_GPIO_GRC19, BIT(7)},
[6] = {&IT83XX_GPIO_GRC19, BIT(6)},
[7] = {&IT83XX_GPIO_GRC24, BIT(4)} },
[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)},
[1] = {&IT83XX_GPIO_GRC19, BIT(5)},
[2] = {&IT83XX_GPIO_GRC19, BIT(4)},
[4] = {&IT83XX_GPIO_GRC24, BIT(2)},
[6] = {&IT83XX_GPIO_GRC24, BIT(3)},
[7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
[1] = {&IT83XX_GPIO_GRC19, BIT(1)},
[2] = {&IT83XX_GPIO_GRC19, BIT(0)},
[3] = {&IT83XX_GPIO_GRC20, BIT(7)},
[4] = {&IT83XX_GPIO_GRC20, BIT(6)},
[5] = {&IT83XX_GPIO_GRC22, BIT(4)},
[6] = {&IT83XX_GPIO_GRC22, BIT(5)},
[7] = {&IT83XX_GPIO_GRC22, BIT(6)} },
[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
[1] = {&IT83XX_GPIO_GCR28, BIT(6)},
[2] = {&IT83XX_GPIO_GCR28, BIT(7)},
[4] = {&IT83XX_GPIO_GRC22, BIT(2)},
[5] = {&IT83XX_GPIO_GRC22, BIT(3)},
[6] = {&IT83XX_GPIO_GRC20, BIT(4)},
[7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)},
[1] = {&IT83XX_GPIO_GCR28, BIT(5)},
[2] = {&IT83XX_GPIO_GRC20, BIT(2)},
[3] = {&IT83XX_GPIO_GRC20, BIT(1)},
[4] = {&IT83XX_GPIO_GRC20, BIT(0)},
[5] = {&IT83XX_GPIO_GRC21, BIT(7)},
[6] = {&IT83XX_GPIO_GRC21, BIT(6)},
[7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)},
[1] = {&IT83XX_GPIO_GRC21, BIT(4)},
[2] = {&IT83XX_GPIO_GCR28, BIT(3)},
[6] = {&IT83XX_GPIO_GRC21, BIT(3)} },
[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
[1] = {&IT83XX_GPIO_GRC21, BIT(1)},
[2] = {&IT83XX_GPIO_GRC21, BIT(0)},
[5] = {&IT83XX_GPIO_GCR27, BIT(7)},
[6] = {&IT83XX_GPIO_GCR28, BIT(0)} },
[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)},
[1] = {&IT83XX_GPIO_GRC23, BIT(4)},
[2] = {&IT83XX_GPIO_GRC23, BIT(5)},
[3] = {&IT83XX_GPIO_GRC23, BIT(6)},
[4] = {&IT83XX_GPIO_GRC23, BIT(7)},
[5] = {&IT83XX_GPIO_GCR27, BIT(4)},
[6] = {&IT83XX_GPIO_GCR27, BIT(5)},
[7] = {&IT83XX_GPIO_GCR27, BIT(6)} },
[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
[1] = {&IT83XX_GPIO_GRC23, BIT(1)},
[2] = {&IT83XX_GPIO_GRC23, BIT(2)},
[3] = {&IT83XX_GPIO_GRC23, BIT(3)},
[4] = {&IT83XX_GPIO_GCR27, BIT(0)},
[5] = {&IT83XX_GPIO_GCR27, BIT(1)},
[6] = {&IT83XX_GPIO_GCR27, BIT(2)} },
[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)},
[1] = {&IT83XX_GPIO_GCR26, BIT(1)},
[2] = {&IT83XX_GPIO_GCR26, BIT(2)},
[3] = {&IT83XX_GPIO_GCR26, BIT(3)},
[4] = {&IT83XX_GPIO_GCR26, BIT(4)},
[5] = {&IT83XX_GPIO_GCR26, BIT(5)},
[6] = {&IT83XX_GPIO_GCR26, BIT(6)},
[7] = {&IT83XX_GPIO_GCR26, BIT(7)} },
[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)},
[1] = {&IT83XX_GPIO_GCR25, BIT(1)},
[2] = {&IT83XX_GPIO_GCR25, BIT(2)},
[3] = {&IT83XX_GPIO_GCR25, BIT(3)},
[4] = {&IT83XX_GPIO_GCR25, BIT(4)},
[5] = {&IT83XX_GPIO_GCR25, BIT(5)},
[6] = {&IT83XX_GPIO_GCR25, BIT(6)},
[7] = {&IT83XX_GPIO_GCR25, BIT(7)} },
#else
[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)},
[5] = {&IT83XX_GPIO_GRC24, (1 << 1)} },
[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)},
[4] = {&IT83XX_GPIO_GRC22, (1 << 0)},
[5] = {&IT83XX_GPIO_GRC19, (1 << 7)},
[6] = {&IT83XX_GPIO_GRC19, (1 << 6)} },
[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, (1 << 5)},
[2] = {&IT83XX_GPIO_GRC19, (1 << 4)},
[7] = {&IT83XX_GPIO_GRC19, (1 << 3)} },
[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)},
[1] = {&IT83XX_GPIO_GRC19, (1 << 1)},
[2] = {&IT83XX_GPIO_GRC19, (1 << 0)},
[3] = {&IT83XX_GPIO_GRC20, (1 << 7)},
[4] = {&IT83XX_GPIO_GRC20, (1 << 6)} },
[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)},
[6] = {&IT83XX_GPIO_GRC20, (1 << 4)},
[7] = {&IT83XX_GPIO_GRC20, (1 << 3)} },
[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, (1 << 2)},
[3] = {&IT83XX_GPIO_GRC20, (1 << 1)},
[4] = {&IT83XX_GPIO_GRC20, (1 << 0)},
[5] = {&IT83XX_GPIO_GRC21, (1 << 7)},
[6] = {&IT83XX_GPIO_GRC21, (1 << 6)},
[7] = {&IT83XX_GPIO_GRC21, (1 << 5)} },
[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)},
[1] = {&IT83XX_GPIO_GRC21, (1 << 1)},
[2] = {&IT83XX_GPIO_GRC21, (1 << 0)} },
[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, (1 << 4)},
[2] = {&IT83XX_GPIO_GRC23, (1 << 5)},
[3] = {&IT83XX_GPIO_GRC23, (1 << 6)},
[4] = {&IT83XX_GPIO_GRC23, (1 << 7)} },
[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)},
[1] = {&IT83XX_GPIO_GRC23, (1 << 1)},
[2] = {&IT83XX_GPIO_GRC23, (1 << 2)},
[3] = {&IT83XX_GPIO_GRC23, (1 << 3)} },
[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
[5] = {&IT83XX_GPIO_GRC24, BIT(1)} },
[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
[4] = {&IT83XX_GPIO_GRC22, BIT(0)},
[5] = {&IT83XX_GPIO_GRC19, BIT(7)},
[6] = {&IT83XX_GPIO_GRC19, BIT(6)} },
[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
[2] = {&IT83XX_GPIO_GRC19, BIT(4)},
[7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
[1] = {&IT83XX_GPIO_GRC19, BIT(1)},
[2] = {&IT83XX_GPIO_GRC19, BIT(0)},
[3] = {&IT83XX_GPIO_GRC20, BIT(7)},
[4] = {&IT83XX_GPIO_GRC20, BIT(6)} },
[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
[6] = {&IT83XX_GPIO_GRC20, BIT(4)},
[7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
[3] = {&IT83XX_GPIO_GRC20, BIT(1)},
[4] = {&IT83XX_GPIO_GRC20, BIT(0)},
[5] = {&IT83XX_GPIO_GRC21, BIT(7)},
[6] = {&IT83XX_GPIO_GRC21, BIT(6)},
[7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
[1] = {&IT83XX_GPIO_GRC21, BIT(1)},
[2] = {&IT83XX_GPIO_GRC21, BIT(0)} },
[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
[2] = {&IT83XX_GPIO_GRC23, BIT(5)},
[3] = {&IT83XX_GPIO_GRC23, BIT(6)},
[4] = {&IT83XX_GPIO_GRC23, BIT(7)} },
[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
[1] = {&IT83XX_GPIO_GRC23, BIT(1)},
[2] = {&IT83XX_GPIO_GRC23, BIT(2)},
[3] = {&IT83XX_GPIO_GRC23, BIT(3)} },
#endif
};

12
chip/it83xx/hwtimer.c
View File

@ -81,7 +81,7 @@ static void free_run_timer_overflow(void)
/* set timer counter register */
IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff;
/* bit[1], timer reset */
IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1);
IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
}
/* w/c interrupt status */
task_clear_pending_irq(et_ctrl_regs[FREE_EXT_TIMER_H].irq);
@ -114,14 +114,14 @@ void __hw_clock_source_set(uint32_t ts)
/* counting down timer, microseconds to timer counter register */
IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff - ts;
/* bit[1], timer reset */
IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1);
IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
}
void __hw_clock_event_set(uint32_t deadline)
{
uint32_t wait;
/* bit0, disable event timer */
IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0);
IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
/* w/c interrupt status */
event_timer_clear_pending_isr();
/* microseconds to timer counter */
@ -139,7 +139,7 @@ uint32_t __hw_clock_event_get(void)
uint32_t next_event_us = __hw_clock_source_read();
/* bit0, event timer is enabled */
if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0)) {
if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)) {
/* timer counter observation value to microseconds */
next_event_us += EVENT_TIMER_COUNT_TO_US(
#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
@ -161,7 +161,7 @@ void __hw_clock_event_clear(void)
int __hw_clock_source_init(uint32_t start_t)
{
/* bit3, timer 3 and timer 4 combinational mode */
IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 3);
IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(3);
/* init free running timer (timer 4, TIMER_H), clock source is 8mhz */
ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1);
/* 1us counter setting (timer 3, TIMER_L) */
@ -181,7 +181,7 @@ static void __hw_clock_source_irq(void)
/* SW/HW interrupt of event timer. */
if (irq == et_ctrl_regs[EVENT_EXT_TIMER].irq) {
IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = 0xffffffff;
IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= (1 << 1);
IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= BIT(1);
event_timer_clear_pending_isr();
process_timers(0);
return;

4
chip/it83xx/i2c.c
View File

@ -292,7 +292,7 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
if (first_byte) {
/* First byte must be slave address. */
IT83XX_I2C_DTR(p_ch) =
data | (direct == RX_DIRECT ? (1 << 0) : 0);
data | (direct == RX_DIRECT ? BIT(0) : 0);
/* start or repeat start signal. */
IT83XX_I2C_CTR(p_ch) = E_START_ID;
} else {
@ -457,7 +457,7 @@ static void enhanced_i2c_start(int p)
*/
IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT;
/* bit1: Enable enhanced i2c module */
IT83XX_I2C_CTR1(p_ch) = (1 << 1);
IT83XX_I2C_CTR1(p_ch) = BIT(1);
}
static int enhanced_i2c_tran_write(int p)

4
chip/it83xx/keyboard_raw.c
View File

@ -31,7 +31,7 @@ void keyboard_raw_init(void)
#ifdef CONFIG_KEYBOARD_COL2_INVERTED
/* KSO[2] is high, others are low. */
IT83XX_KBS_KSOL = (1 << 2);
IT83XX_KBS_KSOL = BIT(2);
#else
/* KSO[7:0] pins low. */
IT83XX_KBS_KSOL = 0x00;
@ -81,7 +81,7 @@ test_mockable void keyboard_raw_drive_column(int col)
#ifdef CONFIG_KEYBOARD_COL2_INVERTED
/* KSO[2] is inverted. */
mask ^= (1 << 2);
mask ^= BIT(2);
#endif
IT83XX_KBS_KSOL = mask & 0xff;
IT83XX_KBS_KSOH1 = (mask >> 8) & 0xff;

12
chip/it83xx/lpc.c
View File

@ -103,7 +103,7 @@ static void pm_put_data_out(enum lpc_pm_ch ch, uint8_t out)
static void pm_clear_ibf(enum lpc_pm_ch ch)
{
/* bit7, write-1 clear IBF */
IT83XX_PMC_PMIE(ch) |= (1 << 7);
IT83XX_PMC_PMIE(ch) |= BIT(7);
}
#ifdef CONFIG_KEYBOARD_IRQ_GPIO
@ -340,8 +340,8 @@ void lpc_keyboard_clear_buffer(void)
uint32_t int_mask = get_int_mask();
interrupt_disable();
/* bit6, write-1 clear OBF */
IT83XX_KBC_KBHICR |= (1 << 6);
IT83XX_KBC_KBHICR &= ~(1 << 6);
IT83XX_KBC_KBHICR |= BIT(6);
IT83XX_KBC_KBHICR &= ~BIT(6);
set_int_mask(int_mask);
}
@ -392,8 +392,8 @@ void lpc_kbc_ibf_interrupt(void)
keyboard_host_write(IT83XX_KBC_KBHIDIR,
(IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
/* bit7, write-1 clear IBF */
IT83XX_KBC_KBHICR |= (1 << 7);
IT83XX_KBC_KBHICR &= ~(1 << 7);
IT83XX_KBC_KBHICR |= BIT(7);
IT83XX_KBC_KBHICR &= ~BIT(7);
}
task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
@ -745,7 +745,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args)
struct ec_response_get_protocol_info *r = args->response;
memset(r, 0, sizeof(*r));
r->protocol_versions = (1 << 3);
r->protocol_versions = BIT(3);
r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->flags = 0;

130
chip/it83xx/registers.h
View File

@ -1179,26 +1179,26 @@ enum i2c_channels {
#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port)))
#define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0)
#define USBPD_REG_MASK_SW_RESET_BIT (1 << 7)
#define USBPD_REG_MASK_TYPE_C_DETECT_RESET (1 << 6)
#define USBPD_REG_MASK_BMC_PHY (1 << 4)
#define USBPD_REG_MASK_AUTO_SEND_SW_RESET (1 << 3)
#define USBPD_REG_MASK_AUTO_SEND_HW_RESET (1 << 2)
#define USBPD_REG_MASK_SNIFFER_MODE (1 << 1)
#define USBPD_REG_MASK_GLOBAL_ENABLE (1 << 0)
#define USBPD_REG_MASK_SW_RESET_BIT BIT(7)
#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6)
#define USBPD_REG_MASK_BMC_PHY BIT(4)
#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3)
#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2)
#define USBPD_REG_MASK_SNIFFER_MODE BIT(1)
#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0)
#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p)+0x01)
#define USBPD_REG_MASK_SOPPP_ENABLE (1 << 7)
#define USBPD_REG_MASK_SOPP_ENABLE (1 << 6)
#define USBPD_REG_MASK_SOP_ENABLE (1 << 5)
#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7)
#define USBPD_REG_MASK_SOPP_ENABLE BIT(6)
#define USBPD_REG_MASK_SOP_ENABLE BIT(5)
#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x04)
#define USBPD_REG_MASK_DISABLE_CC (1 << 4)
#define USBPD_REG_MASK_DISABLE_CC BIT(4)
#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x05)
#ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT ((1 << 3) | (1 << 1))
#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT ((1 << 7) | (1 << 5))
#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (BIT(3) | BIT(1))
#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (BIT(7) | BIT(5))
#else
#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (1 << 3)
#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (1 << 7)
#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT BIT(3)
#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT BIT(7)
#endif
#define USBPD_CC1_DISCONNECTED(p) \
((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) & \
@ -1208,35 +1208,35 @@ enum i2c_channels {
~IT83XX_USBPD_REG_MASK_CC1_DISCONNECT)
#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06)
#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 (1 << 5)
#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 (1 << 1)
#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5)
#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1)
#define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x08)
#define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x09)
#define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0C)
#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p)+0x14)
#define USBPD_REG_MASK_TYPE_C_DETECT (1 << 7)
#define USBPD_REG_MASK_CABLE_RESET_DETECT (1 << 6)
#define USBPD_REG_MASK_HARD_RESET_DETECT (1 << 5)
#define USBPD_REG_MASK_MSG_RX_DONE (1 << 4)
#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE (1 << 3)
#define USBPD_REG_MASK_HARD_RESET_TX_DONE (1 << 2)
#define USBPD_REG_MASK_MSG_TX_DONE (1 << 1)
#define USBPD_REG_MASK_TIMER_TIMEOUT (1 << 0)
#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7)
#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6)
#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5)
#define USBPD_REG_MASK_MSG_RX_DONE BIT(4)
#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3)
#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(2)
#define USBPD_REG_MASK_MSG_TX_DONE BIT(1)
#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0)
#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p)+0x15)
#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p)+0x18)
#define USBPD_REG_MASK_SW_RESET_TX_STAT (1 << 3)
#define USBPD_REG_MASK_TX_BUSY_STAT (1 << 2)
#define USBPD_REG_MASK_TX_DISCARD_STAT (1 << 2)
#define USBPD_REG_MASK_TX_ERR_STAT (1 << 1)
#define USBPD_REG_MASK_TX_START (1 << 0)
#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3)
#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2)
#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2)
#define USBPD_REG_MASK_TX_ERR_STAT BIT(1)
#define USBPD_REG_MASK_TX_START BIT(0)
#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x19)
#define USBPD_REG_MASK_CABLE_ENABLE (1 << 7)
#define USBPD_REG_MASK_SEND_HW_RESET (1 << 6)
#define USBPD_REG_MASK_SEND_BIST_MODE_2 (1 << 5)
#define USBPD_REG_MASK_CABLE_ENABLE BIT(7)
#define USBPD_REG_MASK_SEND_HW_RESET BIT(6)
#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5)
#define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x1A)
#define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1B)
#define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1C)
#define USBPD_REG_MASK_RX_MSG_VALID (1 << 0)
#define USBPD_REG_MASK_RX_MSG_VALID BIT(0)
#define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p)+0x1D)
#define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p)+0x1E)
#define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p)+0x1F)
@ -1252,11 +1252,11 @@ enum i2c_channels {
#define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p)+0x65)
#ifdef IT83XX_INTC_PLUG_IN_SUPPORT
#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p)+0x67)
#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT (1 << 7)
#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR (1 << 4)
#define USBPD_REG_PLUG_IN_OUT_SELECT (1 << 3)
#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE (1 << 1)
#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT (1 << 0)
#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7)
#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4)
#define USBPD_REG_PLUG_IN_OUT_SELECT BIT(3)
#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1)
#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0)
#endif //IT83XX_INTC_PLUG_IN_SUPPORT
enum usbpd_port {
@ -1283,55 +1283,55 @@ enum usbpd_port {
#define VW_VALID_FIELD(f) ((f) << 4)
#define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2
#define VW_IDX_2_SLP_S3 (1 << 0)
#define VW_IDX_2_SLP_S4 (1 << 1)
#define VW_IDX_2_SLP_S5 (1 << 2)
#define VW_IDX_2_SLP_S3 BIT(0)
#define VW_IDX_2_SLP_S4 BIT(1)
#define VW_IDX_2_SLP_S5 BIT(2)
#define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3
#define VW_IDX_3_SUS_STAT (1 << 0)
#define VW_IDX_3_PLTRST (1 << 1)
#define VW_IDX_3_OOB_RST_WARN (1 << 2)
#define VW_IDX_3_SUS_STAT BIT(0)
#define VW_IDX_3_PLTRST BIT(1)
#define VW_IDX_3_OOB_RST_WARN BIT(2)
#define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4
#define VW_IDX_4_OOB_RST_ACK (1 << 0)
#define VW_IDX_4_WAKE (1 << 2)
#define VW_IDX_4_PME (1 << 3)
#define VW_IDX_4_OOB_RST_ACK BIT(0)
#define VW_IDX_4_WAKE BIT(2)
#define VW_IDX_4_PME BIT(3)
#define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5
#define VW_IDX_5_SLAVE_BTLD_DONE (1 << 0)
#define VW_IDX_5_FATAL (1 << 1)
#define VW_IDX_5_NON_FATAL (1 << 2)
#define VW_IDX_5_SLAVE_BTLD_STATUS (1 << 3)
#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0)
#define VW_IDX_5_FATAL BIT(1)
#define VW_IDX_5_NON_FATAL BIT(2)
#define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3)
#define VW_IDX_5_BTLD_STATUS_DONE (VW_IDX_5_SLAVE_BTLD_DONE | \
VW_IDX_5_SLAVE_BTLD_STATUS)
#define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6
#define VW_IDX_6_SCI (1 << 0)
#define VW_IDX_6_SMI (1 << 1)
#define VW_IDX_6_RCIN (1 << 2)
#define VW_IDX_6_HOST_RST_ACK (1 << 3)
#define VW_IDX_6_SCI BIT(0)
#define VW_IDX_6_SMI BIT(1)
#define VW_IDX_6_RCIN BIT(2)
#define VW_IDX_6_HOST_RST_ACK BIT(3)
#define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7
#define VW_IDX_7_HOST_RST_WARN (1 << 0)
#define VW_IDX_7_HOST_RST_WARN BIT(0)
#define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40
#define VW_IDX_40_SUS_ACK (1 << 0)
#define VW_IDX_40_SUS_ACK BIT(0)
#define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41
#define VW_IDX_41_SUS_WARN (1 << 0)
#define VW_IDX_41_SUS_PWRDN_ACK (1 << 1)
#define VW_IDX_41_SLP_A (1 << 3)
#define VW_IDX_41_SUS_WARN BIT(0)
#define VW_IDX_41_SUS_PWRDN_ACK BIT(1)
#define VW_IDX_41_SLP_A BIT(3)
#define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42
#define VW_IDX_42_SLP_LAN (1 << 0)
#define VW_IDX_42_SLP_WLAN (1 << 1)
#define VW_IDX_42_SLP_LAN BIT(0)
#define VW_IDX_42_SLP_WLAN BIT(1)
#define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43
#define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44
#define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47
#define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE+0x90)
#define ESPI_INTERRUPT_EVENT_PUT_PC (1 << 7)
#define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7)
#define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE+0x91)
#define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE+0x92)
@ -1348,7 +1348,7 @@ enum usbpd_port {
#define IT83XX_USB_BASE 0x00F02F00
#define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE+0xE4)
#define USB_DP_DM_PULL_DOWN_EN (1 << 4)
#define USB_DP_DM_PULL_DOWN_EN BIT(4)
/* Wake pin definitions, defined at board-level */
extern const enum gpio_signal hibernate_wake_pins[];

6
chip/it83xx/system.c
View File

@ -118,7 +118,7 @@ int system_is_reboot_warm(void)
void chip_pre_init(void)
{
/* bit4, enable debug mode through SMBus */
IT83XX_SMB_SLVISELR &= ~(1 << 4);
IT83XX_SMB_SLVISELR &= ~BIT(4);
}
#define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */
@ -189,12 +189,12 @@ void system_reset(int flags)
* If we are in debug mode, we need disable it before triggering
* a soft reset or reset will fail.
*/
IT83XX_SMB_SLVISELR |= (1 << 4);
IT83XX_SMB_SLVISELR |= BIT(4);
/* bit0: enable watchdog hardware reset. */
#ifdef IT83XX_ETWD_HW_RESET_SUPPORT
if (flags & SYSTEM_RESET_HARD)
IT83XX_GCTRL_ETWDUARTCR |= (1 << 0);
IT83XX_GCTRL_ETWDUARTCR |= BIT(0);
#endif
/*
* Writing invalid key to watchdog module triggers a soft or hardware

8
chip/it83xx/uart.c
View File

@ -209,10 +209,10 @@ void uart_init(void)
* bit3: uart1 belongs to the EC side.
* This is necessary for enabling eSPI module.
*/
IT83XX_GCTRL_RSTDMMC |= (1 << 3);
IT83XX_GCTRL_RSTDMMC |= BIT(3);
/* reset uart before config it */
IT83XX_GCTRL_RSTC4 |= (1 << 1);
IT83XX_GCTRL_RSTC4 |= BIT(1);
/* Waiting for when we can use the GPIO module to set pin muxing */
gpio_config_module(MODULE_UART, 1);
@ -229,9 +229,9 @@ void uart_init(void)
#ifdef CONFIG_UART_HOST
/* bit2, reset UART2 */
IT83XX_GCTRL_RSTC4 |= (1 << 2);
IT83XX_GCTRL_RSTC4 |= BIT(2);
/* SIN1/SOUT1 of UART 2 is enabled. */
IT83XX_GPIO_GRC1 |= (1 << 2);
IT83XX_GPIO_GRC1 |= BIT(2);
/* Config UART 2 */
host_uart_config();
#endif

2
chip/it83xx/watchdog.c
View File

@ -100,7 +100,7 @@ int watchdog_init(void)
#ifdef CONFIG_HIBERNATE
/* bit4: watchdog can be stopped. */
IT83XX_ETWD_ETWCTRL |= (1 << 4);
IT83XX_ETWD_ETWCTRL |= BIT(4);
#else
/* Specify that watchdog cannot be stopped. */
IT83XX_ETWD_ETWCTRL = 0x00;

30
chip/lm4/i2c.c
View File

@ -21,22 +21,22 @@
#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
/* Flags for writes to MCS */
#define LM4_I2C_MCS_RUN (1 << 0)
#define LM4_I2C_MCS_START (1 << 1)
#define LM4_I2C_MCS_STOP (1 << 2)
#define LM4_I2C_MCS_ACK (1 << 3)
#define LM4_I2C_MCS_HS (1 << 4)
#define LM4_I2C_MCS_QCMD (1 << 5)
#define LM4_I2C_MCS_RUN BIT(0)
#define LM4_I2C_MCS_START BIT(1)
#define LM4_I2C_MCS_STOP BIT(2)
#define LM4_I2C_MCS_ACK BIT(3)
#define LM4_I2C_MCS_HS BIT(4)
#define LM4_I2C_MCS_QCMD BIT(5)
/* Flags for reads from MCS */
#define LM4_I2C_MCS_BUSY (1 << 0)
#define LM4_I2C_MCS_ERROR (1 << 1)
#define LM4_I2C_MCS_ADRACK (1 << 2)
#define LM4_I2C_MCS_DATACK (1 << 3)
#define LM4_I2C_MCS_ARBLST (1 << 4)
#define LM4_I2C_MCS_IDLE (1 << 5)
#define LM4_I2C_MCS_BUSBSY (1 << 6)
#define LM4_I2C_MCS_CLKTO (1 << 7)
#define LM4_I2C_MCS_BUSY BIT(0)
#define LM4_I2C_MCS_ERROR BIT(1)
#define LM4_I2C_MCS_ADRACK BIT(2)
#define LM4_I2C_MCS_DATACK BIT(3)
#define LM4_I2C_MCS_ARBLST BIT(4)
#define LM4_I2C_MCS_IDLE BIT(5)
#define LM4_I2C_MCS_BUSBSY BIT(6)
#define LM4_I2C_MCS_CLKTO BIT(7)
/*
* Minimum delay between resetting the port or sending a stop condition, and
@ -298,7 +298,7 @@ int i2c_raw_get_sda(int port)
int i2c_get_line_levels(int port)
{
/* Conveniently, MBMON bit (1 << 1) is SDA and (1 << 0) is SCL. */
/* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */
return LM4_I2C_MBMON(port) & 0x03;
}

4
chip/lm4/keyboard_raw.c
View File

@ -34,7 +34,7 @@ void keyboard_raw_init(void)
* When column 2 is inverted, the Silego has a pulldown instead of a
* pullup. So drive it push-pull instead of open-drain.
*/
LM4_GPIO_ODR(LM4_GPIO_P) &= ~(1 << 2);
LM4_GPIO_ODR(LM4_GPIO_P) &= ~BIT(2);
#endif
/* Set row inputs with pull-up */
@ -72,7 +72,7 @@ test_mockable void keyboard_raw_drive_column(int col)
#ifdef CONFIG_KEYBOARD_COL2_INVERTED
/* Invert column 2 output */
mask ^= (1 << 2);
mask ^= BIT(2);
#endif
LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = mask & 0xff;

12
chip/lm4/lpc.c
View File

@ -405,7 +405,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
int lpc_get_pltrst_asserted(void)
{
return (LM4_LPC_LPCSTS & (1<<10)) ? 1 : 0;
return (LM4_LPC_LPCSTS & BIT(10)) ? 1 : 0;
}
/**
@ -594,8 +594,8 @@ void lpc_interrupt(void)
#endif
/* Debugging: print changes to LPC0RESET */
if (mis & (1 << 31)) {
if (LM4_LPC_LPCSTS & (1 << 10)) {
if (mis & BIT(31)) {
if (LM4_LPC_LPCSTS & BIT(10)) {
int i;
/* Store port 80 reset event */
@ -682,7 +682,7 @@ static void lpc_init(void)
* data writes, pool bytes 0(data)/1(cmd)
*/
LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60;
LM4_LPC_CTL(LPC_CH_KEYBOARD) = (1 << 24/* IRQSEL1 */) |
LM4_LPC_CTL(LPC_CH_KEYBOARD) = (BIT(24)/* IRQSEL1 */) |
(0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1));
LM4_LPC_ST(LPC_CH_KEYBOARD) = 0;
/* Unmask interrupt for host command/data writes and data reads */
@ -743,7 +743,7 @@ static void lpc_init(void)
* Unmask LPC bus reset interrupt. This lets us monitor the PCH
* PLTRST# signal for debugging.
*/
LM4_LPC_LPCIM |= (1 << 31);
LM4_LPC_LPCIM |= BIT(31);
/* Enable LPC channels */
LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 |
@ -820,7 +820,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args)
struct ec_response_get_protocol_info *r = args->response;
memset(r, 0, sizeof(*r));
r->protocol_versions = (1 << 2) | (1 << 3);
r->protocol_versions = BIT(2) | BIT(3);
r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->flags = 0;

60
chip/lm4/registers.h
View File

@ -41,11 +41,11 @@ static inline int lm4_spi_addr(int ch, int offset)
#define LM4_SSI_CR1(ch) LM4SSIREG(ch, 0x004)
#define LM4_SSI_DR(ch) LM4SSIREG(ch, 0x008)
#define LM4_SSI_SR(ch) LM4SSIREG(ch, 0x00c)
#define LM4_SSI_SR_TFE (1 << 0) /* Transmit FIFO empty */
#define LM4_SSI_SR_TNF (1 << 1) /* Transmit FIFO not full */
#define LM4_SSI_SR_RNE (1 << 2) /* Receive FIFO not empty */
#define LM4_SSI_SR_RFF (1 << 3) /* Receive FIFO full */
#define LM4_SSI_SR_BSY (1 << 4) /* Busy */
#define LM4_SSI_SR_TFE BIT(0) /* Transmit FIFO empty */
#define LM4_SSI_SR_TNF BIT(1) /* Transmit FIFO not full */
#define LM4_SSI_SR_RNE BIT(2) /* Receive FIFO not empty */
#define LM4_SSI_SR_RFF BIT(3) /* Receive FIFO full */
#define LM4_SSI_SR_BSY BIT(4) /* Busy */
#define LM4_SSI_CPSR(ch) LM4SSIREG(ch, 0x010)
#define LM4_SSI_IM(ch) LM4SSIREG(ch, 0x014)
#define LM4_SSI_RIS(ch) LM4SSIREG(ch, 0x018)
@ -85,7 +85,7 @@ static inline int lm4_adc_addr(int ss, int offset)
#define LM4_ADC_SSEMUX(ss) LM4ADCREG(ss, 0x018)
#define LM4_LPC_LPCCTL REG32(0x40080000)
#define LM4_LPC_SCI_START (1 << 9) /* Start a pulse on LPC0SCI signal */
#define LM4_LPC_SCI_START BIT(9) /* Start a pulse on LPC0SCI signal */
#define LM4_LPC_SCI_CLK_1 (0 << 10) /* SCI asserted for 1 clock period */
#define LM4_LPC_SCI_CLK_2 (1 << 10) /* SCI asserted for 2 clock periods */
#define LM4_LPC_SCI_CLK_4 (2 << 10) /* SCI asserted for 4 clock periods */
@ -115,13 +115,13 @@ static inline int lm4_lpc_addr(int ch, int offset)
#define LM4LPCREG(ch, offset) REG32(lm4_lpc_addr(ch, offset))
#define LM4_LPC_CTL(ch) LM4LPCREG(ch, 0x000)
#define LM4_LPC_ST(ch) LM4LPCREG(ch, 0x004)
#define LM4_LPC_ST_TOH (1 << 0) /* TO Host bit */
#define LM4_LPC_ST_FRMH (1 << 1) /* FRoM Host bit */
#define LM4_LPC_ST_CMD (1 << 3) /* Last from-host byte was command */
#define LM4_LPC_ST_BURST (1 << 8)
#define LM4_LPC_ST_SCI (1 << 9)
#define LM4_LPC_ST_SMI (1 << 10)
#define LM4_LPC_ST_BUSY (1 << 12)
#define LM4_LPC_ST_TOH BIT(0) /* TO Host bit */
#define LM4_LPC_ST_FRMH BIT(1) /* FRoM Host bit */
#define LM4_LPC_ST_CMD BIT(3) /* Last from-host byte was command */
#define LM4_LPC_ST_BURST BIT(8)
#define LM4_LPC_ST_SCI BIT(9)
#define LM4_LPC_ST_SMI BIT(10)
#define LM4_LPC_ST_BUSY BIT(12)
#define LM4_LPC_ADR(ch) LM4LPCREG(ch, 0x008)
#define LM4_LPC_POOL_BYTES 1024 /* Size of LPCPOOL in bytes */
#define LM4_LPC_LPCPOOL ((volatile unsigned char *)0x40080400)
@ -186,12 +186,12 @@ static inline int lm4_fan_addr(int ch, int offset)
#define LM4_HIBERNATE_HIBRTCM0 REG32(0x400fc004)
#define LM4_HIBERNATE_HIBRTCLD REG32(0x400fc00c)
#define LM4_HIBERNATE_HIBCTL REG32(0x400fc010)
#define LM4_HIBCTL_WRC (1 << 31)
#define LM4_HIBCTL_CLK32EN (1 << 6)
#define LM4_HIBCTL_PINWEN (1 << 4)
#define LM4_HIBCTL_RTCWEN (1 << 3)
#define LM4_HIBCTL_HIBREQ (1 << 1)
#define LM4_HIBCTL_RTCEN (1 << 0)
#define LM4_HIBCTL_WRC BIT(31)
#define LM4_HIBCTL_CLK32EN BIT(6)
#define LM4_HIBCTL_PINWEN BIT(4)
#define LM4_HIBCTL_RTCWEN BIT(3)
#define LM4_HIBCTL_HIBREQ BIT(1)
#define LM4_HIBCTL_RTCEN BIT(0)
#define LM4_HIBERNATE_HIBIM REG32(0x400fc014)
#define LM4_HIBERNATE_HIBRIS REG32(0x400fc018)
#define LM4_HIBERNATE_HIBMIS REG32(0x400fc01c)
@ -228,22 +228,22 @@ static inline int lm4_fan_addr(int ch, int offset)
#define LM4_SYSTEM_MISC REG32(0x400fe058)
#define LM4_SYSTEM_RESC REG32(0x400fe05c)
#define LM4_SYSTEM_RCC REG32(0x400fe060)
#define LM4_SYSTEM_RCC_ACG (1 << 27)
#define LM4_SYSTEM_RCC_ACG BIT(27)
#define LM4_SYSTEM_RCC_SYSDIV(x) (((x) & 0xf) << 23)
#define LM4_SYSTEM_RCC_USESYSDIV (1 << 22)
#define LM4_SYSTEM_RCC_PWRDN (1 << 13)
#define LM4_SYSTEM_RCC_BYPASS (1 << 11)
#define LM4_SYSTEM_RCC_USESYSDIV BIT(22)
#define LM4_SYSTEM_RCC_PWRDN BIT(13)
#define LM4_SYSTEM_RCC_BYPASS BIT(11)
#define LM4_SYSTEM_RCC_XTAL(x) (((x) & 0x1f) << 6)
#define LM4_SYSTEM_RCC_OSCSRC(x) (((x) & 0x3) << 4)
#define LM4_SYSTEM_RCC_IOSCDIS (1 << 1)
#define LM4_SYSTEM_RCC_MOSCDIS (1 << 0)
#define LM4_SYSTEM_RCC_IOSCDIS BIT(1)
#define LM4_SYSTEM_RCC_MOSCDIS BIT(0)
#define LM4_SYSTEM_RCC2 REG32(0x400fe070)
#define LM4_SYSTEM_RCC2_USERCC2 (1 << 31)
#define LM4_SYSTEM_RCC2_DIV400 (1 << 30)
#define LM4_SYSTEM_RCC2_USERCC2 BIT(31)
#define LM4_SYSTEM_RCC2_DIV400 BIT(30)
#define LM4_SYSTEM_RCC2_SYSDIV2(x) (((x) & 0x3f) << 23)
#define LM4_SYSTEM_RCC2_SYSDIV2LSB (1 << 22)
#define LM4_SYSTEM_RCC2_PWRDN2 (1 << 13)
#define LM4_SYSTEM_RCC2_BYPASS2 (1 << 11)
#define LM4_SYSTEM_RCC2_SYSDIV2LSB BIT(22)
#define LM4_SYSTEM_RCC2_PWRDN2 BIT(13)
#define LM4_SYSTEM_RCC2_BYPASS2 BIT(11)
#define LM4_SYSTEM_RCC2_OSCSRC2(x) (((x) & 0x7) << 4)
#define LM4_SYSTEM_MOSCCTL REG32(0x400fe07c)
#define LM4_SYSTEM_DSLPCLKCFG REG32(0x400fe144)

6
chip/lm4/system.c
View File

@ -30,9 +30,9 @@ enum hibdata_index {
};
/* Flags for HIBDATA_INDEX_WAKE */
#define HIBDATA_WAKE_RTC (1 << 0) /* RTC alarm */
#define HIBDATA_WAKE_HARD_RESET (1 << 1) /* Hard reset via short RTC alarm */
#define HIBDATA_WAKE_PIN (1 << 2) /* Wake pin */
#define HIBDATA_WAKE_RTC BIT(0) /* RTC alarm */
#define HIBDATA_WAKE_HARD_RESET BIT(1) /* Hard reset via short RTC alarm */
#define HIBDATA_WAKE_PIN BIT(2) /* Wake pin */
/*
* Time to hibernate to trigger a power-on reset. 50 ms is sufficient for the

2
chip/lm4/watchdog.c
View File

@ -101,7 +101,7 @@ int watchdog_init(void)
LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD;
/* De-activate the watchdog when the JTAG stops the CPU */
LM4_WATCHDOG_TEST(0) |= 1 << 8;
LM4_WATCHDOG_TEST(0) |= BIT(8);
/* Reset after 2 time-out, activate the watchdog and lock the control
* register. */

8
chip/mchp/adc.c
View File

@ -50,14 +50,14 @@ static int start_single_and_wait(int timeout)
/* clear all R/W1C channel status */
MCHP_ADC_STS = 0xffffu;
/* clear R/W1C single done status */
MCHP_ADC_CTRL |= (1 << 7);
MCHP_ADC_CTRL |= BIT(7);
/* clear GIRQ single status */
MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
/* make sure all writes are issued before starting conversion */
asm volatile ("dsb");
/* Start conversion */
MCHP_ADC_CTRL |= 1 << 1;
MCHP_ADC_CTRL |= BIT(1);
MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
@ -131,7 +131,7 @@ static void adc_init(void)
MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ADC);
/* Activate ADC module */
MCHP_ADC_CTRL |= 1 << 0;
MCHP_ADC_CTRL |= BIT(0);
/* Enable interrupt */
task_waiting = TASK_ID_INVALID;
@ -148,7 +148,7 @@ void adc_interrupt(void)
MCHP_ADC_STS = 0xffffu;
/* Clear interrupt status bit */
MCHP_ADC_CTRL |= 1 << 7;
MCHP_ADC_CTRL |= BIT(7);
MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;

6
chip/mchp/clock.c
View File

@ -341,7 +341,7 @@ static void prepare_for_deep_sleep(void)
/* Enable assertion of DeepSleep signals
* from the core when core enters sleep.
*/
CPU_SCB_SYSCTRL |= (1 << 2);
CPU_SCB_SYSCTRL |= BIT(2);
/* Stop timers */
MCHP_TMR32_CTL(0) &= ~1;
@ -422,7 +422,7 @@ static void resume_from_deep_sleep(void)
MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */
/* Disable assertion of DeepSleep signal when core executes WFI */
CPU_SCB_SYSCTRL &= ~(1 << 2);
CPU_SCB_SYSCTRL &= ~BIT(2);
#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
print_saved_regs();
@ -483,7 +483,7 @@ static void resume_from_deep_sleep(void)
#ifdef CONFIG_WATCHDOG
#ifdef CONFIG_CHIPSET_DEBUG
/* enable WDG stall on active JTAG and do not start */
MCHP_WDG_CTL = (1 << 4);
MCHP_WDG_CTL = BIT(4);
#else
MCHP_WDG_CTL |= 1;
#endif

8
chip/mchp/fan.c
View File

@ -82,15 +82,15 @@ int fan_get_duty(int ch)
int fan_get_rpm_mode(int ch)
{
return !!(MCHP_FAN_CFG1(0) & (1 << 7));
return !!(MCHP_FAN_CFG1(0) & BIT(7));
}
void fan_set_rpm_mode(int ch, int rpm_mode)
{
if (rpm_mode)
MCHP_FAN_CFG1(0) |= 1 << 7;
MCHP_FAN_CFG1(0) |= BIT(7);
else
MCHP_FAN_CFG1(0) &= ~(1 << 7);
MCHP_FAN_CFG1(0) &= ~BIT(7);
clear_status();
}
@ -118,7 +118,7 @@ enum fan_status fan_get_status(int ch)
{
uint8_t sts = MCHP_FAN_STATUS(0);
if (sts & ((1 << 5) | (1 << 1)))
if (sts & (BIT(5) | BIT(1)))
return FAN_STATUS_FRUSTRATED;
if (fan_get_rpm_actual(ch) == 0)
return FAN_STATUS_STOPPED;

8
chip/mchp/gpio.c
View File

@ -57,7 +57,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func)
while (mask) {
i = __builtin_ffs(mask) - 1;
val = MCHP_GPIO_CTL(port, i);
val &= ~((1 << 12) | (1 << 13));
val &= ~(BIT(12) | BIT(13));
/* mux_control = 0 indicates GPIO */
if (func > 0)
val |= (func & 0x3) << 12;
@ -77,7 +77,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal)
i = GPIO_MASK_TO_NUM(mask);
val = MCHP_GPIO_CTL(gpio_list[signal].port, i);
return (val & (1 << 24)) ? 1 : 0;
return (val & BIT(24)) ? 1 : 0;
}
void gpio_set_level(enum gpio_signal signal, int value)
@ -90,9 +90,9 @@ void gpio_set_level(enum gpio_signal signal, int value)
i = GPIO_MASK_TO_NUM(mask);
if (value)
MCHP_GPIO_CTL(gpio_list[signal].port, i) |= (1 << 16);
MCHP_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16);
else
MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~(1 << 16);
MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16);
}
/*

6
chip/mchp/gpspi.c
View File

@ -109,7 +109,7 @@ int gpspi_transaction_async(const struct spi_device_t *spi_device,
ctrl = gpspi_port_to_ctrl_id(hw_port);
/* Disable auto read */
MCHP_SPI_CR(ctrl) &= ~(1 << 5);
MCHP_SPI_CR(ctrl) &= ~BIT(5);
if ((txdata != NULL) && (txdata != 0)) {
#ifdef CONFIG_MCHP_GPSPI_TX_DMA
@ -151,7 +151,7 @@ int gpspi_transaction_async(const struct spi_device_t *spi_device,
if (!cs_asserted)
gpio_set_level(spi_device->gpio_cs, 0);
/* Enable auto read */
MCHP_SPI_CR(ctrl) |= 1 << 5;
MCHP_SPI_CR(ctrl) |= BIT(5);
dma_start_rx(opdma, rxlen, rxdata);
MCHP_SPI_TD(ctrl) = 0;
ret = EC_SUCCESS;
@ -180,7 +180,7 @@ int gpspi_transaction_flush(const struct spi_device_t *spi_device)
ret = dma_wait(chan);
/* Disable auto read */
MCHP_SPI_CR(ctrl) &= ~(1 << 5);
MCHP_SPI_CR(ctrl) &= ~BIT(5);
deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US;
/* Wait for FIFO empty SPISR_TXBE */

16
chip/mchp/hwtimer.c
View File

@ -18,7 +18,7 @@ void __hw_clock_event_set(uint32_t deadline)
{
MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) -
(0xffffffff - deadline);
MCHP_TMR32_CTL(1) |= (1 << 5);
MCHP_TMR32_CTL(1) |= BIT(5);
}
uint32_t __hw_clock_event_get(void)
@ -28,7 +28,7 @@ uint32_t __hw_clock_event_get(void)
void __hw_clock_event_clear(void)
{
MCHP_TMR32_CTL(1) &= ~(1 << 5);
MCHP_TMR32_CTL(1) &= ~BIT(5);
}
uint32_t __hw_clock_source_read(void)
@ -38,9 +38,9 @@ uint32_t __hw_clock_source_read(void)
void __hw_clock_source_set(uint32_t ts)
{
MCHP_TMR32_CTL(0) &= ~(1 << 5);
MCHP_TMR32_CTL(0) &= ~BIT(5);
MCHP_TMR32_CNT(0) = 0xffffffff - ts;
MCHP_TMR32_CTL(0) |= (1 << 5);
MCHP_TMR32_CTL(0) |= BIT(5);
}
/*
@ -66,10 +66,10 @@ static void configure_timer(int timer_id)
uint32_t val;
/* Ensure timer is not running */
MCHP_TMR32_CTL(timer_id) &= ~(1 << 5);
MCHP_TMR32_CTL(timer_id) &= ~BIT(5);
/* Enable timer */
MCHP_TMR32_CTL(timer_id) |= (1 << 0);
MCHP_TMR32_CTL(timer_id) |= BIT(0);
val = MCHP_TMR32_CTL(timer_id);
@ -103,10 +103,10 @@ int __hw_clock_source_init(uint32_t start_t)
MCHP_TMR32_CNT(0) = 0xffffffff - start_t;
/* Auto restart */
MCHP_TMR32_CTL(0) |= (1 << 3);
MCHP_TMR32_CTL(0) |= BIT(3);
/* Start counting in timer 0 */
MCHP_TMR32_CTL(0) |= (1 << 5);
MCHP_TMR32_CTL(0) |= BIT(5);
/* Enable interrupt */
task_enable_irq(MCHP_IRQ_TIMER32_0);

68
chip/mchp/i2c.c
View File

@ -46,44 +46,44 @@
#define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul
#define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul
/* Status */
#define STS_NBB (1 << 0) /* Bus busy */
#define STS_LAB (1 << 1) /* Arbitration lost */
#define STS_LRB (1 << 3) /* Last received bit */
#define STS_BER (1 << 4) /* Bus error */
#define STS_PIN (1 << 7) /* Pending interrupt */
#define STS_NBB BIT(0) /* Bus busy */
#define STS_LAB BIT(1) /* Arbitration lost */
#define STS_LRB BIT(3) /* Last received bit */
#define STS_BER BIT(4) /* Bus error */
#define STS_PIN BIT(7) /* Pending interrupt */
/* Control */
#define CTRL_ACK (1 << 0) /* Acknowledge */
#define CTRL_STO (1 << 1) /* STOP */
#define CTRL_STA (1 << 2) /* START */
#define CTRL_ENI (1 << 3) /* Enable interrupt */
#define CTRL_ESO (1 << 6) /* Enable serial output */
#define CTRL_PIN (1 << 7) /* Pending interrupt not */
#define CTRL_ACK BIT(0) /* Acknowledge */
#define CTRL_STO BIT(1) /* STOP */
#define CTRL_STA BIT(2) /* START */
#define CTRL_ENI BIT(3) /* Enable interrupt */
#define CTRL_ESO BIT(6) /* Enable serial output */
#define CTRL_PIN BIT(7) /* Pending interrupt not */
/* Completion */
#define COMP_DTEN (1 << 2) /* enable device timeouts */
#define COMP_MCEN (1 << 3) /* enable master cumulative timeouts */
#define COMP_SCEN (1 << 4) /* enable slave cumulative timeouts */
#define COMP_BIDEN (1 << 5) /* enable Bus idle timeouts */
#define COMP_IDLE (1 << 29) /* i2c bus is idle */
#define COMP_DTEN BIT(2) /* enable device timeouts */
#define COMP_MCEN BIT(3) /* enable master cumulative timeouts */
#define COMP_SCEN BIT(4) /* enable slave cumulative timeouts */
#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */
#define COMP_IDLE BIT(29) /* i2c bus is idle */
#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
/* Configuration */
#define CFG_PORT_MASK (0x0F) /* port selection field */
#define CFG_TCEN (1 << 4) /* Enable HW bus timeouts */
#define CFG_FEN (1 << 8) /* enable input filtering */
#define CFG_RESET (1 << 9) /* reset controller */
#define CFG_ENABLE (1 << 10) /* enable controller */
#define CFG_GC_DIS (1 << 14) /* disable general call address */
#define CFG_ENIDI (1 << 29) /* Enable I2C idle interrupt */
#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */
#define CFG_FEN BIT(8) /* enable input filtering */
#define CFG_RESET BIT(9) /* reset controller */
#define CFG_ENABLE BIT(10) /* enable controller */
#define CFG_GC_DIS BIT(14) /* disable general call address */
#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */
/* Enable network layer master done interrupt */
#define CFG_ENMI (1 << 30)
#define CFG_ENMI BIT(30)
/* Enable network layer slave done interrupt */
#define CFG_ENSI (1 << 31)
#define CFG_ENSI BIT(31)
/* Master Command */
#define MCMD_MRUN (1 << 0)
#define MCMD_MPROCEED (1 << 1)
#define MCMD_START0 (1 << 8)
#define MCMD_STARTN (1 << 9)
#define MCMD_STOP (1 << 10)
#define MCMD_READM (1 << 12)
#define MCMD_MRUN BIT(0)
#define MCMD_MPROCEED BIT(1)
#define MCMD_START0 BIT(8)
#define MCMD_STARTN BIT(9)
#define MCMD_STOP BIT(10)
#define MCMD_READM BIT(12)
#define MCMD_WCNT_BITPOS (16)
#define MCMD_WCNT_MASK0 (0xFF)
#define MCMD_WCNT_MASK (0xFF << 16)
@ -342,9 +342,9 @@ static void reset_controller(int controller)
int i;
/* Reset asserted for at least one AHB clock */
MCHP_I2C_CONFIG(controller) |= 1 << 9;
MCHP_I2C_CONFIG(controller) |= BIT(9);
MCHP_EC_ID_RO = 0;
MCHP_I2C_CONFIG(controller) &= ~(1 << 9);
MCHP_I2C_CONFIG(controller) &= ~BIT(9);
for (i = 0; i < i2c_ports_used; ++i)
if (controller == i2c_port_to_controller(i2c_ports[i].port)) {
@ -464,9 +464,9 @@ static void select_port(int port, int controller)
if ((MCHP_I2C_CONFIG(controller) & 0x0f) == port_sel)
return;
MCHP_I2C_CONFIG(controller) |= 1 << 9;
MCHP_I2C_CONFIG(controller) |= BIT(9);
MCHP_EC_ID_RO = 0; /* dummy write to read-only as delay */
MCHP_I2C_CONFIG(controller) &= ~(1 << 9);
MCHP_I2C_CONFIG(controller) &= ~BIT(9);
configure_controller(controller, port_sel, i2c_ports[port].kbps);
}

8
chip/mchp/keyboard_raw.c
View File

@ -39,19 +39,19 @@ void keyboard_raw_task_start(void)
test_mockable void keyboard_raw_drive_column(int out)
{
if (out == KEYBOARD_COLUMN_ALL) {
MCHP_KS_KSO_SEL = 1 << 5; /* KSEN=0, KSALL=1 */
MCHP_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */
#ifdef CONFIG_KEYBOARD_COL2_INVERTED
gpio_set_level(GPIO_KBD_KSO2, 1);
#endif
} else if (out == KEYBOARD_COLUMN_NONE) {
MCHP_KS_KSO_SEL = 1 << 6; /* KSEN=1 */
MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */
#ifdef CONFIG_KEYBOARD_COL2_INVERTED
gpio_set_level(GPIO_KBD_KSO2, 0);
#endif
} else {
#ifdef CONFIG_KEYBOARD_COL2_INVERTED
if (out == 2) {
MCHP_KS_KSO_SEL = 1 << 6; /* KSEN=1 */
MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */
gpio_set_level(GPIO_KBD_KSO2, 1);
} else {
MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
@ -100,5 +100,5 @@ DECLARE_IRQ(MCHP_IRQ_KSC_INT, keyboard_raw_interrupt, 1);
int keyboard_raw_is_input_low(int port, int id)
{
return (MCHP_GPIO_CTL(port, id) & (1 << 24)) == 0;
return (MCHP_GPIO_CTL(port, id) & BIT(24)) == 0;
}

24
chip/mchp/lfw/ec_lfw.c
View File

@ -100,10 +100,10 @@ void timer_init(void)
uint32_t val = 0;
/* Ensure timer is not running */
MCHP_TMR32_CTL(0) &= ~(1 << 5);
MCHP_TMR32_CTL(0) &= ~BIT(5);
/* Enable timer */
MCHP_TMR32_CTL(0) |= (1 << 0);
MCHP_TMR32_CTL(0) |= BIT(0);
val = MCHP_TMR32_CTL(0);
@ -119,10 +119,10 @@ void timer_init(void)
MCHP_TMR32_CNT(0) = 0xffffffff;
/* Auto restart */
MCHP_TMR32_CTL(0) |= (1 << 3);
MCHP_TMR32_CTL(0) |= BIT(3);
/* Start counting in timer 0 */
MCHP_TMR32_CTL(0) |= (1 << 5);
MCHP_TMR32_CTL(0) |= BIT(5);
}
@ -246,7 +246,7 @@ void uart_write_c(char c)
uart_write_c('\r');
/* Wait for space in transmit FIFO. */
while (!(MCHP_UART_LSR(0) & (1 << 5)))
while (!(MCHP_UART_LSR(0) & BIT(5)))
;
MCHP_UART_TB(0) = c;
}
@ -282,31 +282,31 @@ void jump_to_image(uintptr_t init_addr)
void uart_init(void)
{
/* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */
MCHP_UART_CFG(0) &= ~(1 << 1);
MCHP_UART_CFG(0) &= ~BIT(1);
/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
/* Set CLK_SRC = 0 */
MCHP_UART_CFG(0) &= ~(1 << 0);
MCHP_UART_CFG(0) &= ~BIT(0);
/* Set DLAB = 1 */
MCHP_UART_LCR(0) |= (1 << 7);
MCHP_UART_LCR(0) |= BIT(7);
/* PBRG0/PBRG1 */
MCHP_UART_PBRG0(0) = 1;
MCHP_UART_PBRG1(0) = 0;
/* Set DLAB = 0 */
MCHP_UART_LCR(0) &= ~(1 << 7);
MCHP_UART_LCR(0) &= ~BIT(7);
/* Set word length to 8-bit */
MCHP_UART_LCR(0) |= (1 << 0) | (1 << 1);
MCHP_UART_LCR(0) |= BIT(0) | BIT(1);
/* Enable FIFO */
MCHP_UART_FCR(0) = (1 << 0);
MCHP_UART_FCR(0) = BIT(0);
/* Activate UART */
MCHP_UART_ACT(0) |= (1 << 0);
MCHP_UART_ACT(0) |= BIT(0);
gpio_config_module(MODULE_UART, 1);
}

14
chip/mchp/lpc.c
View File

@ -348,7 +348,7 @@ void chip_8042_config(uint32_t io_base)
MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15);
#endif
/* Set up indication of Auxiliary sts */
MCHP_8042_KB_CTRL |= 1 << 7;
MCHP_8042_KB_CTRL |= BIT(7);
MCHP_8042_ACT |= 1;
@ -360,7 +360,7 @@ void chip_8042_config(uint32_t io_base)
#ifndef CONFIG_KEYBOARD_IRQ_GPIO
/* Set up SERIRQ for keyboard */
MCHP_8042_KB_CTRL |= (1 << 5);
MCHP_8042_KB_CTRL |= BIT(5);
MCHP_LPC_SIRQ(1) = 0x01;
#endif
}
@ -464,7 +464,7 @@ static void setup_lpc(void)
#ifndef CONFIG_KEYBOARD_IRQ_GPIO
/* Set up SERIRQ for keyboard */
MCHP_8042_KB_CTRL |= (1 << 5);
MCHP_8042_KB_CTRL |= BIT(5);
MCHP_LPC_SIRQ(1) = 0x01;
#endif
/* EMI0 at IO 0x800 */
@ -815,7 +815,7 @@ void kb_ibf_interrupt(void)
{
if (lpc_keyboard_input_pending())
keyboard_host_write(MCHP_8042_H2E,
MCHP_8042_STS & (1 << 3));
MCHP_8042_STS & BIT(3));
MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT;
task_wake(TASK_ID_KEYPROTO);
@ -844,12 +844,12 @@ DECLARE_IRQ(MCHP_IRQ_8042EM_OBE, kb_obe_interrupt, 1);
*/
int lpc_keyboard_has_char(void)
{
return (MCHP_8042_STS & (1 << 0)) ? 1 : 0;
return (MCHP_8042_STS & BIT(0)) ? 1 : 0;
}
int lpc_keyboard_input_pending(void)
{
return (MCHP_8042_STS & (1 << 1)) ? 1 : 0;
return (MCHP_8042_STS & BIT(1)) ? 1 : 0;
}
/*
@ -944,7 +944,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args)
CPUTS("MEC1701 Handler EC_CMD_GET_PROTOCOL_INFO");
memset(r, 0, sizeof(*r));
r->protocol_versions = (1 << 3);
r->protocol_versions = BIT(3);
r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->flags = 0;

4
chip/mchp/pwm.c
View File

@ -110,8 +110,8 @@ static void pwm_configure(int ch, int active_low, int clock_low)
* clock_low=1 selects the 100kHz_Clk source
*/
MCHP_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */
(active_low ? (1 << 2) : 0) |
(clock_low ? (1 << 1) : 0);
(active_low ? BIT(2) : 0) |
(clock_low ? BIT(1) : 0);
}
static const uint16_t pwm_pcr[MCHP_PWM_ID_MAX] = {

282
chip/mchp/registers.h
View File

@ -90,64 +90,64 @@
#define MCHP_PCR_JTAG (0x0000)
/* Command all blocks to sleep */
#define MCHP_PCR_SLP_EN0_ISPI (1 << 2)
#define MCHP_PCR_SLP_EN0_EFUSE (1 << 1)
#define MCHP_PCR_SLP_EN0_JTAG (1 << 0)
#define MCHP_PCR_SLP_EN0_ISPI BIT(2)
#define MCHP_PCR_SLP_EN0_EFUSE BIT(1)
#define MCHP_PCR_SLP_EN0_JTAG BIT(0)
#define MCHP_PCR_SLP_EN0_SLEEP 0x07ul
/* Sleep Enable, Clock Required, Reset on Sleep 1 bits */
#define MCHP_PCR_BTMR16_1 ((1 << 8) + 31)
#define MCHP_PCR_BTMR16_0 ((1 << 8) + 30)
#define MCHP_PCR_ECS ((1 << 8) + 29)
#define MCHP_PCR_PWM8 ((1 << 8) + 27)
#define MCHP_PCR_PWM7 ((1 << 8) + 26)
#define MCHP_PCR_PWM6 ((1 << 8) + 25)
#define MCHP_PCR_PWM5 ((1 << 8) + 24)
#define MCHP_PCR_PWM4 ((1 << 8) + 23)
#define MCHP_PCR_PWM3 ((1 << 8) + 22)
#define MCHP_PCR_PWM2 ((1 << 8) + 21)
#define MCHP_PCR_PWM1 ((1 << 8) + 20)
#define MCHP_PCR_TACH2 ((1 << 8) + 12)
#define MCHP_PCR_TACH1 ((1 << 8) + 11)
#define MCHP_PCR_I2C0 ((1 << 8) + 10)
#define MCHP_PCR_WDT ((1 << 8) + 9)
#define MCHP_PCR_CPU ((1 << 8) + 8)
#define MCHP_PCR_TFDP ((1 << 8) + 7)
#define MCHP_PCR_DMA ((1 << 8) + 6)
#define MCHP_PCR_PMC ((1 << 8) + 5)
#define MCHP_PCR_PWM0 ((1 << 8) + 4)
#define MCHP_PCR_TACH0 ((1 << 8) + 2)
#define MCHP_PCR_PECI ((1 << 8) + 1)
#define MCHP_PCR_ECIA ((1 << 8) + 0)
#define MCHP_PCR_BTMR16_1 (BIT(8) + 31)
#define MCHP_PCR_BTMR16_0 (BIT(8) + 30)
#define MCHP_PCR_ECS (BIT(8) + 29)
#define MCHP_PCR_PWM8 (BIT(8) + 27)
#define MCHP_PCR_PWM7 (BIT(8) + 26)
#define MCHP_PCR_PWM6 (BIT(8) + 25)
#define MCHP_PCR_PWM5 (BIT(8) + 24)
#define MCHP_PCR_PWM4 (BIT(8) + 23)
#define MCHP_PCR_PWM3 (BIT(8) + 22)
#define MCHP_PCR_PWM2 (BIT(8) + 21)
#define MCHP_PCR_PWM1 (BIT(8) + 20)
#define MCHP_PCR_TACH2 (BIT(8) + 12)
#define MCHP_PCR_TACH1 (BIT(8) + 11)
#define MCHP_PCR_I2C0 (BIT(8) + 10)
#define MCHP_PCR_WDT (BIT(8) + 9)
#define MCHP_PCR_CPU (BIT(8) + 8)
#define MCHP_PCR_TFDP (BIT(8) + 7)
#define MCHP_PCR_DMA (BIT(8) + 6)
#define MCHP_PCR_PMC (BIT(8) + 5)
#define MCHP_PCR_PWM0 (BIT(8) + 4)
#define MCHP_PCR_TACH0 (BIT(8) + 2)
#define MCHP_PCR_PECI (BIT(8) + 1)
#define MCHP_PCR_ECIA (BIT(8) + 0)
/* Command all blocks to sleep */
#define MCHP_PCR_SLP_EN1_BTMR16_1 (1 << 31)
#define MCHP_PCR_SLP_EN1_BTMR16_0 (1 << 30)
#define MCHP_PCR_SLP_EN1_ECS (1 << 29)
#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31)
#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30)
#define MCHP_PCR_SLP_EN1_ECS BIT(29)
/* bit[28] reserved */
#define MCHP_PCR_SLP_EN1_PWM_ALL ((1 << 4) + (0xff << 20))
#define MCHP_PCR_SLP_EN1_PWM8 (1 << 27)
#define MCHP_PCR_SLP_EN1_PWM7 (1 << 26)
#define MCHP_PCR_SLP_EN1_PWM6 (1 << 25)
#define MCHP_PCR_SLP_EN1_PWM5 (1 << 24)
#define MCHP_PCR_SLP_EN1_PWM4 (1 << 23)
#define MCHP_PCR_SLP_EN1_PWM3 (1 << 22)
#define MCHP_PCR_SLP_EN1_PWM2 (1 << 21)
#define MCHP_PCR_SLP_EN1_PWM1 (1 << 20)
#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20))
#define MCHP_PCR_SLP_EN1_PWM8 BIT(27)
#define MCHP_PCR_SLP_EN1_PWM7 BIT(26)
#define MCHP_PCR_SLP_EN1_PWM6 BIT(25)
#define MCHP_PCR_SLP_EN1_PWM5 BIT(24)
#define MCHP_PCR_SLP_EN1_PWM4 BIT(23)
#define MCHP_PCR_SLP_EN1_PWM3 BIT(22)
#define MCHP_PCR_SLP_EN1_PWM2 BIT(21)
#define MCHP_PCR_SLP_EN1_PWM1 BIT(20)
/* bits[19:13] reserved */
#define MCHP_PCR_SLP_EN1_TACH2 (1 << 12)
#define MCHP_PCR_SLP_EN1_TACH1 (1 << 11)
#define MCHP_PCR_SLP_EN1_I2C0 (1 << 10)
#define MCHP_PCR_SLP_EN1_WDT (1 << 9)
#define MCHP_PCR_SLP_EN1_CPU (1 << 8)
#define MCHP_PCR_SLP_EN1_TFDP (1 << 7)
#define MCHP_PCR_SLP_EN1_DMA (1 << 6)
#define MCHP_PCR_SLP_EN1_PMC (1 << 5)
#define MCHP_PCR_SLP_EN1_PWM0 (1 << 4)
#define MCHP_PCR_SLP_EN1_TACH2 BIT(12)
#define MCHP_PCR_SLP_EN1_TACH1 BIT(11)
#define MCHP_PCR_SLP_EN1_I2C0 BIT(10)
#define MCHP_PCR_SLP_EN1_WDT BIT(9)
#define MCHP_PCR_SLP_EN1_CPU BIT(8)
#define MCHP_PCR_SLP_EN1_TFDP BIT(7)
#define MCHP_PCR_SLP_EN1_DMA BIT(6)
#define MCHP_PCR_SLP_EN1_PMC BIT(5)
#define MCHP_PCR_SLP_EN1_PWM0 BIT(4)
/* bit[3] reserved */
#define MCHP_PCR_SLP_EN1_TACH0 (1 << 2)
#define MCHP_PCR_SLP_EN1_PECI (1 << 1)
#define MCHP_PCR_SLP_EN1_ECIA (1 << 0)
#define MCHP_PCR_SLP_EN1_TACH0 BIT(2)
#define MCHP_PCR_SLP_EN1_PECI BIT(1)
#define MCHP_PCR_SLP_EN1_ECIA BIT(0)
/* all sleep enable 1 bits */
#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff
/*
@ -176,25 +176,25 @@
/* Command all blocks to sleep */
/* bits[31:27] reserved */
#define MCHP_PCR_SLP_EN2_P80CAP1 (1 << 26)
#define MCHP_PCR_SLP_EN2_P80CAP0 (1 << 25)
#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26)
#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25)
/* bit[24] reserved */
#define MCHP_PCR_SLP_EN2_ACPI_EC4 (1 << 23)
#define MCHP_PCR_SLP_EN2_ACPI_EC3 (1 << 22)
#define MCHP_PCR_SLP_EN2_ACPI_EC2 (1 << 21)
#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23)
#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22)
#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21)
/* bit[20] reserved */
#define MCHP_PCR_SLP_EN2_ESPI (1 << 19)
#define MCHP_PCR_SLP_EN2_RTC (1 << 18)
#define MCHP_PCR_SLP_EN2_MAILBOX (1 << 17)
#define MCHP_PCR_SLP_EN2_MIF8042 (1 << 16)
#define MCHP_PCR_SLP_EN2_ACPI_PM1 (1 << 15)
#define MCHP_PCR_SLP_EN2_ACPI_EC1 (1 << 14)
#define MCHP_PCR_SLP_EN2_ACPI_EC0 (1 << 13)
#define MCHP_PCR_SLP_EN2_GCFG (1 << 12)
#define MCHP_PCR_SLP_EN2_ESPI BIT(19)
#define MCHP_PCR_SLP_EN2_RTC BIT(18)
#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17)
#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16)
#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15)
#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14)
#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13)
#define MCHP_PCR_SLP_EN2_GCFG BIT(12)
/* bits[11:3] reserved */
#define MCHP_PCR_SLP_EN2_UART1 (1 << 2)
#define MCHP_PCR_SLP_EN2_UART0 (1 << 1)
#define MCHP_PCR_SLP_EN2_LPC (1 << 0)
#define MCHP_PCR_SLP_EN2_UART1 BIT(2)
#define MCHP_PCR_SLP_EN2_UART0 BIT(1)
#define MCHP_PCR_SLP_EN2_LPC BIT(0)
/* all sleep enable 2 bits */
#define MCHP_PCR_SLP_EN2_SLEEP 0x07ffffff
@ -228,35 +228,35 @@
#define MCHP_PCR_ADC ((3 << 8) + 3)
/* Command all blocks to sleep */
#define MCHP_PCR_SLP_EN3_PWM9 (1 << 31)
#define MCHP_PCR_SLP_EN3_CCT0 (1 << 30)
#define MCHP_PCR_SLP_EN3_HTMR1 (1 << 29)
#define MCHP_PCR_SLP_EN3_AESHASH (1 << 28)
#define MCHP_PCR_SLP_EN3_RNG (1 << 27)
#define MCHP_PCR_SLP_EN3_PKE (1 << 26)
#define MCHP_PCR_SLP_EN3_LED3 (1 << 25)
#define MCHP_PCR_SLP_EN3_BTMR32_1 (1 << 24)
#define MCHP_PCR_SLP_EN3_BTMR32_0 (1 << 23)
#define MCHP_PCR_SLP_EN3_BTMR16_3 (1 << 22)
#define MCHP_PCR_SLP_EN3_BTMR16_2 (1 << 21)
#define MCHP_PCR_SLP_EN3_GPSPI1 (1 << 20)
#define MCHP_PCR_SLP_EN3_BCM0 (1 << 19)
#define MCHP_PCR_SLP_EN3_LED2 (1 << 18)
#define MCHP_PCR_SLP_EN3_LED1 (1 << 17)
#define MCHP_PCR_SLP_EN3_LED0 (1 << 16)
#define MCHP_PCR_SLP_EN3_I2C3 (1 << 15)
#define MCHP_PCR_SLP_EN3_I2C2 (1 << 14)
#define MCHP_PCR_SLP_EN3_I2C1 (1 << 13)
#define MCHP_PCR_SLP_EN3_RPMPWM0 (1 << 12)
#define MCHP_PCR_SLP_EN3_KEYSCAN (1 << 11)
#define MCHP_PCR_SLP_EN3_HTMR0 (1 << 10)
#define MCHP_PCR_SLP_EN3_GPSPI0 (1 << 9)
#define MCHP_PCR_SLP_EN3_PWM9 BIT(31)
#define MCHP_PCR_SLP_EN3_CCT0 BIT(30)
#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29)
#define MCHP_PCR_SLP_EN3_AESHASH BIT(28)
#define MCHP_PCR_SLP_EN3_RNG BIT(27)
#define MCHP_PCR_SLP_EN3_PKE BIT(26)
#define MCHP_PCR_SLP_EN3_LED3 BIT(25)
#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24)
#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23)
#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22)
#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21)
#define MCHP_PCR_SLP_EN3_GPSPI1 BIT(20)
#define MCHP_PCR_SLP_EN3_BCM0 BIT(19)
#define MCHP_PCR_SLP_EN3_LED2 BIT(18)
#define MCHP_PCR_SLP_EN3_LED1 BIT(17)
#define MCHP_PCR_SLP_EN3_LED0 BIT(16)
#define MCHP_PCR_SLP_EN3_I2C3 BIT(15)
#define MCHP_PCR_SLP_EN3_I2C2 BIT(14)
#define MCHP_PCR_SLP_EN3_I2C1 BIT(13)
#define MCHP_PCR_SLP_EN3_RPMPWM0 BIT(12)
#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11)
#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10)
#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9)
/* bit[8] reserved */
#define MCHP_PCR_SLP_EN3_PS2_2 (1 << 7)
#define MCHP_PCR_SLP_EN3_PS2_1 (1 << 6)
#define MCHP_PCR_SLP_EN3_PS2_0 (1 << 5)
#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7)
#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6)
#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5)
/* bit[4] reserved */
#define MCHP_PCR_SLP_EN3_ADC (1 << 3)
#define MCHP_PCR_SLP_EN3_ADC BIT(3)
/* bits[2:0] reserved */
/* all sleep enable 3 bits */
#define MCHP_PCR_SLP_EN3_SLEEP 0xfffffeed
@ -281,23 +281,23 @@
#define MCHP_PCR_PWM10 ((4 << 8) + 0)
/* Command all blocks to sleep */
#define MCHP_PCR_SLP_EN4_FJCL (1 << 15)
#define MCHP_PCR_SLP_EN4_PSPI (1 << 14)
#define MCHP_PCR_SLP_EN4_PROCHOT (1 << 13)
#define MCHP_PCR_SLP_EN4_RCID2 (1 << 12)
#define MCHP_PCR_SLP_EN4_RCID1 (1 << 11)
#define MCHP_PCR_SLP_EN4_RCID0 (1 << 10)
#define MCHP_PCR_SLP_EN4_BCM1 (1 << 9)
#define MCHP_PCR_SLP_EN4_QMSPI (1 << 8)
#define MCHP_PCR_SLP_EN4_RPMPWM1 (1 << 7)
#define MCHP_PCR_SLP_EN4_RTMR (1 << 6)
#define MCHP_PCR_SLP_EN4_CNT16_3 (1 << 5)
#define MCHP_PCR_SLP_EN4_CNT16_2 (1 << 4)
#define MCHP_PCR_SLP_EN4_CNT16_1 (1 << 3)
#define MCHP_PCR_SLP_EN4_CNT16_0 (1 << 2)
#define MCHP_PCR_SLP_EN4_FJCL BIT(15)
#define MCHP_PCR_SLP_EN4_PSPI BIT(14)
#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13)
#define MCHP_PCR_SLP_EN4_RCID2 BIT(12)
#define MCHP_PCR_SLP_EN4_RCID1 BIT(11)
#define MCHP_PCR_SLP_EN4_RCID0 BIT(10)
#define MCHP_PCR_SLP_EN4_BCM1 BIT(9)
#define MCHP_PCR_SLP_EN4_QMSPI BIT(8)
#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7)
#define MCHP_PCR_SLP_EN4_RTMR BIT(6)
#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5)
#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4)
#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3)
#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2)
#define MCHP_PCR_SLP_EN4_PWM_ALL (3 << 0)
#define MCHP_PCR_SLP_EN4_PWM11 (1 << 1)
#define MCHP_PCR_SLP_EN4_PWM10 (1 << 0)
#define MCHP_PCR_SLP_EN4_PWM11 BIT(1)
#define MCHP_PCR_SLP_EN4_PWM10 BIT(0)
/* all sleep enable 4 bits */
#define MCHP_PCR_SLP_EN4_SLEEP 0x0000ffff
@ -314,17 +314,17 @@
/* Bit definitions for MCHP_PCR_SLP_EN2/CLK_REQ2/RST_EN2 */
/* Bit definitions for MCHP_PCR_SLP_EN3/CLK_REQ3/RST_EN3 */
#define MCHP_PCR_SLP_EN1_PKE (1 << 26)
#define MCHP_PCR_SLP_EN1_NDRNG (1 << 27)
#define MCHP_PCR_SLP_EN1_AES_SHA (1 << 28)
#define MCHP_PCR_SLP_EN1_PKE BIT(26)
#define MCHP_PCR_SLP_EN1_NDRNG BIT(27)
#define MCHP_PCR_SLP_EN1_AES_SHA BIT(28)
#define MCHP_PCR_SLP_EN1_ALL_CRYPTO (0x07 << 26)
/* Bit definitions for MCHP_PCR_SLP_EN4/CLK_REQ4/RST_EN4 */
/* Bit defines for MCHP_PCR_PWR_RST_STS */
#define MCHP_PWR_RST_STS_VTR (1 << 6)
#define MCHP_PWR_RST_STS_VBAT (1 << 5)
#define MCHP_PWR_RST_STS_VTR BIT(6)
#define MCHP_PWR_RST_STS_VBAT BIT(5)
/* Bit defines for MCHP_PCR_PWR_RST_CTL */
#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8
@ -333,7 +333,7 @@
/* Bit defines for MCHP_PCR_SYS_RST */
#define MCHP_PCR_SYS_SOFT_RESET (1 << 8)
#define MCHP_PCR_SYS_SOFT_RESET BIT(8)
/* TFDP */
@ -554,7 +554,7 @@
#define MCHP_UART_GIRQ_BIT(x) (1ul << (x))
/* Bit defines for MCHP_UARTx_LSR */
#define MCHP_LSR_TX_EMPTY (1 << 5)
#define MCHP_LSR_TX_EMPTY BIT(5)
/* GPIO */
@ -580,7 +580,7 @@
* Example: GPIO043, Control 1 register address = 0x4008108c
* port/bank = 0x23 >> 5 = 1
* id = 0x23 & 0x1F = 0x03
* Control 1 Address = 0x40081000 + (((1 << 5) + 0x03) << 2) = 0x4008108c
* Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c
*
* Example: GPIO235, Control 1 register address = 0x40081274
* port/bank = 0x9d >> 5 = 4
@ -641,7 +641,7 @@
#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12)
#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12)
#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12)
#define MCHP_GPIO_CTRL_OUT_LVL (1 << 16)
#define MCHP_GPIO_CTRL_OUT_LVL BIT(16)
/* GPIO Parallel Input and Output registers.
* gpio_bank in [0, 5]
@ -705,11 +705,11 @@
#define MCHP_VBAT_VWIRE_BACKUP 30
/* Bit definition for MCHP_VBAT_STS */
#define MCHP_VBAT_STS_SOFTRESET (1 << 2)
#define MCHP_VBAT_STS_RESETI (1 << 4)
#define MCHP_VBAT_STS_WDT (1 << 5)
#define MCHP_VBAT_STS_SYSRESETREQ (1 << 6)
#define MCHP_VBAT_STS_VBAT_RST (1 << 7)
#define MCHP_VBAT_STS_SOFTRESET BIT(2)
#define MCHP_VBAT_STS_RESETI BIT(4)
#define MCHP_VBAT_STS_WDT BIT(5)
#define MCHP_VBAT_STS_SYSRESETREQ BIT(6)
#define MCHP_VBAT_STS_VBAT_RST BIT(7)
#define MCHP_VBAT_STS_ANY_RST (0xF4u)
/* Bit definitions for MCHP_VBAT_CE */
@ -1326,9 +1326,9 @@ enum MCHP_i2c_port {
((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17)
/* Bits in MCHP_QMSPI0_EXE */
#define MCHP_QMSPI_EXE_START (1 << 0)
#define MCHP_QMSPI_EXE_STOP (1 << 1)
#define MCHP_QMSPI_EXE_CLR_FIFOS (1 << 2)
#define MCHP_QMSPI_EXE_START BIT(0)
#define MCHP_QMSPI_EXE_STOP BIT(1)
#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2)
/* MCHP QMSPI FIFO Sizes */
#define MCHP_QMSPI_TX_FIFO_LEN 8
@ -1982,30 +1982,30 @@ enum dma_channel {
/* Bits for DMA Main Control */
#define MCHP_DMA_MAIN_CTRL_ACT (1 << 0)
#define MCHP_DMA_MAIN_CTRL_SRST (1 << 1)
#define MCHP_DMA_MAIN_CTRL_ACT BIT(0)
#define MCHP_DMA_MAIN_CTRL_SRST BIT(1)
/* Bits for DMA channel regs */
#define MCHP_DMA_ACT_EN (1 << 0)
#define MCHP_DMA_ACT_EN BIT(0)
/* DMA Channel Control */
#define MCHP_DMA_ABORT (1 << 25)
#define MCHP_DMA_SW_GO (1 << 24)
#define MCHP_DMA_ABORT BIT(25)
#define MCHP_DMA_SW_GO BIT(24)
#define MCHP_DMA_XFER_SIZE_MASK (7ul << 20)
#define MCHP_DMA_XFER_SIZE(x) ((x) << 20)
#define MCHP_DMA_DIS_HW_FLOW (1 << 19)
#define MCHP_DMA_INC_DEV (1 << 17)
#define MCHP_DMA_INC_MEM (1 << 16)
#define MCHP_DMA_DIS_HW_FLOW BIT(19)
#define MCHP_DMA_INC_DEV BIT(17)
#define MCHP_DMA_INC_MEM BIT(16)
#define MCHP_DMA_DEV(x) ((x) << 9)
#define MCHP_DMA_DEV_MASK0 (0x7f)
#define MCHP_DMA_DEV_MASK (0x7f << 9)
#define MCHP_DMA_TO_DEV (1 << 8)
#define MCHP_DMA_DONE (1 << 2)
#define MCHP_DMA_RUN (1 << 0)
#define MCHP_DMA_TO_DEV BIT(8)
#define MCHP_DMA_DONE BIT(2)
#define MCHP_DMA_RUN BIT(0)
/* DMA Channel Status */
#define MCHP_DMA_STS_ALU_DONE (1 << 3)
#define MCHP_DMA_STS_DONE (1 << 2)
#define MCHP_DMA_STS_HWFL_ERR (1 << 1)
#define MCHP_DMA_STS_BUS_ERR (1 << 0)
#define MCHP_DMA_STS_ALU_DONE BIT(3)
#define MCHP_DMA_STS_DONE BIT(2)
#define MCHP_DMA_STS_HWFL_ERR BIT(1)
#define MCHP_DMA_STS_BUS_ERR BIT(0)
/*
* Peripheral device DMA Device ID's for bits [15:9]

2
chip/mchp/spi_chip.h
View File

@ -36,7 +36,7 @@
#define GPSPI_CLASS0 1
#define QMSPI_CLASS (0 << 4)
#define GPSPI_CLASS (1 << 4)
#define GPSPI_CLASS BIT(4)
#define QMSPI_CTRL0 0
#define GPSPI_CTRL0 0

36
chip/mchp/uart.c
View File

@ -30,7 +30,7 @@ int uart_init_done(void)
void uart_tx_start(void)
{
/* If interrupt is already enabled, nothing to do */
if (MCHP_UART_IER(0) & (1 << 1))
if (MCHP_UART_IER(0) & BIT(1))
return;
/* Do not allow deep sleep while transmit in progress */
@ -42,13 +42,13 @@ void uart_tx_start(void)
* UART where the FIFO only triggers the interrupt when its
* threshold is _crossed_, not just met.
*/
MCHP_UART_IER(0) |= (1 << 1);
MCHP_UART_IER(0) |= BIT(1);
task_trigger_irq(MCHP_IRQ_UART0);
}
void uart_tx_stop(void)
{
MCHP_UART_IER(0) &= ~(1 << 1);
MCHP_UART_IER(0) &= ~BIT(1);
/* Re-allow deep sleep */
enable_sleep(SLEEP_MASK_UART);
@ -79,7 +79,7 @@ int uart_tx_in_progress(void)
int uart_rx_available(void)
{
return MCHP_UART_LSR(0) & (1 << 0);
return MCHP_UART_LSR(0) & BIT(0);
}
void uart_write_char(char c)
@ -99,7 +99,7 @@ int uart_read_char(void)
static void uart_clear_rx_fifo(int channel)
{
MCHP_UART_FCR(0) = (1 << 0) | (1 << 1);
MCHP_UART_FCR(0) = BIT(0) | BIT(1);
}
void uart_disable_interrupt(void)
@ -131,31 +131,31 @@ void uart_init(void)
MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_UART0);
/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
MCHP_UART_CFG(0) &= ~(1 << 1);
MCHP_UART_CFG(0) &= ~BIT(1);
/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
/* Set CLK_SRC = 0 */
MCHP_UART_CFG(0) &= ~(1 << 0);
MCHP_UART_CFG(0) &= ~BIT(0);
/* Set DLAB = 1 */
MCHP_UART_LCR(0) |= (1 << 7);
MCHP_UART_LCR(0) |= BIT(7);
/* PBRG0/PBRG1 */
MCHP_UART_PBRG0(0) = 1;
MCHP_UART_PBRG1(0) = 0;
/* Set DLAB = 0 */
MCHP_UART_LCR(0) &= ~(1 << 7);
MCHP_UART_LCR(0) &= ~BIT(7);
/* Set word length to 8-bit */
MCHP_UART_LCR(0) |= (1 << 0) | (1 << 1);
MCHP_UART_LCR(0) |= BIT(0) | BIT(1);
/* Enable FIFO */
MCHP_UART_FCR(0) = (1 << 0);
MCHP_UART_FCR(0) = BIT(0);
/* Activate UART */
MCHP_UART_ACT(0) |= (1 << 0);
MCHP_UART_ACT(0) |= BIT(0);
gpio_config_module(MODULE_UART, 1);
@ -163,8 +163,8 @@ void uart_init(void)
* Enable interrupts for UART0.
*/
uart_clear_rx_fifo(0);
MCHP_UART_IER(0) |= (1 << 0);
MCHP_UART_MCR(0) |= (1 << 3);
MCHP_UART_IER(0) |= BIT(0);
MCHP_UART_MCR(0) |= BIT(3);
MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
task_enable_irq(MCHP_IRQ_UART0);
@ -185,13 +185,13 @@ void uart_enter_dsleep(void)
gpio_reset(GPIO_UART0_RX);
/* power-down/de-activate UART0 */
MCHP_UART_ACT(0) &= ~(1 << 0);
MCHP_UART_ACT(0) &= ~BIT(0);
/* clear interrupt enable for UART0 */
MCHP_INT_DISABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
/* Clear pending interrupts on GPIO_UART0_RX(GPIO105, girq=9, bit=5) */
MCHP_INT_SOURCE(9) = (1 << 5);
MCHP_INT_SOURCE(9) = BIT(5);
/* Enable GPIO interrupts on the UART0 RX pin. */
gpio_enable_interrupt(GPIO_UART0_RX);
@ -207,7 +207,7 @@ void uart_exit_dsleep(void)
* Note: we can't disable this interrupt if it has already fired
* because then the IRQ will not run at all.
*/
if (!((1 << 5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */
if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */
gpio_disable_interrupt(GPIO_UART0_RX);
/* Configure UART0 pins for use in UART peripheral. */
@ -220,7 +220,7 @@ void uart_exit_dsleep(void)
task_enable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART = 40 */
/* power-up/activate UART0 */
MCHP_UART_ACT(0) |= (1 << 0);
MCHP_UART_ACT(0) |= BIT(0);
}
void uart_deepsleep_interrupt(enum gpio_signal signal)

16
chip/mchp/watchdog.c
View File

@ -17,9 +17,9 @@ void watchdog_reload(void)
#ifdef CONFIG_WATCHDOG_HELP
/* Reload the auxiliary timer */
MCHP_TMR16_CTL(0) &= ~(1 << 5);
MCHP_TMR16_CTL(0) &= ~BIT(5);
MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
MCHP_TMR16_CTL(0) |= 1 << 5;
MCHP_TMR16_CTL(0) |= BIT(5);
#endif
}
DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
@ -38,10 +38,10 @@ int watchdog_init(void)
MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0);
/* Stop the auxiliary timer if it's running */
MCHP_TMR16_CTL(0) &= ~(1 << 5);
MCHP_TMR16_CTL(0) &= ~BIT(5);
/* Enable auxiliary timer */
MCHP_TMR16_CTL(0) |= 1 << 0;
MCHP_TMR16_CTL(0) |= BIT(0);
val = MCHP_TMR16_CTL(0);
@ -49,10 +49,10 @@ int watchdog_init(void)
val = (val & 0xffff) | (47999 << 16);
/* No auto restart */
val &= ~(1 << 3);
val &= ~BIT(3);
/* Count down */
val &= ~(1 << 2);
val &= ~BIT(2);
MCHP_TMR16_CTL(0) = val;
@ -63,7 +63,7 @@ int watchdog_init(void)
/* Load and start the auxiliary timer */
MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS;
MCHP_TMR16_CNT(0) |= 1 << 5;
MCHP_TMR16_CNT(0) |= BIT(5);
#endif
/* Clear WDT PCR sleep enable */
@ -75,7 +75,7 @@ int watchdog_init(void)
/* Start watchdog */
#ifdef CONFIG_CHIPSET_DEBUG
/* WDT will not count if JTAG TRST# is pulled high by JTAG cable */
MCHP_WDG_CTL = (1 << 4) | (1 << 0);
MCHP_WDG_CTL = BIT(4) | BIT(0);
#else
MCHP_WDG_CTL |= 1;
#endif

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