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Make wait_for_ready available for all 

wait_for_ready is a generic function which loops until bits in a
register are set. This patch move it to util.c to make it available
for all.

There are more places where the function is applicable but this CL
keeps the scope under chip/stm32/clock-stm32. There is no
functionality change.

BUG=none
BRANCH=none
TEST=buildall

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I796599344c1d86ab7144d1d6b434ec54cf1cc55d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317887
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This commit is contained in:
Daisuke Nojiri 2020-07-24 11:16:56 -07:00 committed by Commit Bot
parent 00d3f2d0d6
commit b7c6726e22
8 changed files with 49 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
chip/stm32/clock-stm32f0.c
View File

@ -113,13 +113,7 @@ void config_hispeed_clock(void)
{
#ifdef CHIP_FAMILY_STM32F3
/* Ensure that HSE is ON */
if (!(STM32_RCC_CR & BIT(17))) {
/* Enable HSE */
STM32_RCC_CR |= BIT(16);
/* Wait for HSE to be ready */
while (!(STM32_RCC_CR & BIT(17)))
;
}
wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17));
/*
* HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK
@ -151,13 +145,7 @@ defined(CHIP_VARIANT_STM32F070)
return;
/* Ensure that HSI is ON */
if (!(STM32_RCC_CR & (1<<1))) {
/* Enable HSI */
STM32_RCC_CR |= (1<<0);
/* Wait for HSI to be ready */
while (!(STM32_RCC_CR & (1<<1)))
;
}
wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1));
/*
* HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz
@ -186,13 +174,7 @@ defined(CHIP_VARIANT_STM32F070)
;
#else
/* Ensure that HSI48 is ON */
if (!(STM32_RCC_CR2 & BIT(17))) {
/* Enable HSI */
STM32_RCC_CR2 |= BIT(16);
/* Wait for HSI to be ready */
while (!(STM32_RCC_CR2 & BIT(17)))
;
}
wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17));
#if (CPU_CLOCK == HSI48_CLOCK)
/*

13
chip/stm32/clock-stm32f4.c
View File

@ -44,19 +44,6 @@ uint32_t us_to_rtcss(int32_t us)
return (RTC_PREDIV_S - (us / US_PER_RTC_TICK));
}
static void wait_for_ready(volatile uint32_t *cr_reg,
uint32_t enable, uint32_t ready)
{
/* Ensure that clock source is ON */
if (!(*cr_reg & ready)) {
/* Enable clock */
*cr_reg |= enable;
/* Wait for ready */
while (!(*cr_reg & ready))
;
}
}
void config_hispeed_clock(void)
{
#ifdef CONFIG_STM32_CLOCK_HSE_HZ

7
chip/stm32/clock-stm32h7.c
View File

@ -265,12 +265,7 @@ static void clock_enable_osc(enum clock_osc osc, bool enabled)
}
/* Turn on the oscillator if not already on */
if (!(STM32_RCC_CR & ready)) {
STM32_RCC_CR |= on;
/* Wait until ready */
while (!(STM32_RCC_CR & ready))
;
}
wait_for_ready(&STM32_RCC_CR, on, ready);
}
static void clock_switch_osc(enum clock_osc osc)

18
chip/stm32/clock-stm32l.c
View File

@ -86,13 +86,8 @@ static void clock_set_osc(enum clock_osc osc)
switch (osc) {
case OSC_HSI:
/* Ensure that HSI is ON */
if (!(STM32_RCC_CR & STM32_RCC_CR_HSIRDY)) {
/* Enable HSI */
STM32_RCC_CR |= STM32_RCC_CR_HSION;
/* Wait for HSI to be ready */
while (!(STM32_RCC_CR & STM32_RCC_CR_HSIRDY))
;
}
wait_for_ready(&STM32_RCC_CR,
STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY);
/* Disable LPSDSR */
STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR;
@ -142,13 +137,8 @@ static void clock_set_osc(enum clock_osc osc)
(STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
STM32_RCC_ICSCR_MSIRANGE_1MHZ;
/* Ensure that MSI is ON */
if (!(STM32_RCC_CR & STM32_RCC_CR_MSIRDY)) {
/* Enable MSI */
STM32_RCC_CR |= STM32_RCC_CR_MSION;
/* Wait for MSI to be ready */
while (!(STM32_RCC_CR & STM32_RCC_CR_MSIRDY))
;
}
wait_for_ready(&STM32_RCC_CR,
STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY);
/* Switch to MSI */
STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI;

9
chip/stm32/clock-stm32l4.c
View File

@ -83,13 +83,8 @@ static void clock_enable_osc(enum clock_osc osc)
return;
}
if (!(STM32_RCC_CR & ready)) {
/* Enable HSI */
STM32_RCC_CR |= on;
/* Wait for HSI to be ready */
while (!(STM32_RCC_CR & ready))
;
}
/* Enable HSI and wait for HSI to be ready */
wait_for_ready(&STM32_RCC_CR, on, ready);
}
/* Switch system clock oscillator */

12
common/util.c
View File

@ -679,3 +679,15 @@ void hexdump(const uint8_t *data, int len)
ccprintf("|\n");
}
}
void wait_for_ready(volatile uint32_t *reg, uint32_t enable, uint32_t ready)
{
if (*reg & ready)
return;
/* Enable */
*reg |= enable;
/* Wait for ready */
while (!(*reg & ready))
;
}

9
include/util.h
View File

@ -299,6 +299,15 @@ static inline uint64_t mulaa32(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
}
#endif
/**
* Set enable bit(s) in register and wait for ready bit(s)
*
* @param reg Register to be get and set for enable and ready
* @param enable Bit(s) to be enabled
* @param ready Bit(s) to be read for readiness
*/
void wait_for_ready(volatile uint32_t *reg, uint32_t enable, uint32_t ready);
#ifdef __cplusplus
}
#endif

18
test/interrupt.c
View File

@ -29,11 +29,20 @@ void my_isr(void)
interrupt_count++;
}
static volatile uint32_t enable_ready_reg;
static void set_ready_bit(void)
{
if (enable_ready_reg & BIT(0))
enable_ready_reg |= BIT(1);
}
void interrupt_generator(void)
{
while (1) {
udelay(3 * PERIOD_US(prng_no_seed()));
task_trigger_test_interrupt(my_isr);
task_trigger_test_interrupt(set_ready_bit);
}
}
@ -71,12 +80,21 @@ static int interrupt_disable_test(void)
return EC_SUCCESS;
}
static int test_wait_for_ready(void)
{
wait_for_ready(&enable_ready_reg, BIT(0), BIT(1));
TEST_EQ(enable_ready_reg, BIT(0) | BIT(1), "%x");
return EC_SUCCESS;
}
void run_test(int argc, char **argv)
{
test_reset();
RUN_TEST(interrupt_test);
RUN_TEST(interrupt_disable_test);
RUN_TEST(test_wait_for_ready);
test_print_result();
}