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Merge remote-tracking branch cros/main into firmware-corsola-15194.B-main 

Generated by: util/update_release_branch.py -r -z --board corsola
--relevant_paths_file util/corsola-relevant-paths.txt firmware-
corsola-15194.B-main

Relevant changes:

git log --oneline c5b9ec1eb4..772fc07be4 -- zephyr/program/corsola
common/charge_state.c common/dps.c common/mkbp_* common/usb_charger.c
common/usb_common.c common/usbc/*_pd_* common/usbc/dp_alt_mode.c
common/usbc/usb_pe_drp_sm.c common/usbc/usb_prl_sm.c
common/usbc/usb_sm.c common/usbc/usb_tc_drp_acc_trysrc_sm.c
driver/battery/smart.c driver/bc12/pi3usb9201.* driver/charger/isl923x.*
driver/charger/rt949* driver/ppc/nx20p348x.* driver/ppc/rt1718s.*
driver/ppc/syv682x.* driver/tcpm/anx7447.* driver/tcpm/rt1718s.*
driver/tcpm/tcpci.* driver/usb_mux/it5205.* driver/usb_mux/ps8743.*
power/mt8186.c zephyr/boards/arm/npcx9/* zephyr/boards/riscv/it8xxx2/*
zephyr/drivers/* zephyr/program/corsola/* zephyr/shim/*
util/getversion.sh

51bea3adfa zephyr: introduce a "finch" feature
85d7598eda Prepend *sleep() family functions with crec_
67d434dc15 corsola: Initial zephyr config for kyogre
1af04c1167 wugtrio: modify motionsense rotation matrix
f413cf1b30 Skitty: Initial Zephyr EC image
ac29be4c73 isl9238c: Add support for 5 mOhm sense resistors
8d523b29fe zephyr: add CONFIG_FLASH_PROTECT_RW/NEXT_BOOT
13b7d43937 zephyr: handle flags of console commands
8a08fe4af5 driver: add veml3328
217834a83c ec: Add #line to 3 files
7affa66953 PD_CONTROLLER: Add get_vconn_state API
a3c42064a1 zephyr: add PRINTF_LONG_IS_32BITS config
b5bc704a5f ppc/syv682x: Add CC status judgment after FRS trigger.
a15c4d8323 charge_state: change critical battery hibernate way
b5ea4d0990 util: Add druid to version string
c73578f4c7 zephyr: LED: Guard charge_state/battery calls by their configs
c900ecb807 pdc_rts54xx: Enable GET_CONNECTOR_STATUS
8fe913ce25 pdc_power_mgmt: Notify Hard Reset event
b1fe7db0fc PD_CONTROLLER: Add pd_set_new_power_request functionality
20509b86f9 Wugtrio: Initial zephyr config for wugtrio
79c663abfa brox: Add shims for EC_CMD_PD_CONTROL and enable
81ad5ebbcb usbpd: Move EC_CMD_PD_CONTROL and support func to common source
dcdf379695 pdc: Add API to suspend/resume chip communication
6961adf3bf buccaneer: Add buccaneer and *-druid to getversion.sh
01fd87251d zephyr: set Zephyr panic reason correctly
e6f8ab81b0 util/getversion.sh: Change case to align with style guide
a5cd6c238c ec: Add #line to z/s/chip/it8xxx2/power_policy.c
83b06f66d4 pdc: Print versions in decimal
314ef4563b hook: Add HOOK_INIT_EARLY
33e27683c8 helipilot: Add extra repo version strings
726d9ab4d0 zephyr/drivers/pdc_rts54xx: Define block read command
e4c5a7ce19 Tentacurel: Add new battery (38Wh)
38f92a6a16 starmie: Enable ACCEL_SPOOF_MODE for detachable projects
ff220d0d5f one_wire_uart: increase retry count
94fa496082 Keyboard: Check FIFO size only if MKBP keyboard is enabled
24a4e7b37f ppc/syv682x: clear the all flags during initialization
502ba64ad4 hid-over-i2c: implement GET_REPORT
2873bbe48b charge: drop CONFIG_USB_PD_PREFER_MV
ddc425ec53 pd_controller: Add port event API
abdedfc39c usbpd: Don't compile shim/src/tcpc.c for PDC devices
60d751ad50 PD_CONTROLLER: Add set active charge port shim functionality
2a29393f59 zephyr/drivers/pdc_rts54xx: Fix GET_RTK_STATUS result structure
cb4673224b zephyr: it8xxx2: fix incorrect PSTATE region size
917dcb720f rts54xx: Promote ping error to LOG_ERR

BUG=None
TEST=`make -j buildall`

Cq-Depend: chromium:5444116
Force-Relevant-Builds: all
Change-Id: I539fb7ef65eb37dfdaebe17b9d31da19002a94f0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/5445801
Tested-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
Auto-Submit: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Knox Chiou <knoxchiou@chromium.org>
This commit is contained in:
Eric Yilun Lin 2024-04-10 19:57:02 -07:00 committed by Chromeos LUCI
parent c5b9ec1eb4 772fc07be4
commit b707deaa78
726 changed files with 15635 additions and 4190 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
.gitlab-ci.yml
View File

@ -2,7 +2,7 @@
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
image: jbettis/ubuntu-23jan24
image: jbettis/ubuntu-05apr24
# You can update that image using this repo:
# https://gitlab.com/zephyr-ec/gitlab-ci-runner/-/tree/main
@ -172,7 +172,31 @@ before_script:
-o "${BUILD_DIR}/${PROJECT}/output/no_zephyr.info"
-r "${BUILD_DIR}/${PROJECT}/output/zephyr.info" "${ZEPHYR_BASE}/**"
"${MODULES_DIR}/**"
"${EC_DIR}/zephyr/drivers/**" "${EC_DIR}/zephyr/include/drivers/**"
"${EC_DIR}/zephyr/drivers/cros_displight/*"
"${EC_DIR}/zephyr/drivers/cros_flash/*"
"${EC_DIR}/zephyr/drivers/cros_kb_raw*"
"${EC_DIR}/zephyr/drivers/cros_kblight/*"
"${EC_DIR}/zephyr/drivers/cros_rtc/*"
"${EC_DIR}/zephyr/drivers/cros_shi/*"
"${EC_DIR}/zephyr/drivers/cros_system/*"
"${EC_DIR}/zephyr/drivers/cros_tabletmode_interrupt/*"
"${EC_DIR}/zephyr/drivers/fingerprint/*"
"${EC_DIR}/zephyr/drivers/keyboard_input/*"
"${EC_DIR}/zephyr/drivers/one_wire_uart/*"
"${EC_DIR}/zephyr/drivers/sm5803/*"
"${EC_DIR}/zephyr/drivers/vivaldi_kbd/*"
"${EC_DIR}/zephyr/include/drivers/cros_displight.h"
"${EC_DIR}/zephyr/include/drivers/cros_flash.h"
"${EC_DIR}/zephyr/include/drivers/cros_kb_raw.h"
"${EC_DIR}/zephyr/include/drivers/cros_rtc.h"
"${EC_DIR}/zephyr/include/drivers/cros_shi.h"
"${EC_DIR}/zephyr/include/drivers/cros_system.h"
"${EC_DIR}/zephyr/include/drivers/fingerprint_sim.h"
"${EC_DIR}/zephyr/include/drivers/fingerprint.h"
"${EC_DIR}/zephyr/include/drivers/one_wire_uart_internal.h"
"${EC_DIR}/zephyr/include/drivers/one_wire_uart_stream.h"
"${EC_DIR}/zephyr/include/drivers/one_wire_uart.h"
"${EC_DIR}/zephyr/include/drivers/vivaldi_kbd.h"
"${EC_DIR}/zephyr/shim/chip/**" "${EC_DIR}/zephyr/shim/core/**"
"/usr/include/**"
"${EC_DIR}/build/**" "${EC_DIR}/twister-out*/**"

6
README.md
View File

@ -374,9 +374,9 @@ Most code run on the EC after initialization is run in the context of a task
there is no heap (malloc). All variable storage must be explicitly declared at
build-time. The EC (and system) will reboot if any task has a stack overflow.
Tasks typically have a top-level loop with a call to task_wait_event() or
usleep() to set a delay in uSec before continuing. A watchdog will trigger if a
task runs for too long. The watchdog timeout varies by EC chip and the clock
speed the EC is running at.
crec_usleep() to set a delay in uSec before continuing. A watchdog will trigger
if a task runs for too long. The watchdog timeout varies by EC chip and the
clock speed the EC is running at.
The list of tasks for a board is specified in ec.tasklist in the `board/$BOARD/`
sub-directory. Tasks are listed in priority order with the lowest priority task

2
baseboard/asurada/board_id.c
View File

@ -53,7 +53,7 @@ static int adc_value_to_numeric_id(enum adc_channel ch)
gpio_set_level(GPIO_EN_EC_ID_ODL, 0);
/* Wait to allow cap charge */
msleep(10);
crec_msleep(10);
mv = adc_read_channel(ch);
if (mv == ADC_READ_ERROR)

2
baseboard/asurada/usb_pd_policy.c
View File

@ -108,7 +108,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
uint64_t now = get_time().val;
/* wait for the minimum spacing between IRQ_HPD if needed */
if (now < svdm_hpd_deadline[port])
usleep(svdm_hpd_deadline[port] - now);
crec_usleep(svdm_hpd_deadline[port] - now);
/* generate IRQ_HPD pulse */
svdm_set_hpd_gpio(port, 0);

9
baseboard/bloonchipper/base_ec.tasklist
View File

@ -3,12 +3,19 @@
* found in the LICENSE file.
*/
/* If we are actually using DRUID in the FP task, we need a bigger stack. */
#ifdef CONFIG_LIB_DRUID_WRAPPER
#define FPSENSOR_TASK_STACK_SIZE 20240
#else
#define FPSENSOR_TASK_STACK_SIZE 4096
#endif
/**
* See CONFIG_TASK_LIST in config.h for details.
*/
#define BASEBOARD_CONFIG_TASK_LIST \
TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, 4096) \
TASK_ALWAYS_RW(FPSENSOR, fp_task, NULL, FPSENSOR_TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 6144) \
TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)

2
baseboard/bloonchipper/fpsensor_detect.c
View File

@ -13,7 +13,7 @@ test_mockable enum fp_transport_type get_fp_transport_type(void)
enum fp_transport_type ret;
gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
usleep(1);
crec_usleep(1);
switch (gpio_get_level(GPIO_TRANSPORT_SEL)) {
case 0:
ret = FP_TRANSPORT_TYPE_UART;

2
baseboard/bloonchipper/fpsensor_detect_rw.c
View File

@ -13,7 +13,7 @@ test_mockable enum fp_sensor_type fpsensor_detect_get_type(void)
enum fp_sensor_type ret;
gpio_set_level(GPIO_DIVIDER_HIGHSIDE, 1);
usleep(1);
crec_usleep(1);
switch (gpio_get_level(GPIO_FP_SENSOR_SEL)) {
case 0:
ret = FP_SENSOR_TYPE_ELAN;

2
baseboard/brask/usb_pd_policy.c
View File

@ -207,7 +207,7 @@ static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
* before sending the reply without violating that timer.
*/
if (!usb_mux_set_completed(port))
usleep(PD_T_VDM_E_MODE / 2);
crec_usleep(PD_T_VDM_E_MODE / 2);
CPRINTS("UFP Enter TBT mode");
return 1; /* ACK */

2
baseboard/brya/usb_pd_policy.c
View File

@ -247,7 +247,7 @@ static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
* before sending the reply without violating that timer.
*/
if (!usb_mux_set_completed(port))
usleep(PD_T_VDM_E_MODE / 2);
crec_usleep(PD_T_VDM_E_MODE / 2);
CPRINTS("UFP Enter TBT mode");
return 1; /* ACK */

2
baseboard/cherry/usb_pd_policy.c
View File

@ -119,7 +119,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
uint64_t now = get_time().val;
/* wait for the minimum spacing between IRQ_HPD if needed */
if (now < svdm_hpd_deadline[port])
usleep(svdm_hpd_deadline[port] - now);
crec_usleep(svdm_hpd_deadline[port] - now);
/* generate IRQ_HPD pulse */
svdm_set_hpd_gpio(port, 0);

2
baseboard/goroh/board_id.c
View File

@ -53,7 +53,7 @@ static int adc_value_to_numeric_id(enum adc_channel ch)
gpio_set_level(GPIO_EN_EC_ID_ODL, 0);
/* Wait to allow cap charge */
msleep(10);
crec_msleep(10);
mv = adc_read_channel(ch);
if (mv == ADC_READ_ERROR)

16
baseboard/grunt/baseboard.c
View File

@ -216,14 +216,14 @@ void board_set_tcpc_power_mode(int port, int mode)
switch (mode) {
case ANX74XX_NORMAL_MODE:
gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 1);
msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
break;
case ANX74XX_STANDBY_MODE:
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
crec_msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0);
msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
break;
default:
break;
@ -241,7 +241,7 @@ void board_reset_pd_mcu(void)
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
/* TCPC1 (ps8751) requires 1ms reset down assertion */
msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
crec_msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
/* Deassert reset to TCPC1 */
gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
@ -251,18 +251,18 @@ void board_reset_pd_mcu(void)
/*
* anx3429 requires 10ms reset/power down assertion
*/
msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
/* Assert reset to TCPC0 (anx3447) */
gpio_set_level(GPIO_USB_C0_PD_RST, 1);
msleep(ANX74XX_RESET_HOLD_MS);
crec_msleep(ANX74XX_RESET_HOLD_MS);
gpio_set_level(GPIO_USB_C0_PD_RST, 0);
msleep(ANX74XX_RESET_FINISH_MS);
crec_msleep(ANX74XX_RESET_FINISH_MS);
/* Assert reset to TCPC1 (ps8751) */
gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
msleep(PS8XXX_RESET_DELAY_MS);
crec_msleep(PS8XXX_RESET_DELAY_MS);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
#endif
}

10
baseboard/guybrush/baseboard.c
View File

@ -586,11 +586,11 @@ static void reset_nct38xx_port(int port)
}
gpio_set_level(reset_gpio_l, 0);
msleep(NCT38XX_RESET_HOLD_DELAY_MS);
crec_msleep(NCT38XX_RESET_HOLD_DELAY_MS);
gpio_set_level(reset_gpio_l, 1);
nct38xx_reset_notify(port);
if (NCT3807_RESET_POST_DELAY_MS != 0)
msleep(NCT3807_RESET_POST_DELAY_MS);
crec_msleep(NCT3807_RESET_POST_DELAY_MS);
/* Re-init ioex after resetting the TCPC */
ioex_init(port);
@ -711,7 +711,7 @@ void board_pwrbtn_to_pch(int level)
if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) {
start = get_time();
do {
usleep(200);
crec_usleep(200);
if (gpio_get_level(GPIO_PCH_RSMRST_L))
break;
} while (time_since32(start) < timeout_rsmrst_rise_us);
@ -719,7 +719,7 @@ void board_pwrbtn_to_pch(int level)
if (!gpio_get_level(GPIO_PCH_RSMRST_L))
ccprints("Error pwrbtn: RSMRST_L still low");
msleep(G3_TO_PWRBTN_DELAY_MS);
crec_msleep(G3_TO_PWRBTN_DELAY_MS);
}
gpio_set_level(GPIO_PCH_PWRBTN_L, level);
}
@ -740,7 +740,7 @@ void board_hibernate(void)
pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
/* Give PD task and PPC chip time to get to 5V */
msleep(SAFE_RESET_VBUS_DELAY_MS);
crec_msleep(SAFE_RESET_VBUS_DELAY_MS);
}
/* Try to put our battery fuel gauge into sleep mode */

6
baseboard/hatch/baseboard.c
View File

@ -176,7 +176,7 @@ void board_hibernate(void)
* needs time to work through the transitions. Also, it
* works.
*/
msleep(300);
crec_msleep(300);
}
/******************************************************************************/
@ -252,10 +252,10 @@ static void reset_pd_port(int port, enum gpio_signal reset_gpio, int hold_delay,
int level = !!(tcpc_config[port].flags & TCPC_FLAGS_RESET_ACTIVE_HIGH);
gpio_set_level(reset_gpio, level);
msleep(hold_delay);
crec_msleep(hold_delay);
gpio_set_level(reset_gpio, !level);
if (finish_delay)
msleep(finish_delay);
crec_msleep(finish_delay);
}
void board_reset_pd_mcu(void)

10
baseboard/helipilot/base_board.c
View File

@ -11,7 +11,6 @@
#include "fpsensor/fpsensor_detect.h"
#include "gpio.h"
#include "hooks.h"
#include "otp_key.h"
#include "registers.h"
#include "shi_chip.h"
#include "spi.h"
@ -103,17 +102,14 @@ static void board_init(void)
/* Enable interrupt on PCH power signals */
gpio_enable_interrupt(GPIO_SLP_L);
if (IS_ENABLED(SECTION_IS_RW)) {
board_init_rw();
}
/* Initialize trng peripheral before kicking off the application to
* avoid incurring that cost when generating random numbers
*/
npcx_trng_hw_init();
/* Power on OTP Memory */
otp_key_init();
if (IS_ENABLED(SECTION_IS_RW)) {
board_init_rw();
}
/*
* Enable the SPI slave interface if the PCH is up.

11
baseboard/helipilot/base_board.h
View File

@ -286,17 +286,6 @@
*-------------------------------------------------------------------------*
*/
/*
* Macros for GPIO signals used in common code that don't match the
* schematic names. Signal names in gpio.inc match the schematic and are
* then redefined here to so it's more clear which signal is being used for
* which purpose.
*/
#define GPIO_WP GPIO_HOST_MCU_WP_OD
#define GPIO_SHI_CS_L GPIO_SPI_HOST_CS_MCU_ODL
#define GPIO_FPS_INT GPIO_FP_MCU_INT_L
#define GPIO_EC_INT_L GPIO_MCU_PLATFORM_INT_L
#ifndef __ASSEMBLER__
#include "base_board_rw.h"

5
baseboard/helipilot/base_board_rw.c
View File

@ -19,13 +19,10 @@
/* TODO(b/279096907): Investigate de-duping with other FPMCU boards*/
/* create alias to fit spi_devices declaration in 80 chars */
#define FP_SPI_CS GPIO_SPI_MCU_CS_FP_L
/* SPI devices */
const struct spi_device_t spi_devices[] = {
/* Fingerprint sensor (SCLK at 4Mhz) */
{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = FP_SPI_CS }
{ .port = CONFIG_SPI_FP_PORT, .div = 3, .gpio_cs = GPIO_FP_SPI_CS }
};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);

10
baseboard/helipilot/base_gpio.inc
View File

@ -5,10 +5,11 @@
*/
/* Interrupts */
GPIO_INT(HOST_MCU_WP_OD, PIN(A, 4), GPIO_INT_BOTH, switch_interrupt)
/* HOST_MCU_WP_OD in the schematic. */
GPIO_INT(WP, PIN(A, 4), GPIO_INT_BOTH, switch_interrupt)
/* SHI CS Ready, Low Active. */
GPIO_INT(SPI_HOST_CS_MCU_ODL, PIN(5, 3), GPIO_INT_FALLING,shi_cs_event)
/* SHI CS Ready, Low Active. SPI_HOST_CS_MCU_ODL in the schematic. */
GPIO_INT(SHI_CS_L, PIN(5, 3), GPIO_INT_FALLING,shi_cs_event)
GPIO_INT(SLP_L, PIN(A, 0), GPIO_INT_BOTH, slp_event)
/* Inputs */
@ -21,7 +22,8 @@ GPIO(TRANSPORT_SEL, PIN(4, 3), GPIO_INPUT)
GPIO(SPI_HOST_DO_MCU_DI, PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
GPIO(SPI_HOST_DI_MCU_DO, PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
GPIO(SPI_HOST_CLK_MCU, PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
GPIO(MCU_PLATFORM_INT_L, PIN(A, 7), GPIO_ODR_HIGH)
/* MCU_PLATFORM_INT_L in the schematic. */
GPIO(EC_INT_L, PIN(A, 7), GPIO_ODR_HIGH)
/* Outputs */
GPIO(DIVIDER_HIGHSIDE, PIN(9, 3), GPIO_OUT_LOW)

7
baseboard/helipilot/base_gpio_rw.inc
View File

@ -9,14 +9,17 @@
#endif
/* Interrupts */
GPIO_INT(FP_MCU_INT_L, PIN(B, 0), GPIO_INT_RISING, fps_event)
/* FP_MCU_INT_L in the schematic. */
GPIO_INT(FPS_INT, PIN(B, 0), GPIO_INT_RISING, fps_event)
/* Inputs */
GPIO(FP_SENSOR_SEL, PIN(4, 4), GPIO_INPUT)
/* Outputs */
GPIO(FP_RST_ODL, PIN(9, 6), GPIO_OUT_HIGH)
GPIO(SPI_MCU_CS_FP_L, PIN(A, 6), GPIO_OUT_HIGH)
/* SPI_MCU_CS_FP_L in the schematic. */
GPIO(FP_SPI_CS, PIN(A, 6), GPIO_OUT_HIGH)
GPIO(USER_PRES_L, PIN(A, 5), GPIO_ODR_HIGH)
/* SPIP - to fingerprint sensor */
/* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */

12
baseboard/honeybuns/baseboard.c
View File

@ -68,7 +68,7 @@ __maybe_unused static void board_power_sequence(int enable)
board_power_seq[i].level);
CPRINTS("power seq: rail = %d", i);
if (board_power_seq[i].delay_ms)
msleep(board_power_seq[i].delay_ms);
crec_msleep(board_power_seq[i].delay_ms);
}
} else {
for (i = board_power_seq_count - 1; i >= 0; i--) {
@ -171,10 +171,10 @@ void baseboard_set_mst_lane_control(int mf)
if (mf != gpio_get_level(GPIO_MST_HUB_LANE_SWITCH)) {
/* put MST into reset */
gpio_set_level(GPIO_MST_RST_L, 0);
msleep(1);
crec_msleep(1);
gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, mf);
CPRINTS("MST: lane control = %s", mf ? "high" : "low");
msleep(1);
crec_msleep(1);
/* lane control is set, take MST out of reset */
gpio_set_level(GPIO_MST_RST_L, 1);
}
@ -187,7 +187,7 @@ static void baseboard_enable_mp4245(void)
mp4245_set_voltage_out(5000);
mp4245_votlage_out_enable(1);
msleep(MP4245_VOUT_5V_DELAY_MS);
crec_msleep(MP4245_VOUT_5V_DELAY_MS);
mp3245_get_vbus(&mv, &ma);
CPRINTS("mp4245: vout @ %d mV enabled", mv);
}
@ -281,7 +281,7 @@ static void baseboard_power_on(void)
*/
for (port = 0; port < port_max; port++) {
ppc_init(port);
msleep(1000);
crec_msleep(1000);
/* Inform TC state machine that it can resume */
pd_set_suspend(port, 0);
}
@ -336,7 +336,7 @@ static void baseboard_toggle_mf(void)
* take effect.
*/
pd_set_suspend(USB_PD_PORT_HOST, 1);
msleep(250);
crec_msleep(250);
pd_set_suspend(USB_PD_PORT_HOST, 0);
}
}

2
baseboard/honeybuns/usb_pd_policy.c
View File

@ -288,7 +288,7 @@ void pd_transition_voltage(int idx)
* msec. The max loop count and this sleep time gives plenty
* of time for this change.
*/
msleep(2);
crec_msleep(2);
}
CPRINTS("usbc[%d]: Vbus transition timeout: target = %d, measure = %d",

2
baseboard/honeybuns/usbc_support.c
View File

@ -72,7 +72,7 @@ static int baseboard_ppc_enable_sink_path(int port)
status = write_reg(port, SN5S330_FUNC_SET1, SN5S330_ILIM_3_06);
if (status) {
retries++;
msleep(1);
crec_msleep(1);
} else {
break;
}

6
baseboard/intelrvp/adlrvp.c
View File

@ -326,7 +326,7 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* retimer_init() function ensures power is up before calling
* this function.
*/
msleep(1);
crec_msleep(1);
ioex_set_level((enum ioex_signal)bb_controls[me->usb_port]
.retimer_rst_gpio,
1);
@ -335,13 +335,13 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level((enum ioex_signal)bb_controls[me->usb_port]
.retimer_rst_gpio,
0);
msleep(1);
crec_msleep(1);
ioex_set_level((enum ioex_signal)bb_controls[me->usb_port]
.usb_ls_en_gpio,
0);

2
baseboard/intelrvp/baseboard.c
View File

@ -150,7 +150,7 @@ int ioexpander_read_intelrvp_version(int *port0, int *port1)
PCA9555_CMD_INPUT_PORT_1, port1))
return 0;
msleep(1);
crec_msleep(1);
}
/* pca9555 read failed */

2
baseboard/kalista/baseboard.c
View File

@ -217,7 +217,7 @@ const int usb_port_enable[USB_PORT_COUNT] = {
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
msleep(1);
crec_msleep(1);
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
}

2
baseboard/kukui/baseboard.c
View File

@ -156,7 +156,7 @@ int board_get_version(void)
gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 0);
/* Wait to allow cap charge */
msleep(20);
crec_msleep(20);
mv = adc_read_channel(ADC_BOARD_ID);
if (mv == ADC_READ_ERROR)

1
baseboard/kukui/baseboard.h
View File

@ -55,7 +55,6 @@
* 12.85V * 1.05 = 13.5V
*/
#define PD_MAX_VOLTAGE_MV 12850
#define CONFIG_USB_PD_PREFER_MV
#elif defined(VARIANT_KUKUI_CHARGER_ISL9238)
#define CONFIG_CHARGER_ISL9238C
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */

119
baseboard/kukui/charger_mt6370.c
View File

@ -17,39 +17,6 @@
#include "util.h"
#define BAT_LEVEL_PD_LIMIT 85
#define SYSTEM_PLT_MW 3500
/*
* b/143318064: Prefer a voltage above 5V to force it picks a voltage
* above 5V at first. If PREFER_MV is 5V, when desired power is around
* 15W ~ 11W, it would pick 5V/3A initially, and mt6370 can only sink
* around 10W, and cause a low charging efficiency.
*/
#define PREVENT_CURRENT_DROP_MV 6000
#define DEFAULT_PREFER_MV 5000
/*
* We empirically chose 300mA as the limit for when buck inefficiency is
* noticeable.
*/
#define STABLE_CURRENT_DELTA 300
struct pd_pref_config_t pd_pref_config = {
.mv = PREVENT_CURRENT_DROP_MV,
.cv = 70,
.plt_mw = SYSTEM_PLT_MW,
.type = PD_PREFER_BUCK,
};
static void update_plt_suspend(void)
{
pd_pref_config.plt_mw = 0;
}
DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, update_plt_suspend, HOOK_PRIO_DEFAULT);
static void update_plt_resume(void)
{
pd_pref_config.plt_mw = SYSTEM_PLT_MW;
}
DECLARE_HOOK(HOOK_CHIPSET_RESUME, update_plt_resume, HOOK_PRIO_DEFAULT);
#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
@ -170,90 +137,6 @@ static int command_jc(int argc, const char **argv)
}
DECLARE_CONSOLE_COMMAND(jc, command_jc, "", "mt6370 junction temp");
/*
* b/143318064: A workwround for mt6370 bad buck efficiency.
* If the delta of VBUS and VBAT(on krane, desired voltage 4.4V) is too small
* (i.e. < 500mV), the buck throughput will be bounded, and causing that we
* can't drain 5V/3A when battery SoC above around 40%.
* This function watches battery current. If we see battery current drops after
* switching from high voltage to 5V (This will happen if we enable
* CONFIG_USB_PD_PREFER_MV and set prefer votage to 5V), the charger will lost
* power due to the inefficiency (e.g. switch from 9V/1.67A = 15W to 5V/3A,
* but mt6370 would only sink less than 5V/2.4A = 12W), and we will request a
* higher voltage PDO to prevent a slow charging time.
*/
static void battery_desired_curr_dynamic(struct charge_state_data *curr)
{
static int prev_stable_current = CHARGE_CURRENT_UNINITIALIZED;
static int prev_supply_voltage;
int supply_voltage;
int stable_current;
int delta_current;
if (curr->state != ST_CHARGE) {
prev_supply_voltage = 0;
prev_stable_current = CHARGE_CURRENT_UNINITIALIZED;
/*
* Always force higher voltage on first PD negotiation.
* When desired power is around 15W ~ 11W, PD would pick
* 5V/3A initially, but mt6370 can't drain that much, and
* causes a low charging efficiency.
*/
pd_pref_config.mv = PREVENT_CURRENT_DROP_MV;
return;
}
supply_voltage = charge_manager_get_charger_voltage();
stable_current = charge_get_stable_current();
if (!charge_is_current_stable())
return;
if (!prev_supply_voltage)
goto update_charge;
delta_current = prev_stable_current - stable_current;
if (curr->batt.state_of_charge >= pd_pref_config.cv &&
supply_voltage == DEFAULT_PREFER_MV &&
prev_supply_voltage > supply_voltage &&
delta_current > STABLE_CURRENT_DELTA) {
/* Raise perfer voltage above 5000mV */
pd_pref_config.mv = PREVENT_CURRENT_DROP_MV;
/*
* Delay stable current evaluation for 5 mins if we see a
* current drop. It's a reasonable waiting time since that
* the battery desired current can't catch the gap that fast
* in the period.
*/
charge_reset_stable_current_us(5 * MINUTE);
/* Rewrite the stable current to re-evalute desired watt */
charge_set_stable_current(prev_stable_current);
/*
* do not alter current by thermal if we just raising PD
* voltage
*/
thermal_wait_until.val = get_time().val + (10 * SECOND);
} else {
pd_pref_config.mv = DEFAULT_PREFER_MV;
/*
* If the power supply is plugged while battery full,
* the stable_current will always be 0 such that we are unable
* to switch to 5V. We force evaluating PDO to switch to 5V.
*/
if (prev_supply_voltage == supply_voltage && !stable_current &&
!prev_stable_current &&
supply_voltage != DEFAULT_PREFER_MV &&
charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
pd_set_new_power_request(
charge_manager_get_active_charge_port());
}
update_charge:
prev_supply_voltage = supply_voltage;
prev_stable_current = stable_current;
}
#ifdef CONFIG_BATTERY_SMART
static void charge_enable_eoc_and_te(void)
{
@ -268,8 +151,6 @@ void mt6370_charger_profile_override(struct charge_state_data *curr)
static int previous_chg_limit_mv;
int chg_limit_mv = pd_get_max_voltage();
battery_desired_curr_dynamic(curr);
battery_thermal_control(curr);
#ifdef CONFIG_BATTERY_SMART

4
baseboard/kukui/usb_pd_policy.c
View File

@ -257,11 +257,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
uint64_t now = get_time().val;
/* wait for the minimum spacing between IRQ_HPD if needed */
if (now < svdm_hpd_deadline[port])
usleep(svdm_hpd_deadline[port] - now);
crec_usleep(svdm_hpd_deadline[port] - now);
/* generate IRQ_HPD pulse */
gpio_set_level(GPIO_USB_C0_HPD_OD, 0);
usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
crec_usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
gpio_set_level(GPIO_USB_C0_HPD_OD, 1);
#ifdef VARIANT_KUKUI_DP_MUX_GPIO

2
baseboard/mtscp-rv32i/OWNERS Normal file
View File

@ -0,0 +1,2 @@
# MT8188 / Geralt SCP
fshao@chromium.org

25
baseboard/mtscp-rv32i/baseboard.c
View File

@ -18,17 +18,22 @@ struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = {
/* SRAM (for IPI shared buffer) */
{ SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R },
/* For AP domain */
#ifdef CHIP_VARIANT_MT8195
{ 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P },
#if defined(CHIP_VARIANT_MT8195) || defined(CHIP_VARIANT_MT8188)
{ AP_REG_BASE, AP_REG_BASE + 0x10000000,
MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P },
#else
{ 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R },
{ AP_REG_BASE, AP_REG_BASE + 0x10000000, MPU_ATTR_W | MPU_ATTR_R },
#endif
#if !defined(CHIP_VARIANT_MT8188)
/* For SCP sys */
{ 0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R },
#ifdef CHIP_VARIANT_MT8195
{ 0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R },
{ CONFIG_PANIC_DRAM_BASE,
CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE,
#endif
#if defined(CHIP_VARIANT_MT8195) || defined(CHIP_VARIANT_MT8188)
{ CONFIG_DRAM_BASE, DRAM_NC_BASE,
MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R },
{ DRAM_NC_BASE, (unsigned int)KERNEL_BASE + (unsigned int)KERNEL_SIZE,
MPU_ATTR_W | MPU_ATTR_R },
#else
{ 0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R },
@ -43,7 +48,7 @@ static void report_previous_panic(void)
{
struct panic_data *panic = panic_get_data();
if (panic == NULL && SCP_CORE0_MON_PC_LATCH == 0)
if (panic == NULL && SCP_CORE_MON_PC_LATCH == 0)
return;
ccprintf("[Previous Panic]\n");
@ -52,8 +57,8 @@ static void report_previous_panic(void)
} else {
ccprintf("No panic data\n");
}
ccprintf("Latch PC:%x LR:%x SP:%x\n", SCP_CORE0_MON_PC_LATCH,
SCP_CORE0_MON_LR_LATCH, SCP_CORE0_MON_SP_LATCH);
ccprintf("Latch PC:%x LR:%x SP:%x\n", SCP_CORE_MON_PC_LATCH,
SCP_CORE_MON_LR_LATCH, SCP_CORE_MON_SP_LATCH);
}
DECLARE_HOOK(HOOK_INIT, report_previous_panic, HOOK_PRIO_DEFAULT);
#endif

127
baseboard/mtscp-rv32i/baseboard.h
View File

@ -13,14 +13,18 @@
#define CONFIG_FLASH_SIZE_BYTES CONFIG_RAM_BASE
#define CONFIG_LTO
#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
#define CONFIG_UART_CONSOLE 0
#ifdef CHIP_VARIANT_MT8195
#define CONFIG_PANIC_CONSOLE_OUTPUT
#if defined(BOARD_CHERRY_SCP_CORE1) || defined(BOARD_GERALT_SCP_CORE1)
#undef CONFIG_LTO
#define SCP_CORE_SN 1
#define CONFIG_UART_CONSOLE 1
#else
#define SCP_CORE_SN 0
#define CONFIG_UART_CONSOLE 0
#endif
/* IPI configs */
#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 600
#define CONFIG_IPC_SHARED_OBJ_ADDR \
(SCP_FW_END - \
(CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
@ -43,28 +47,121 @@
#define SCP_IPI_HOST_COMMAND 13
#define SCP_IPI_VDEC_LAT 14
#define SCP_IPI_VDEC_CORE 15
#define SCP_IPI_COUNT 16
#define SCP_IPI_ISP_IMG_CMD 16
#define SCP_IPI_COUNT 17
#define IPI_COUNT SCP_IPI_COUNT
#define SCP_IPI_NS_SERVICE 0xFF
/* Access DRAM through cached access */
/*
* (1) DRAM cacheable region
* (2) DRAM non-cacheable region
* (3) Panic data region
* (4) Kernel DMA allocable region
* (5) DRAM end address
*
* base (size)
* ---+-------------------- (1) CONFIG_DRAM_BASE (CONFIG_DRAM_SIZE)
* C | DRAM .text, .rodata
* | DRAM .data LMA
* | DRAM .bss, .data
* ---+-------------------- (2) DRAM_NC_BASE (DRAM_NC_SIZE)
* NC | .dramnc
* +-------------------- (3) CONFIG_PANIC_DRAM_BASE (CONFIG_PANIC_DRAM_SIZE)
* | Panic Data
* +-------------------- (4) KERNEL_BASE (KERNEL_SIZE)
* | Kernel DMA allocable
* | for MDP, etc.
* ---+-------------------- (5) CONFIG_DRAM_SIZE + DRAM_TOTAL_SIZE (NA)
*
* base size
* MT8192
* (1) 0x10000000 0x500000
* (2) 0x10500000 0
* (3) 0x10500000 0
* (4) 0x10500000 0xF00000
* (5) 0x11400000
* MT8195 core0
* (1) 0x10000000 0x4FF000
* (2) 0x104FF000 0
* (3) 0x104FF000 0x1000
* (4) 0x10500000 0xF00000
* (5) 0x11400000
* MT8195 core1
* (1) 0x20000000 0x003FF000
* (2) 0x203FF000 0
* (3) 0x203FF000 0x00001000
* (4) 0x20400000 0x0CC00000
* (5) 0x2D000000
* MT8188
* (1) 0x50000000 0x500000
* (2) 0x504FF000 0
* (3) 0x504FF000 0x1000
* (4) 0x50500000 0xF00000
* (5) 0x51400000
*/
/* size of (1) */
#define CONFIG_DRAM_SIZE \
(DRAM_TOTAL_SIZE - CONFIG_PANIC_DRAM_SIZE - DRAM_NC_SIZE - KERNEL_SIZE)
/* base of (2) */
#define DRAM_NC_BASE (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE)
/* base of (3) */
#define CONFIG_PANIC_DRAM_BASE (DRAM_NC_BASE + DRAM_NC_SIZE)
/* base of (4) */
#define KERNEL_BASE (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE)
#if defined(CHIP_VARIANT_MT8192)
/* base of (1) */
#define CONFIG_DRAM_BASE 0x10000000
/* Shared memory address in AP physical address space. */
#define CONFIG_DRAM_BASE_LOAD 0x50000000
#define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */
/* size of (2) */
#define DRAM_NC_SIZE 0
/* size of (3) */
#define CONFIG_PANIC_DRAM_SIZE 0
/* size of (4) */
#define KERNEL_SIZE 0xF00000
/* DRAM total size for (5) */
#define DRAM_TOTAL_SIZE 0x01400000 /* 20 MB */
#endif /* CHIP_VARIANT_MT8192 */
/* Add some space (0x100) before panic for jump data */
#define CONFIG_PANIC_DRAM_BASE (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE)
#if defined(CHIP_VARIANT_MT8195)
#if defined(BOARD_CHERRY_SCP_CORE1)
#define CONFIG_DRAM_BASE 0x20000000
#define CONFIG_DRAM_BASE_LOAD 0x70000000
#define DRAM_NC_SIZE 0x0
#define CONFIG_PANIC_DRAM_SIZE 0x00001000 /* 4K */
#define KERNEL_SIZE 0x0CC00000 /* 204 MB */
#define DRAM_TOTAL_SIZE 0x0D000000 /* 208 MB */
#else
#define CONFIG_DRAM_BASE 0x10000000
#define CONFIG_DRAM_BASE_LOAD 0x50000000
#define DRAM_NC_SIZE 0
#define CONFIG_PANIC_DRAM_SIZE 0x00001000 /* 4K */
#define KERNEL_SIZE 0xF00000
#define DRAM_TOTAL_SIZE 0x01400000 /* 20 MB */
#endif /* BOARD_CHERRY_SCP_CORE1 */
#endif /* CHIP_VARIANT_MT8195 */
#define CONFIG_PANIC_BASE_OFFSET 0x100 /* reserved for jump data */
#ifdef CHIP_VARIANT_MT8195
#define CONFIG_PANIC_DATA_BASE \
(CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET)
#endif
#if defined(CHIP_VARIANT_MT8188)
#if defined(BOARD_GERALT_SCP_CORE1)
#define CONFIG_DRAM_BASE 0x70000000
#define CONFIG_DRAM_BASE_LOAD 0x70000000
#define DRAM_NC_SIZE 0x0
#define CONFIG_PANIC_DRAM_SIZE 0x00001000 /* 4K */
#define KERNEL_SIZE 0x05000000 /* 204 MB */
#define DRAM_TOTAL_SIZE 0x12000000 /* 208 MB */
#else
#define CONFIG_DRAM_BASE 0x50000000
#define CONFIG_DRAM_BASE_LOAD 0x50000000
#define DRAM_NC_SIZE 0
#define CONFIG_PANIC_DRAM_SIZE 0x00001000 /* 4K */
#define KERNEL_SIZE 0xF00000
#define DRAM_TOTAL_SIZE 0x01800000 /* 24 MB */
#endif /* BOARD_GERALT_SCP_CORE1 */
#endif /* CHIP_VARIANT_MT8188 */
/* MPU settings */
#define NR_MPU_ENTRIES 16

1
baseboard/mtscp-rv32i/build.mk
View File

@ -10,3 +10,4 @@ baseboard-y+=baseboard.o
baseboard-$(HAS_TASK_VDEC_SERVICE)+=vdec.o
baseboard-$(HAS_TASK_VENC_SERVICE)+=venc.o
baseboard-$(HAS_TASK_MDP_SERVICE)+=mdp.o
baseboard-$(HAS_TASK_CAM_SERVICE)+=cam.o

159
baseboard/mtscp-rv32i/cam.c Normal file
View File

@ -0,0 +1,159 @@
/* Copyright 2024 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "cam.h"
#include "console.h"
#include "dma.h"
#include "ipi_chip.h"
#include "queue_policies.h"
#include "registers.h"
#include "task.h"
#include "util.h"
#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
/* Forwad declaration. */
static struct consumer const event_cam_consumer;
#if defined(BOARD_GERALT_SCP_CORE1)
static struct consumer const event_img_consumer;
#endif
static void event_cam_written(struct consumer const *consumer, size_t count);
#if defined(BOARD_GERALT_SCP_CORE1)
static void event_img_written(struct consumer const *consumer, size_t count);
#endif
static struct queue const event_cam_queue =
QUEUE_DIRECT(8, struct cam_msg, null_producer, event_cam_consumer);
#if defined(BOARD_GERALT_SCP_CORE1)
static struct queue const event_img_queue =
QUEUE_DIRECT(32, struct cam_msg, null_producer, event_img_consumer);
#endif
static struct consumer const event_cam_consumer = {
.queue = &event_cam_queue,
.ops = &((struct consumer_ops const){
.written = event_cam_written,
}),
};
#if defined(BOARD_GERALT_SCP_CORE1)
static struct consumer const event_img_consumer = {
.queue = &event_img_queue,
.ops = &((struct consumer_ops const){
.written = event_img_written,
}),
};
#endif
/* Stub functions only provided by private overlays. */
#ifndef HAVE_PRIVATE_MT_SCP_CORE1
void ipi_cam_handler(void *data)
{
}
void ipi_img_handler(void *data)
{
}
int32_t startRED(void)
{
return 0;
}
void img_task_handler(void)
{
}
#endif
static void event_cam_written(struct consumer const *consumer, size_t count)
{
task_wake(TASK_ID_CAM_SERVICE);
}
#if defined(BOARD_GERALT_SCP_CORE1)
static void event_img_written(struct consumer const *consumer, size_t count)
{
task_wake(TASK_ID_IMG_SERVICE);
}
#endif
static void cam_ipi_handler(int id, void *data, uint32_t len)
{
struct cam_msg rsv_msg;
int ret = 0;
if (!len)
return;
rsv_msg.id = id;
memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg)));
/*
* If there is no other IPI handler touch this queue, we don't need to
* interrupt_disable() or task_disable_irq().
*/
if (id == SCP_IPI_ISP_CMD || id == SCP_IPI_ISP_FRAME)
ret = queue_add_unit(&event_cam_queue, &rsv_msg);
#if defined(BOARD_GERALT_SCP_CORE1)
else
ret = queue_add_unit(&event_img_queue, &rsv_msg);
#endif
if (!ret)
CPRINTS("Could not send ipi cmd %d to the queue", id);
}
DECLARE_IPI(SCP_IPI_ISP_CMD, cam_ipi_handler, 0);
DECLARE_IPI(SCP_IPI_ISP_FRAME, cam_ipi_handler, 0);
DECLARE_IPI(SCP_IPI_ISP_IMG_CMD, cam_ipi_handler, 0);
/* This function renames from cam_service_entry. */
void cam_service_task(void *u)
{
struct cam_msg rsv_msg;
size_t size;
while (1) {
/*
* Queue unit is added in IPI handler, which is in ISR context.
* Disable IRQ to prevent a clobbered queue.
*/
ipi_disable_irq();
size = queue_remove_unit(&event_cam_queue, &rsv_msg);
ipi_enable_irq();
if (!size)
task_wait_event(-1);
else
ipi_cam_handler(&rsv_msg);
}
}
#if defined(BOARD_GERALT_SCP_CORE1)
void img_service_task(void *u)
{
struct cam_msg rsv_msg;
size_t size;
while (1) {
/*
* Queue unit is added in IPI handler, which is in ISR context.
* Disable IRQ to prevent a clobbered queue.
*/
ipi_disable_irq();
size = queue_remove_unit(&event_img_queue, &rsv_msg);
ipi_enable_irq();
if (!size) {
if (img_task_working)
task_wake(TASK_ID_IMG_HANDLER);
else
task_wait_event(-1);
} else
ipi_img_handler(&rsv_msg);
}
}
void img_handler_task(void *u)
{
CPRINTS("img_handler_task");
startRED();
img_task_handler();
}
#endif

35
baseboard/mtscp-rv32i/cam.h Normal file
View File

@ -0,0 +1,35 @@
/* Copyright 2024 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef __CROS_EC_CAM_SRV_H
#define __CROS_EC_CAM_SRV_H
#include "ipi_chip.h"
#include <stdbool.h>
/*
* IMPORTANT:
* Please check MAX_MTKCAM_IPI_EVENT_SIZE if IPI message structure changes
*/
#define MAX_MTKCAM_IPI_EVENT_SIZE 588
struct cam_msg {
unsigned char id;
unsigned char msg[MAX_MTKCAM_IPI_EVENT_SIZE];
};
BUILD_ASSERT(member_size(struct cam_msg, msg) <=
CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
/* Functions provided by private overlay. */
void ipi_cam_handler(void *data);
#if defined(BOARD_GERALT_SCP_CORE1)
void ipi_img_handler(void *data);
int32_t startRED(void);
void img_task_handler(void);
bool img_task_working = false;
#endif
#endif /* __CROS_EC_CAM_SRV_H */

2
baseboard/mtscp-rv32i/mdp.c
View File

@ -29,7 +29,7 @@ static struct consumer const event_mdp_consumer = {
};
/* Stub functions only provided by private overlays. */
#ifndef HAVE_PRIVATE_MT_SCP
#if !defined(HAVE_PRIVATE_MT_SCP) || defined(HAVE_PRIVATE_MT_NO_MDP)
void mdp_common_init(void)
{
}

2
baseboard/octopus/baseboard.c
View File

@ -363,5 +363,5 @@ void board_hibernate(void)
* with any PD contract renegotiation, and tcpm to put TCPC into low
* power mode if required.
*/
msleep(1500);
crec_msleep(1500);
}

4
baseboard/octopus/variant_usbc_ec_tcpcs.c
View File

@ -65,7 +65,7 @@ static void board_it83xx_hpd_status(const struct usb_mux *me,
gpio_set_level(gpio, hpd_lvl);
if (hpd_irq) {
gpio_set_level(gpio, 1);
msleep(1);
crec_msleep(1);
gpio_set_level(gpio, hpd_lvl);
}
}
@ -144,7 +144,7 @@ void board_reset_pd_mcu(void)
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
msleep(PS8XXX_RESET_DELAY_MS);
crec_msleep(PS8XXX_RESET_DELAY_MS);
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);

8
baseboard/octopus/variant_usbc_standalone_tcpcs.c
View File

@ -180,7 +180,7 @@ void board_reset_pd_mcu(void)
* enough charge to last the reboot as well
*/
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
msleep(PS8XXX_RESET_DELAY_MS);
crec_msleep(PS8XXX_RESET_DELAY_MS);
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
}
#else
@ -197,9 +197,9 @@ void board_reset_pd_mcu(void)
if (gpio_is_implemented(GPIO_USB_C0_PD_RST) &&
battery_is_present() == BP_YES) {
gpio_set_level(GPIO_USB_C0_PD_RST, 1);
msleep(ANX74XX_RESET_HOLD_MS);
crec_msleep(ANX74XX_RESET_HOLD_MS);
gpio_set_level(GPIO_USB_C0_PD_RST, 0);
msleep(ANX74XX_RESET_FINISH_MS);
crec_msleep(ANX74XX_RESET_FINISH_MS);
}
#endif
/*
@ -212,7 +212,7 @@ void board_reset_pd_mcu(void)
* enough charge to last the reboot as well
*/
gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0);
msleep(PS8XXX_RESET_DELAY_MS);
crec_msleep(PS8XXX_RESET_DELAY_MS);
gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
} else {
CPRINTS("Skipping C1 TCPC reset because no battery");

4
baseboard/trogdor/usb_pd_policy.c
View File

@ -231,12 +231,12 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
uint64_t now = get_time().val;
/* Wait for the minimum spacing between IRQ_HPD if needed */
if (now < svdm_hpd_deadline[port])
usleep(svdm_hpd_deadline[port] - now);
crec_usleep(svdm_hpd_deadline[port] - now);
/* Generate IRQ_HPD pulse */
CPRINTS("C%d: Recv IRQ. HPD->0", port);
gpio_set_level(hpd, 0);
usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
crec_usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
gpio_set_level(hpd, 1);
CPRINTS("C%d: Recv IRQ. HPD->1", port);

2
baseboard/volteer/usb_pd_policy.c
View File

@ -201,7 +201,7 @@ static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
* before sending the reply without violating that timer.
*/
if (!usb_mux_set_completed(port))
usleep(PD_T_VDM_E_MODE / 2);
crec_usleep(PD_T_VDM_E_MODE / 2);
CPRINTS("UFP Enter TBT mode");
return 1; /* ACK */

4
baseboard/zork/baseboard.c
View File

@ -230,7 +230,7 @@ void board_hibernate(void)
pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
/* Give PD task and PPC chip time to get to 5V */
msleep(900);
crec_msleep(900);
}
zork_board_hibernate();
@ -309,7 +309,7 @@ void board_pwrbtn_to_pch(int level)
* From measurement, wait 80 ms for RSMRST_L to rise after
* S5_PGOOD.
*/
msleep(80);
crec_msleep(80);
if (!gpio_get_level(GPIO_S5_PGOOD))
ccprints("Error: pwrbtn S5_PGOOD low");

4
baseboard/zork/variant_trembyle.c
View File

@ -275,11 +275,11 @@ static void reset_nct38xx_port(int port)
return;
gpio_set_level(reset_gpio_l, 0);
msleep(NCT38XX_RESET_HOLD_DELAY_MS);
crec_msleep(NCT38XX_RESET_HOLD_DELAY_MS);
gpio_set_level(reset_gpio_l, 1);
nct38xx_reset_notify(port);
if (NCT3807_RESET_POST_DELAY_MS != 0)
msleep(NCT3807_RESET_POST_DELAY_MS);
crec_msleep(NCT3807_RESET_POST_DELAY_MS);
}
void board_reset_pd_mcu(void)

48
bazel/all_targets.generated.bzl
View File

@ -408,6 +408,15 @@ def all_targets():
core = "riscv-rv32i",
zephyr = False,
)
ec_target(
name = "cherry_scp_core1",
baseboard = "mtscp-rv32i",
board = "cherry_scp_core1",
chip = "mt_scp",
core = "riscv-rv32i",
real_board = "cherry_scp",
zephyr = False,
)
ec_target(
name = "chinchou",
board = "chinchou",
@ -900,6 +909,23 @@ def all_targets():
name = "geralt",
board = "geralt",
)
ec_target(
name = "geralt_scp",
baseboard = "mtscp-rv32i",
board = "geralt_scp",
chip = "mt_scp",
core = "riscv-rv32i",
zephyr = False,
)
ec_target(
name = "geralt_scp_core1",
baseboard = "mtscp-rv32i",
board = "geralt_scp_core1",
chip = "mt_scp",
core = "riscv-rv32i",
real_board = "geralt_scp",
zephyr = False,
)
ec_target(
name = "gimble",
baseboard = "brya",
@ -949,6 +975,10 @@ def all_targets():
name = "gothrax",
board = "gothrax",
)
ec_target(
name = "greenbayupoc",
board = "greenbayupoc",
)
ec_target(
name = "grunt",
baseboard = "grunt",
@ -1273,6 +1303,11 @@ def all_targets():
core = "cortex-m",
zephyr = False,
)
ec_target(
name = "kyogre",
board = "kyogre",
extra_modules = ["cmsis"],
)
ec_target(
name = "lalala",
baseboard = "keeby",
@ -2004,6 +2039,10 @@ def all_targets():
core = "cortex-m",
zephyr = False,
)
ec_target(
name = "skitty",
board = "skitty",
)
ec_target(
name = "skyrim",
board = "skyrim",
@ -2088,6 +2127,11 @@ def all_targets():
core = "cortex-m",
zephyr = False,
)
ec_target(
name = "sundance",
board = "sundance",
extra_modules = ["cmsis"],
)
ec_target(
name = "sweetberry",
board = "sweetberry",
@ -2366,6 +2410,10 @@ def all_targets():
core = "cortex-m",
zephyr = False,
)
ec_target(
name = "wugtrio",
board = "wugtrio",
)
ec_target(
name = "xivu",
board = "xivu",

4
board/ambassador/board.c
View File

@ -609,10 +609,10 @@ void board_reset_pd_mcu(void)
TCPC_FLAGS_RESET_ACTIVE_HIGH);
gpio_set_level(GPIO_USB_C0_TCPC_RST, level);
msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
crec_msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
gpio_set_level(GPIO_USB_C0_TCPC_RST, !level);
if (BOARD_TCPC_C0_RESET_POST_DELAY)
msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
crec_msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
}
int board_set_active_charge_port(int port)

2
board/anahera/led.c
View File

@ -218,6 +218,6 @@ void led_task(void *u)
* the duration exceeds the tick time, then don't sleep.
*/
if (task_duration < LED_TICK_INTERVAL_MS)
usleep(LED_TICK_INTERVAL_MS - task_duration);
crec_usleep(LED_TICK_INTERVAL_MS - task_duration);
}
}

8
board/anahera/usbc_config.c
View File

@ -187,10 +187,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -203,7 +203,7 @@ void board_reset_pd_mcu(void)
/*
* delay for power-on to reset-off and min. assertion time
*/
msleep(NCT38XX_RESET_HOLD_DELAY_MS);
crec_msleep(NCT38XX_RESET_HOLD_DELAY_MS);
gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
gpio_set_level(GPIO_USB_C1_TCPC_RST_ODL, 1);
@ -213,7 +213,7 @@ void board_reset_pd_mcu(void)
/* wait for chips to come up */
if (NCT3807_RESET_POST_DELAY_MS != 0)
msleep(NCT3807_RESET_POST_DELAY_MS);
crec_msleep(NCT3807_RESET_POST_DELAY_MS);
}
static void board_tcpc_init(void)

2
board/atlas/board.c
View File

@ -216,7 +216,7 @@ const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_USB_PD_RST_L, 0);
msleep(PS8XXX_RST_L_RST_H_DELAY_MS);
crec_msleep(PS8XXX_RST_L_RST_H_DELAY_MS);
gpio_set_level(GPIO_USB_PD_RST_L, 1);
}

12
board/aurash/usbc_config.c
View File

@ -185,10 +185,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -200,9 +200,9 @@ __override int bb_retimer_reset(const struct usb_mux *me)
* QS Silicon is complete
*/
bb_retimer_power_enable(me, false);
msleep(5);
crec_msleep(5);
bb_retimer_power_enable(me, true);
msleep(25);
crec_msleep(25);
return EC_SUCCESS;
}
@ -223,13 +223,13 @@ void board_reset_pd_mcu(void)
* delay for power-on to reset-off and min. assertion time
*/
msleep(20);
crec_msleep(20);
gpio_set_level(tcpc_rst, 1);
/* wait for chips to come up */
msleep(50);
crec_msleep(50);
}
static void enable_ioex(int ioex)

8
board/baklava/board.c
View File

@ -189,9 +189,9 @@ void board_reset_pd_mcu(void)
cflush();
gpio_set_level(GPIO_USBC_UF_RESET_L, 0);
msleep(PS8805_FW_INIT_DELAY_MS);
crec_msleep(PS8805_FW_INIT_DELAY_MS);
gpio_set_level(GPIO_USBC_UF_RESET_L, 1);
msleep(PS8805_FW_INIT_DELAY_MS);
crec_msleep(PS8805_FW_INIT_DELAY_MS);
}
void board_enable_usbc_interrupts(void)
@ -340,10 +340,10 @@ static int command_dplane(int argc, const char **argv)
/* put MST into reset */
gpio_set_level(GPIO_MST_RST_L, 0);
msleep(1);
crec_msleep(1);
/* Set lane control to requested level */
gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, lane == 2 ? 1 : 0);
msleep(1);
crec_msleep(1);
/* Take MST out of reset */
gpio_set_level(GPIO_MST_RST_L, 1);

8
board/banshee/usbc_config.c
View File

@ -368,10 +368,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -386,7 +386,7 @@ void board_reset_pd_mcu(void)
/*
* delay for power-on to reset-off and min. assertion time
*/
msleep(NCT38XX_RESET_HOLD_DELAY_MS);
crec_msleep(NCT38XX_RESET_HOLD_DELAY_MS);
gpio_set_level(GPIO_USB_C0_C1_TCPC_RST_ODL, 1);
gpio_set_level(GPIO_USB_C2_C3_TCPC_RST_ODL, 1);
@ -397,7 +397,7 @@ void board_reset_pd_mcu(void)
/* wait for chips to come up */
if (NCT3808_RESET_POST_DELAY_MS != 0)
msleep(NCT3808_RESET_POST_DELAY_MS);
crec_msleep(NCT3808_RESET_POST_DELAY_MS);
}
static void board_tcpc_init(void)

2
board/beadrix/board.c
View File

@ -133,7 +133,7 @@ __override void board_pulse_entering_rw(void)
*/
gpio_set_level(GPIO_EC_ENTERING_RW, 1);
gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
usleep(MSEC);
crec_usleep(MSEC);
gpio_set_level(GPIO_EC_ENTERING_RW, 0);
gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
}

2
board/beetley/board.c
View File

@ -347,7 +347,7 @@ __override void board_pulse_entering_rw(void)
*/
gpio_set_level(GPIO_EC_ENTERING_RW, 1);
gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
usleep(MSEC);
crec_usleep(MSEC);
gpio_set_level(GPIO_EC_ENTERING_RW, 0);
gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
}

2
board/bellis/board.c
View File

@ -326,7 +326,7 @@ static void board_init(void)
/* If the reset cause is external, pulse PMIC force reset. */
if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
msleep(100);
crec_msleep(100);
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
}

2
board/berknip/board.c
View File

@ -95,7 +95,7 @@ static void board_chipset_resume(void)
if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
msleep(PI3HDX1204_POWER_ON_DELAY_MS);
crec_msleep(PI3HDX1204_POWER_ON_DELAY_MS);
pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
check_hdmi_hpd_status());
}

2
board/blipper/board.c
View File

@ -499,7 +499,7 @@ __override void board_pulse_entering_rw(void)
*/
gpio_set_level(GPIO_EC_ENTERING_RW, 1);
gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
usleep(MSEC);
crec_usleep(MSEC);
gpio_set_level(GPIO_EC_ENTERING_RW, 0);
gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
}

5
board/boldar/board.c
View File

@ -312,9 +312,10 @@ static void ps8815_reset(void)
int val;
gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
crec_msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
PS8815_PWR_H_RST_H_DELAY_MS));
gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
msleep(PS8815_FW_INIT_DELAY_MS);
crec_msleep(PS8815_FW_INIT_DELAY_MS);
/*
* b/144397088

2
board/boten/board.c
View File

@ -135,7 +135,7 @@ __override void board_pulse_entering_rw(void)
*/
gpio_set_level(GPIO_EC_ENTERING_RW, 1);
gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
usleep(MSEC);
crec_usleep(MSEC);
gpio_set_level(GPIO_EC_ENTERING_RW, 0);
gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
}

12
board/brask/usbc_config.c
View File

@ -237,10 +237,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -252,9 +252,9 @@ __override int bb_retimer_reset(const struct usb_mux *me)
* QS Silicon is complete
*/
bb_retimer_power_enable(me, false);
msleep(5);
crec_msleep(5);
bb_retimer_power_enable(me, true);
msleep(25);
crec_msleep(25);
return EC_SUCCESS;
}
@ -276,14 +276,14 @@ void board_reset_pd_mcu(void)
* delay for power-on to reset-off and min. assertion time
*/
msleep(20);
crec_msleep(20);
gpio_set_level(tcpc_rst, 1);
gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 1);
/* wait for chips to come up */
msleep(50);
crec_msleep(50);
}
static void enable_ioex(int ioex)

8
board/brya/usbc_config.c
View File

@ -316,10 +316,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -348,7 +348,7 @@ void board_reset_pd_mcu(void)
* delay for power-on to reset-off and min. assertion time
*/
msleep(20);
crec_msleep(20);
gpio_set_level(tcpc_rst, 1);
if (ec_cfg_usb_db_type() != DB_USB_ABSENT) {
@ -358,7 +358,7 @@ void board_reset_pd_mcu(void)
/* wait for chips to come up */
msleep(50);
crec_msleep(50);
}
static void board_tcpc_init(void)

2
board/bugzzy/board.c
View File

@ -801,7 +801,7 @@ static void panel_power_change_deferred(void)
}
if (board_id < 4) {
gpio_set_level(GPIO_EN_LCD_ENP, signal);
msleep(1);
crec_msleep(1);
gpio_set_level(GPIO_EN_LCD_ENN, signal);
} else if (signal != 0) {
i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,

2
board/burnet/board.c
View File

@ -521,7 +521,7 @@ static void board_init(void)
/* If the reset cause is external, pulse PMIC force reset. */
if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
msleep(100);
crec_msleep(100);
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
}

6
board/c2d2/board.c
View File

@ -814,7 +814,7 @@ static int command_h1_reset(int argc, const char **argv)
VREF_MON_DIS_H1_RST_HELD,
"H1 reset");
if (rv == EC_SUCCESS) {
msleep(100);
crec_msleep(100);
rv = command_vref_alternate(
c, cmd_off, GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
@ -891,7 +891,7 @@ static inline void drain_vref_lines(void)
/* Ensure we have enough time to drain line. Not in mutex */
mutex_unlock(&vref_bus_state_mutex);
msleep(5);
crec_msleep(5);
mutex_lock(&vref_bus_state_mutex);
if (vref_monitor_disable) {
mutex_unlock(&vref_bus_state_mutex);
@ -916,7 +916,7 @@ static inline void drain_vref_lines(void)
mutex_unlock(&vref_bus_state_mutex);
/* Ensure we have enough time to charge line up to real voltage */
msleep(10);
crec_msleep(10);
}
/* This if forward declared as a deferred function above */

2
board/casta/board.c
View File

@ -127,7 +127,7 @@ void i2c_start_xfer_notify(const int port, const uint16_t addr_flags)
if (time_delta_us >= BATTERY_FREE_MIN_DELTA_US)
return;
usleep(BATTERY_FREE_MIN_DELTA_US - time_delta_us);
crec_usleep(BATTERY_FREE_MIN_DELTA_US - time_delta_us);
}
void i2c_end_xfer_notify(const int port, const uint16_t addr_flags)

2
board/cerise/board.c
View File

@ -311,7 +311,7 @@ static void board_init(void)
/* If the reset cause is external, pulse PMIC force reset. */
if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
msleep(100);
crec_msleep(100);
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
}

2
board/cherry_scp/OWNERS Normal file
View File

@ -0,0 +1,2 @@
# MT8188 / Geralt SCP
fshao@chromium.org

48
board/cherry_scp/board.h
View File

@ -10,12 +10,53 @@
#include "baseboard.h"
#define SCP_CORE1_RAM_START 0xa0000
#define SCP_CORE1_RAM_SIZE 0x1f000 /* 124K */
#define SCP_CORE1_RAM_PADDING 0xc00 /* for 4K-alignment */
#ifdef BOARD_CHERRY_SCP_CORE1
/*
* RW only, no flash
* +-------------------- 0xa0000 + 0
* | ROM vectortable, .text, .rodata, .data LMA
* +-------------------- 0xa0000 + 0x14000 = 0xb4000
* | RAM .bss, .data
* +-------------------- 0xa0000 + 0x1ec00 = 0xbec00
* | Reserved (padding for 1k-alignment)
* +-------------------- 0xa0000 + 0x1edb0 = 0xbedb0
* | IPI shared buffer with AP (288 + 8) * 2
* +-------------------- 0xa0000 + 0x1f000 = 0xbf000
*
* [Memory remap]
* SCP core 1 has registers to remap core view addresses by SCP bus. This is
* useful to boot SCP core 1 because SCP core 0/1 both default read instructions
* on address 0 when boot up. The remap registers configure by kernel driver
* before release reset of SCP core 1.
*/
#define CONFIG_ROM_BASE 0x0
#define CONFIG_RAM_BASE 0x14000
#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
#define CONFIG_RAM_SIZE \
((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
/*
* SCP_FW_END is used to calc the base of IPI buffer for AP.
*/
#define SCP_FW_END SCP_CORE1_RAM_SIZE
#else
/*
* RW only, no flash
* +-------------------- 0x0
* | ROM vectortable, .text, .rodata, .data LMA
* +-------------------- 0x6f000
* | RAM .bss, .data
* +-------------------- 0xaf000 (4k-alignment)
* | SCP core1 boot code
* +-------------------- 0xbf000 (4k-alignment)
* | Reserved (padding for 4k-alignment)
* +-------------------- 0xbfc00
* | Reserved (padding for 1k-alignment)
* +-------------------- 0xbfdb0
@ -25,9 +66,12 @@
#define CONFIG_ROM_BASE 0x0
#define CONFIG_RAM_BASE 0x6f000
#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
#define CONFIG_RAM_SIZE \
((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
#define CONFIG_RAM_SIZE \
((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE - \
SCP_CORE1_RAM_SIZE - SCP_CORE1_RAM_PADDING)
#define SCP_FW_END 0xc0000
#endif /* BOARD_CHERRY_SCP_CORE1 */
#endif /* __CROS_EC_BOARD_H */

16
board/cherry_scp/ec.tasklist
View File

@ -7,12 +7,20 @@
* See CONFIG_TASK_LIST in config.h for details.
*/
#ifdef BOARD_CHERRY_SCP_CORE1
#define FEATURE_TASK_LIST \
TASK_ALWAYS(CAM_SERVICE, cam_service_task, NULL, 6016)
#else
#define FEATURE_TASK_LIST \
TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, 4096) \
TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, 4096) \
TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, 4096)
#endif
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, 4096) \
TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, 4096) \
TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, 4096) \
FEATURE_TASK_LIST \
TASK_ALWAYS(SR, sr_task, NULL, TASK_STACK_SIZE)

1
board/cherry_scp_core1 Symbolic link
View File

@ -0,0 +1 @@
cherry_scp

5
board/chronicler/usbc_config.c
View File

@ -132,9 +132,10 @@ static void ps8815_reset(void)
int val;
gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
crec_msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
PS8815_PWR_H_RST_H_DELAY_MS));
gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
msleep(PS8815_FW_INIT_DELAY_MS);
crec_msleep(PS8815_FW_INIT_DELAY_MS);
/*
* b/144397088

2
board/coachz/board.c
View File

@ -606,7 +606,7 @@ void board_reset_pd_mcu(void)
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
msleep(PS8XXX_RESET_DELAY_MS);
crec_msleep(PS8XXX_RESET_DELAY_MS);
gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
}

5
board/collis/board.c
View File

@ -417,9 +417,10 @@ static void ps8815_reset(int port)
}
gpio_set_level(ps8xxx_rst_odl, 0);
msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
crec_msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
PS8815_PWR_H_RST_H_DELAY_MS));
gpio_set_level(ps8xxx_rst_odl, 1);
msleep(PS8815_FW_INIT_DELAY_MS);
crec_msleep(PS8815_FW_INIT_DELAY_MS);
CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);

12
board/constitution/usbc_config.c
View File

@ -200,10 +200,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -215,9 +215,9 @@ __override int bb_retimer_reset(const struct usb_mux *me)
* QS Silicon is complete
*/
bb_retimer_power_enable(me, false);
msleep(5);
crec_msleep(5);
bb_retimer_power_enable(me, true);
msleep(25);
crec_msleep(25);
return EC_SUCCESS;
}
@ -238,13 +238,13 @@ void board_reset_pd_mcu(void)
* delay for power-on to reset-off and min. assertion time
*/
msleep(20);
crec_msleep(20);
gpio_set_level(tcpc_rst, 1);
/* wait for chips to come up */
msleep(50);
crec_msleep(50);
}
void pd_reset_deferred(void)

18
board/coral/board.c
View File

@ -327,14 +327,14 @@ void board_set_tcpc_power_mode(int port, int mode)
switch (mode) {
case ANX74XX_NORMAL_MODE:
gpio_set_level(GPIO_EN_USB_TCPC_PWR, 1);
msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
break;
case ANX74XX_STANDBY_MODE:
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
crec_msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
gpio_set_level(GPIO_EN_USB_TCPC_PWR, 0);
msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
break;
default:
break;
@ -356,7 +356,7 @@ void board_reset_pd_mcu(void)
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
/* TCPC1 (ps8751) requires 1ms reset down assertion */
msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
crec_msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
/* Deassert reset to TCPC1 */
gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1);
@ -366,7 +366,7 @@ void board_reset_pd_mcu(void)
/*
* anx3429 requires 10ms reset/power down assertion
*/
msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
}
@ -378,7 +378,7 @@ static void board_tcpc_init(void)
/* Wait for disconnected battery to wake up */
while (battery_hw_present() == BP_YES &&
battery_is_present() == BP_NO) {
usleep(100 * MSEC);
crec_usleep(100 * MSEC);
/* Give up waiting after 2 seconds */
if (++count > 20)
break;
@ -812,7 +812,7 @@ void board_hibernate(void)
chipset_do_shutdown();
/* Added delay to allow AP to settle down */
msleep(100);
crec_msleep(100);
/* Enable both the VBUS & VCC ports before entering PG3 */
bd9995x_select_input_port(BD9995X_CHARGE_PORT_BOTH, 1);
@ -870,7 +870,7 @@ static int board_read_version(enum adc_channel chan)
/* ID/SKU enable is active high */
gpio_set_flags(GPIO_EC_BRD_ID_EN, GPIO_OUT_HIGH);
/* Wait to allow cap charge */
msleep(1);
crec_msleep(1);
mv = adc_read_channel(chan);
CPRINTS("ID/SKU ADC %d = %d mV", chan, mv);
/* Disable ID/SKU circuit */
@ -937,7 +937,7 @@ static void print_form_factor_list(int low, int high)
SKU_IS_CONVERTIBLE(id) ? "Convertible" : "Clamshell");
/* Don't print too many lines at once */
if (!(++count % 5))
msleep(20);
crec_msleep(20);
}
}

8
board/crota/usbc_config.c
View File

@ -252,10 +252,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -272,13 +272,13 @@ void board_reset_pd_mcu(void)
* delay for power-on to reset-off and min. assertion time
*/
msleep(20);
crec_msleep(20);
gpio_set_level(tcpc_rst, 1);
/* wait for chips to come up */
msleep(50);
crec_msleep(50);
}
static void board_tcpc_init(void)

6
board/dalboz/board.c
View File

@ -201,7 +201,7 @@ static void board_chipset_resume(void)
if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
ioex_set_level(IOEX_EN_PWR_HDMI_DB, 1);
msleep(PI3HDX1204_POWER_ON_DELAY_MS);
crec_msleep(PI3HDX1204_POWER_ON_DELAY_MS);
pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 1);
}
}
@ -463,11 +463,11 @@ static void reset_nct38xx_port(int port)
return;
gpio_set_level(reset_gpio_l, 0);
msleep(NCT38XX_RESET_HOLD_DELAY_MS);
crec_msleep(NCT38XX_RESET_HOLD_DELAY_MS);
gpio_set_level(reset_gpio_l, 1);
nct38xx_reset_notify(port);
if (NCT3807_RESET_POST_DELAY_MS != 0)
msleep(NCT3807_RESET_POST_DELAY_MS);
crec_msleep(NCT3807_RESET_POST_DELAY_MS);
}
void board_reset_pd_mcu(void)

2
board/damu/board.c
View File

@ -311,7 +311,7 @@ static void board_init(void)
/* If the reset cause is external, pulse PMIC force reset. */
if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
msleep(100);
crec_msleep(100);
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
}

5
board/delbin/board.c
View File

@ -304,9 +304,10 @@ static void ps8815_reset(int port)
}
gpio_set_level(ps8xxx_rst_odl, 0);
msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
crec_msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
PS8815_PWR_H_RST_H_DELAY_MS));
gpio_set_level(ps8xxx_rst_odl, 1);
msleep(PS8815_FW_INIT_DELAY_MS);
crec_msleep(PS8815_FW_INIT_DELAY_MS);
CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);

4
board/dirinboz/board.c
View File

@ -293,11 +293,11 @@ static void reset_nct38xx_port(int port)
return;
gpio_set_level(reset_gpio_l, 0);
msleep(NCT38XX_RESET_HOLD_DELAY_MS);
crec_msleep(NCT38XX_RESET_HOLD_DELAY_MS);
gpio_set_level(reset_gpio_l, 1);
nct38xx_reset_notify(port);
if (NCT3807_RESET_POST_DELAY_MS != 0)
msleep(NCT3807_RESET_POST_DELAY_MS);
crec_msleep(NCT3807_RESET_POST_DELAY_MS);
}
void board_reset_pd_mcu(void)

24
board/dita/sensors.c
View File

@ -73,12 +73,12 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
#define THERMAL_MEMORY \
{ \
.temp_host = { \
[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
}, \
.temp_host_release = { \
[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
}, \
.temp_fan_off = 0, \
.temp_fan_max = 0, \
@ -89,12 +89,12 @@ __maybe_unused static const struct ec_thermal_config thermal_memory =
#define THERMAL_SOC \
{ \
.temp_host = { \
[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
}, \
.temp_host_release = { \
[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
}, \
.temp_fan_off = 0, \
.temp_fan_max = 0, \
@ -104,12 +104,12 @@ __maybe_unused static const struct ec_thermal_config thermal_soc = THERMAL_SOC;
#define THERMAL_AMBIENT \
{ \
.temp_host = { \
[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
}, \
.temp_host_release = { \
[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
}, \
.temp_fan_off = 0, \
.temp_fan_max = 0, \

4
board/dooly/board.c
View File

@ -830,11 +830,11 @@ void board_reset_pd_mcu(void)
gpio_set_level(GPIO_USB_C0_TCPC_RST, level0);
gpio_set_level(GPIO_USB_C1_TCPC_RST, level1);
msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
crec_msleep(BOARD_TCPC_C0_RESET_HOLD_DELAY);
gpio_set_level(GPIO_USB_C0_TCPC_RST, !level0);
gpio_set_level(GPIO_USB_C1_TCPC_RST, !level1);
if (BOARD_TCPC_C0_RESET_POST_DELAY)
msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
crec_msleep(BOARD_TCPC_C0_RESET_POST_DELAY);
}
int board_set_active_charge_port(int port)

2
board/drawcia/board.c
View File

@ -539,7 +539,7 @@ __override void board_pulse_entering_rw(void)
*/
gpio_set_level(GPIO_EC_ENTERING_RW, 1);
gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
usleep(MSEC);
crec_usleep(MSEC);
gpio_set_level(GPIO_EC_ENTERING_RW, 0);
gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
}

5
board/eldrid/board.c
View File

@ -362,9 +362,10 @@ static void ps8815_reset(void)
int val;
gpio_set_level(ps8xxx_rst_odl, 0);
msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
crec_msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
PS8815_PWR_H_RST_H_DELAY_MS));
gpio_set_level(ps8xxx_rst_odl, 1);
msleep(PS8815_FW_INIT_DELAY_MS);
crec_msleep(PS8815_FW_INIT_DELAY_MS);
/*
* b/144397088

5
board/elemi/board.c
View File

@ -264,9 +264,10 @@ static void ps8815_reset(void)
int val;
gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
crec_msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
PS8815_PWR_H_RST_H_DELAY_MS));
gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
msleep(PS8815_FW_INIT_DELAY_MS);
crec_msleep(PS8815_FW_INIT_DELAY_MS);
/*
* b/144397088

8
board/eve/battery.c
View File

@ -554,7 +554,7 @@ static int board_battery_disable_cto(uint32_t value)
board_battery_write_flash(SB_VENDOR_ENABLED_PROTECT_C,
EXPECTED_CTO_DISABLE_VALUE, 1);
/* After flash write, allow time for it to complete */
msleep(100);
crec_msleep(100);
/* Read the current protect_c register value */
if (board_battery_read_flash(SB_VENDOR_ENABLED_PROTECT_C, 1,
&protect_c) == EC_SUCCESS)
@ -565,7 +565,7 @@ static int board_battery_disable_cto(uint32_t value)
if (board_battery_seal()) {
/* If failed, then wait one more time and seal again */
msleep(100);
crec_msleep(100);
if (board_battery_seal())
return EC_RES_ERROR;
}
@ -591,7 +591,7 @@ static int board_battery_fix_otd_recovery_temp(uint32_t value)
board_battery_write_flash(SB_VENDOR_OTD_RECOVERY_TEMP,
EXPECTED_OTD_RECOVERY_TEMP, 2);
/* After flash write, allow time for it to complete */
msleep(100);
crec_msleep(100);
/* Read the current OTD recovery temperature */
if (!board_battery_read_flash(SB_VENDOR_OTD_RECOVERY_TEMP, 2,
(uint8_t *)&otd_recovery_temp))
@ -602,7 +602,7 @@ static int board_battery_fix_otd_recovery_temp(uint32_t value)
if (board_battery_seal()) {
/* If failed, then wait one more time and seal again */
msleep(100);
crec_msleep(100);
if (board_battery_seal())
return EC_RES_ERROR;
}

20
board/eve/board.c
View File

@ -282,25 +282,25 @@ void board_set_tcpc_power_mode(int port, int mode)
case 0:
if (mode) {
gpio_set_level(GPIO_USB_C0_TCPC_PWR, 1);
msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
} else {
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
crec_msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
gpio_set_level(GPIO_USB_C0_TCPC_PWR, 0);
msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
}
break;
case 1:
if (mode) {
gpio_set_level(GPIO_USB_C1_TCPC_PWR, 1);
msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
} else {
gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
crec_msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
gpio_set_level(GPIO_USB_C1_TCPC_PWR, 0);
msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
}
break;
}
@ -311,15 +311,15 @@ void board_reset_pd_mcu(void)
/* Assert reset */
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
crec_msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
/* Disable power */
gpio_set_level(GPIO_USB_C0_TCPC_PWR, 0);
gpio_set_level(GPIO_USB_C1_TCPC_PWR, 0);
msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
/* Enable power */
gpio_set_level(GPIO_USB_C0_TCPC_PWR, 1);
gpio_set_level(GPIO_USB_C1_TCPC_PWR, 1);
msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
crec_msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
/* Deassert reset */
gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
@ -333,7 +333,7 @@ void board_tcpc_init(void)
/* Wait for disconnected battery to wake up */
while (battery_hw_present() == BP_YES &&
battery_is_present() == BP_NO) {
usleep(100 * MSEC);
crec_usleep(100 * MSEC);
/* Give up waiting after 2 seconds */
if (++count > 20)
break;

6
board/eve/led.c
View File

@ -398,7 +398,7 @@ static void led_change_color(void)
/* Move one step in the transition table */
led_adjust_color_step(i);
}
msleep(LED_STEP_MSEC);
crec_msleep(LED_STEP_MSEC);
}
}
@ -595,7 +595,7 @@ void led_task(void *u)
led_init();
usleep(SECOND);
crec_usleep(SECOND);
while (1) {
enum led_pattern pattern_desired[LED_BOTH];
@ -626,7 +626,7 @@ void led_task(void *u)
* the duration exceeds the tick time, then don't sleep.
*/
if (task_duration < LED_TICK_TIME)
usleep(LED_TICK_TIME - task_duration);
crec_usleep(LED_TICK_TIME - task_duration);
}
}

2
board/ezkinil/board.c
View File

@ -645,7 +645,7 @@ static void board_chipset_resume(void)
if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
msleep(PI3HDX1204_POWER_ON_DELAY_MS);
crec_msleep(PI3HDX1204_POWER_ON_DELAY_MS);
pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
check_hdmi_hpd_status());
}

8
board/felwinter/usbc_config.c
View File

@ -252,10 +252,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
* Allow 1ms time for the retimer to power up lc_domain
* which powers I2C controller within retimer
*/
msleep(1);
crec_msleep(1);
} else {
gpio_or_ioex_set_level(rst_signal, 0);
msleep(1);
crec_msleep(1);
}
return EC_SUCCESS;
}
@ -276,7 +276,7 @@ void board_reset_pd_mcu(void)
* delay for power-on to reset-off and min. assertion time
*/
msleep(20);
crec_msleep(20);
gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 1);
gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
@ -286,7 +286,7 @@ void board_reset_pd_mcu(void)
/* wait for chips to come up */
msleep(50);
crec_msleep(50);
}
static void enable_ioex(int ioex)

2
board/fennel/board.c
View File

@ -315,7 +315,7 @@ static void board_init(void)
/* If the reset cause is external, pulse PMIC force reset. */
if (system_get_reset_flags() == EC_RESET_FLAG_RESET_PIN) {
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
msleep(100);
crec_msleep(100);
gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 1);
}

2
board/fizz/board.c
View File

@ -248,7 +248,7 @@ const int usb_port_enable[USB_PORT_COUNT] = {
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
msleep(1);
crec_msleep(1);
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
}

10
board/fluffy/board.c
View File

@ -92,12 +92,12 @@ static int command_cc_flip(int argc, const char *argv[])
gpio_set_level(enabled_port, 0);
gpio_set_level(GPIO_EN_USB_MUX2, 0);
/* Wait long enough for CC to discharge. */
usleep(500 * MSEC);
crec_usleep(500 * MSEC);
}
gpio_set_level(GPIO_EN_CC_FLIP, enable);
/* Allow some time for new CC configuration to settle. */
usleep(500 * MSEC);
crec_usleep(500 * MSEC);
if (output_en) {
gpio_set_level(enabled_port, 1);
@ -213,10 +213,10 @@ static void board_init(void)
/* Do a sweeping LED dance. */
for (enum led_ch led = 0; led < LED_COUNT; led++) {
set_led(led, 1);
msleep(100);
crec_msleep(100);
}
msleep(500);
crec_msleep(500);
for (enum led_ch led = 0; led < LED_COUNT; led++)
set_led(led, 0);
@ -293,7 +293,7 @@ static int command_portctl(int argc, const char **argv)
CPRINTS("Port %d: disabled", enabled_port - GPIO_EN_C0);
/* Allow time for an "unplug" to allow VBUS and CC to fall. */
usleep(1 * SECOND);
crec_usleep(1 * SECOND);
/*
* The USB 2.0 lines are arranged using 3x 8:1 muxes. Ports 0-7 are

16
board/fusb307bgevb/lcd.c
View File

@ -33,10 +33,10 @@ static void expander_write(uint8_t data)
static void pulse_enable(uint8_t data)
{
expander_write(data | LCD_EN); /* En high */
usleep(1); /* enable pulse must be >450ns */
crec_usleep(1); /* enable pulse must be >450ns */
expander_write(data & ~LCD_EN); /* En low */
usleep(50); /* commands need > 37us to settle */
crec_usleep(50); /* commands need > 37us to settle */
}
static void write_4bits(uint8_t value)
@ -64,7 +64,7 @@ static void command(uint8_t value)
void lcd_clear(void)
{
command(LCD_CLEAR_DISPLAY); /* clear display, set cursor to zero */
usleep(2000); /* this command takes a long time! */
crec_usleep(2000); /* this command takes a long time! */
}
void lcd_set_cursor(uint8_t col, uint8_t row)
@ -124,12 +124,12 @@ void lcd_init(uint8_t cols, uint8_t rows, uint8_t dotsize)
* above 2.7V before sending commands. Arduino can turn on way
* before 4.5V so we'll wait 50
*/
usleep(50);
crec_usleep(50);
/* Now we pull both RS and R/W low to begin commands */
/* reset expanderand turn backlight off (Bit 8 =1) */
expander_write(state.backlightval);
usleep(1000);
crec_usleep(1000);
/* put the LCD into 4 bit mode
* this is according to the hitachi HD44780 datasheet
@ -137,13 +137,13 @@ void lcd_init(uint8_t cols, uint8_t rows, uint8_t dotsize)
* we start in 8bit mode, try to set 4 bit mode
*/
write_4bits(0x03 << 4);
usleep(4500); /* wait min 4.1ms */
crec_usleep(4500); /* wait min 4.1ms */
/*second try */
write_4bits(0x03 << 4);
usleep(4500); /* wait min 4.1ms */
crec_usleep(4500); /* wait min 4.1ms */
/* third go! */
write_4bits(0x03 << 4);
usleep(150);
crec_usleep(150);
/* finally, set to 4-bit interface */
write_4bits(0x02 << 4);

7
board/gaelin/usbc_config.c
View File

@ -147,9 +147,10 @@ static void ps8815_reset(int port)
}
gpio_set_level(ps8xxx_rst_odl, 0);
msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
crec_msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
PS8815_PWR_H_RST_H_DELAY_MS));
gpio_set_level(ps8xxx_rst_odl, 1);
msleep(PS8815_FW_INIT_DELAY_MS);
crec_msleep(PS8815_FW_INIT_DELAY_MS);
CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
@ -157,7 +158,7 @@ static void ps8815_reset(int port)
CPRINTS("ps8815: reg 0x0f was %02x", val);
else {
CPRINTS("delay 10ms to make sure ps8815 is waken from idle");
msleep(10);
crec_msleep(10);
}
if (i2c_write8(i2c_port, i2c_addr_flags, 0x0f, 0x31) == EC_SUCCESS)

2
board/galtic/board.c
View File

@ -882,7 +882,7 @@ __override void board_pulse_entering_rw(void)
*/
gpio_set_level(GPIO_EC_ENTERING_RW, 1);
gpio_set_level(GPIO_EC_ENTERING_RW2, 1);
usleep(MSEC);
crec_usleep(MSEC);
gpio_set_level(GPIO_EC_ENTERING_RW, 0);
gpio_set_level(GPIO_EC_ENTERING_RW2, 0);
}

2
board/gelarshie/board.c
View File

@ -599,7 +599,7 @@ void board_reset_pd_mcu(void)
gpio_set_level(GPIO_USB_C0_PD_RST_L, 0);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
msleep(PS8XXX_RESET_DELAY_MS);
crec_msleep(PS8XXX_RESET_DELAY_MS);
gpio_set_level(GPIO_USB_C0_PD_RST_L, 1);
gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
}

2
board/geralt_scp/OWNERS Normal file
View File

@ -0,0 +1,2 @@
# MT8188 / Geralt SCP
fshao@chromium.org

71
board/geralt_scp/board.h Normal file
View File

@ -0,0 +1,71 @@
/* Copyright 2024 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Cherry SCP configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
#include "baseboard.h"
#define SCP_CORE1_RAM_START 0xd0000
#define SCP_CORE1_RAM_SIZE 0x2F000 /* 124K */
#ifdef BOARD_GERALT_SCP_CORE1
/*
* RW only, no flash
* +-------------------- 0xd0000 + 0
* | ROM vectortable, .text, .rodata, .data LMA
* +-------------------- 0xd0000 + 0x10000 = 0xe0000
* | RAM .bss, .data
* +-------------------- 0xd0000 + 0x1ec00 = 0xeec00
* | Reserved (padding for 1k-alignment)
* +-------------------- 0xd0000 + 0x1edb0 = 0xeedb0
* | IPI shared buffer with AP (288 + 8) * 2
* +-------------------- 0xd0000 + 0x2f000 = 0xff000
*
* [Memory remap]
* SCP core 1 has registers to remap core view addresses by SCP bus. This is
* useful to boot SCP core 1 because SCP core 0/1 both default read instructions
* on address 0 when boot up.
*
* The core address 0x0~0x10000 are translated to 0xaf000~0xbf000.
*/
#define CONFIG_ROM_BASE 0x0
#define CONFIG_RAM_BASE 0x10000
#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
#define CONFIG_RAM_SIZE \
((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
/* SCP_FW_END is used to calc the base of IPI buffer for AP.
* Provide AP view physical address which include the offset.
*/
#define SCP_FW_END SCP_CORE1_RAM_SIZE
#else
/*
* RW only, no flash
* +-------------------- 0x0
* | ROM vectortable, .text, .rodata, .data LMA
* +-------------------- 0x68000
* | RAM .bss, .data
* +-------------------- 0xbf000 (4k-alignment)
* | Reserved (padding for 1k-alignment)
* +-------------------- 0xbfdb0
* | IPI shared buffer with AP (288 + 8) * 2
* +-------------------- 0xc0000
*/
#define CONFIG_ROM_BASE 0x0
#define CONFIG_RAM_BASE 0x68000
#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
#define CONFIG_RAM_SIZE \
((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
#define SCP_FW_END 0xd0000
#endif /* BOARD_GERALT_SCP_CORE1 */
#endif /* __CROS_EC_BOARD_H */

12
board/geralt_scp/build.mk Normal file
View File

@ -0,0 +1,12 @@
# -*- makefile -*-
# Copyright 2024 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
CHIP:=mt_scp
CHIP_VARIANT:=mt8188
CHIP_FAMILY:=RV55
BASEBOARD:=mtscp-rv32i

27
board/geralt_scp/ec.tasklist Normal file
View File

@ -0,0 +1,27 @@
/* Copyright 2024 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* See CONFIG_TASK_LIST in config.h for details.
*/
#ifdef BOARD_GERALT_SCP_CORE1
#define FEATURE_TASK_LIST \
TASK_ALWAYS(IMG_SERVICE, img_service_task, NULL, 8192) \
TASK_ALWAYS(IMG_HANDLER, img_handler_task, NULL, 58368) \
TASK_ALWAYS(CAM_SERVICE, cam_service_task, NULL, 6016)
#else
#define FEATURE_TASK_LIST
#endif
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
FEATURE_TASK_LIST \
TASK_ALWAYS(SR, sr_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(VDEC_SERVICE, vdec_service_task, NULL, 4096) \
TASK_ALWAYS(VDEC_CORE_SERVICE, vdec_core_service_task, NULL, 4096) \
TASK_ALWAYS(VENC_SERVICE, venc_service_task, NULL, TRENTA_TASK_STACK_SIZE) \
TASK_ALWAYS(MDP_SERVICE, mdp_service_task, NULL, 4096)

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